Chip stacking structure with back power supply and preparation method thereof

Abstract

The invention provides a back power supply chip stacking structure and a preparation method thereof, the chip stacking structure comprises two chips which are bonded up and down, the two chips realize signal transmission through signal connection layers which are bonded with each other, and the two chips are connected with each other through a power rail and an embedded power layer. Only by forming the metal interconnection layer on the back of the first chip as the back power supply layer, the transistors of the upper chip and the lower chip can be powered, and transmission of electric signals is achieved. By means of the stacking design, the chip stacking structure can achieve the double number of transistors under the same area, for example, only a 14 nm manufacturing process can be used, the upper and lower transistor stacking method is combined, the number of transistors under a 7 nm manufacturing process is achieved, the same performance is achieved, and therefore the process cost is saved. In addition, the second chip bonded with the first chip also serves as a temporary slide glass, so that the temporary slide glass does not need to be additionally provided, and the manufacturing cost is further reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip stacking structure and a preparation method thereof. Background Art

[0002] In traditional 2.5D or 3D advanced packaging, wiring is mostly done on the front side of the wafer, and signal lines and power lines are stacked and connected vertically to form semiconductor devices with two or more layers of active electronic components of an integrated circuit. Power lines are used to supply power to the chip to form a power supply network. However, there is also a signal network formed by signal lines in the front area of ​​the chip. Making the power supply network on the front of the chip means that the power supply network and signal network in the chip must share the same component space, and the power supply network often occupies a large space, making it difficult to further reduce the volume of the entire packaging structure. In addition, the three-dimensional packaging structure with increased chip density may experience high IR voltage drop, which will lead to increased power consumption and decreased device performance.

[0003] Therefore, the industry began to explore the possibility of transferring the power supply network to the back side, making backside PDN a hot technical topic. The current backside PDN technology is commonly used in 2D packaging. Based on the backside PDN technology, how to further increase the chip density of the packaging structure and increase the number of transistors to improve device performance has become another difficult problem faced by technicians. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip stacking structure and a preparation method thereof, so as to improve chip density and increase the number of transistors.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a chip stacking structure with back-side power supply, the chip stacking structure comprising:

[0006] A first chip includes a first substrate, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from top to bottom, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistors;

[0007] A second chip is bonded below the first chip, comprising a second substrate, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from bottom to top, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistor;

[0008] The first chip and the second chip are also respectively formed with power rails, which penetrate the dielectric layer and the signal connection layer to electrically connect the buried power layer; the signal connection layers of the two chips are in contact to achieve signal connection; the power rails of the two chips are in contact to achieve electrical connection.

[0009] Preferably, the chip stacking structure further comprises an isolation layer formed by a shallow trench isolation process, and the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

[0010] Preferably, a plurality of penetrating metal pillars are formed in the first substrate, and the plurality of metal pillars are electrically connected to the power rail and the buried power layer of the first chip respectively.

[0011] Preferably, a metal interconnection layer is formed on the surface of the first substrate for electrically leading out the metal pillars.

[0012] Preferably, it further comprises a capacitor and inductor layer, and the capacitor and inductor layer is located between the first substrate and the metal interconnection layer.

[0013] The present invention also provides a method for preparing a back-side powered chip stacking structure, the method comprising the following steps:

[0014] S1: providing a first substrate, forming a buried power layer and a dielectric layer on the first substrate, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a first chip, wherein the buried power layer is used as a power supply channel for the transistors;

[0015] S2: providing a second substrate, forming a buried power layer and a dielectric layer on the second substrate, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a second chip;

[0016] S3: forming a signal connection layer on the surface of the dielectric layer of the first chip and the second chip away from the substrate, wherein a metal line is formed in the signal connection layer to achieve signal connection with the transistor; the first chip and the second chip are also respectively formed with a power rail, wherein the power rail penetrates the dielectric layer and the signal connection layer to electrically connect the buried power layer;

[0017] S4: bonding the first chip and the second chip up and down to form a stacked body, so that the signal connection layers of the two chips are in contact with each other to achieve signal connection, and the power rails of the two chips are in contact with each other to achieve electrical connection.

[0018] Preferably, the method further comprises the following steps:

[0019] S5: turning over the stacked body so that the first chip faces upward, and then thinning the first substrate of the first chip;

[0020] S6: forming a plurality of penetrating metal pillars in the thinned first substrate, wherein the plurality of metal pillars are electrically connected to the power rails and the buried power layer of the first chip respectively;

[0021] S7: forming a metal interconnection layer on the surface of the thinned first substrate to electrically lead out the metal pillars.

[0022] Preferably, before preparing the metal interconnection layer in step S7, a capacitor and inductor layer is formed on the surface of the first substrate, and the capacitor and inductor layer is located between the first substrate and the metal interconnection layer.

[0023] Preferably, the first substrate in step S1 comprises a silicon substrate layer, an etch stop layer and a silicon cover layer stacked in sequence, and the second substrate in step S2 is a silicon substrate layer; and the thinning process of the first substrate in step S5 removes the silicon substrate layer and the etch stop layer.

[0024] Preferably, steps S1 and S2 further include a process of forming an isolation layer by a shallow trench isolation process, wherein the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

[0025] As described above, the present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure includes two chips bonded up and down, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, combined with the setting of the power rail and the buried power layer, it is only necessary to form a metal interconnection layer on the back of the first chip as a back power supply layer, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve double the number of transistors in the same area. For example, only a 14nm process can be used, combined with the upper and lower transistor stacking method of the present application, the number of transistors under the 7nm process can be achieved, and the same performance can be achieved, thereby saving process costs. In addition, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1-Figure 8 It is a schematic diagram showing the process steps of the chip stacking structure of the present invention.

[0027] Fig. 9 Shown is a schematic structural diagram of the chip stacking structure of the present invention.

[0028] Fig.10 It is a schematic structural diagram of a chip stacking structure with capacitor and inductor layers according to the present invention.

[0029] Component number description

[0030] 101 Silicon substrate layer

[0031] DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0034] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0035] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0036] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0037] like Figure 1-Figure 8 As shown, the present invention provides a method for preparing a back-side powered chip stacking structure, which specifically includes the following steps:

[0038] S1: Provide a first substrate, such as Figure 1-Figure 2As shown, a buried power layer 104 and a dielectric layer 105 are formed on the first substrate, a plurality of transistors 201 electrically connected to the buried power layer 104 are formed in the dielectric layer 105, and a first chip 100 is formed. The buried power layer 104 is used as a power supply channel for the transistors 201.

[0039] Specifically, the first substrate includes a silicon substrate layer 101, an etch stop layer 102 and a silicon capping layer 103 stacked in sequence, and the etch stop layer 102 can be one or any of SiGe, Ti, Al, and SiN. The buried power layer 104 and the dielectric layer 105 are formed in sequence on the silicon capping layer 103. As an example, the transistor 201 can be a Fin FET, and the transistor 201 can be formed after the buried power layer 104 is formed. The transistor 201 is obtained by covering the silicon material layer and then further etching, doping and other processes. The specific manufacturing process of the transistor 201 (Fin FET) can refer to the prior art and will not be described in detail here. The dielectric layer 105 is used to achieve electrical insulation between the transistors 201 and the electrical insulation between the upper and lower structures.

[0040] Furthermore, this step may also include a shallow trench isolation process (STI). In some embodiments, the shallow trench isolation process is used to form a buried power layer 104: first, a layer of insulating material is deposited, and a groove is formed by etching, and then the groove is filled with a conductive material to form a patterned conductive layer to realize power supply to the transistor. In some other embodiments, the shallow trench isolation process is used to make an isolation layer 202 to achieve isolation between multiple buried power layers 104: for example, the chip is provided with multiple buried power layers 104 (Buried power rail, BPR), including a first BPR for providing a first power supply voltage (such as VDD) and a second BPR for providing a second power supply voltage (such as VSS or GND); or, the transistors are divided into multiple subsets, and the multiple buried power layers include a third BPR for providing a first power supply voltage to a first subset of transistors, and a fourth BPR for providing a first power supply voltage to a second subset of transistors. In some other embodiments, the shallow trench isolation process is used to achieve electrical insulation between transistors, and an isolation layer 202 is set between transistors 201 to separate them from each other and ensure mutual insulation.

[0041] Next, step S2 is performed: providing a second substrate, such as Figure 3 As shown, a buried power layer 104 and a dielectric layer 105 are formed on the second substrate. A plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105 to form a second chip 200 .

[0042] Specifically, as an example, the structure of the second substrate can select the same composite layer structure as the first substrate, including a silicon substrate layer 101, an etch stop layer 102 and a silicon capping layer 103 stacked in sequence. As a preferred solution, the second substrate only includes the silicon substrate layer 101, because the cost of a single silicon substrate layer 101 is obviously lower than the cost of the composite layer. The reason for selecting a composite layer for the first substrate is that in the subsequent step S5, the process of thinning the first substrate requires the etch stop layer 102 as a stop signal during thinning. There is no thinning process for the second substrate, and there is no need to set the etch stop layer 102. At the same time, similar to the first chip, the second chip is also formed with an isolation layer 202 for isolation between multiple buried power layers or for electrical insulation between transistors.

[0043] Then, proceed to step S3: Figure 4 As shown, a signal connection layer 106 is formed on the surface of the dielectric layer 105 of the first chip 100 and the second chip 200 away from the substrate, and a metal line is formed in the signal connection layer 106 to achieve signal connection with the transistor 201; the first chip 100 and the second chip 200 are also respectively formed with a power rail 16, and the power rail 16 penetrates the dielectric layer 105 and the signal connection layer 106 to electrically connect the buried power layer 104;

[0044] Specifically, the signal connection layer 106 can be prepared by a copper Damascene process. As an example, an insulating layer such as silicon dioxide is first deposited on the surface of the dielectric layer 105, then etched to form a groove, and then metallic copper is deposited in the groove to finally form the signal connection layer 106, and the metal wires in the signal connection layer 106 are copper.

[0045] Then, proceed to step S4: Figure 5 As shown, the first chip 100 and the second chip 200 are bonded up and down to form a stack, so that the signal connection layers 106 of the two chips are in contact to achieve signal connection; the power rails 16 of the two chips are in contact to achieve electrical connection;

[0046] Specifically, the two chips are stacked and interconnected by bonding, and the transistors 201 of the upper and lower chips can be powered by the power rail 16 and the buried power layer 104. Double the number of transistors can be achieved in the same area. For example, only the 14nm process can be used, combined with the upper and lower transistor stacking method of the present application, to achieve the same performance as the number of transistors in the 7nm process. Advanced processes mean expensive process costs. By stacking up and down, while achieving the same performance, process costs can also be saved.

[0047] Then, proceed to step S5: Figure 6-Figure 7As shown, the stack is turned over so that the first chip 100 faces upward, and then the first substrate of the first chip 100 is thinned;

[0048] Specifically, the first substrate before thinning includes a silicon substrate layer 101, an etch stop layer 102 and a silicon cover layer 103. During thinning, the etch stop layer 102 serves as a stop signal during thinning. In the process, the silicon substrate layer 101 of the first substrate is first thinned by CMP, and then the remaining part of the silicon substrate layer 101 is removed by dry etching, and finally the etch stop layer 102 is removed by wet etching, that is, the first substrate after thinning includes only the silicon cover layer 103.

[0049] It should be noted that the flipped second chip 200 is located at the bottom and acts as a temporary carrier. If there is no second chip 200, a temporary carrier needs to be provided to carry and fix the first chip 100 for subsequent thinning. The temporary carrier is a temporary material with high process cost. The bonding of the first chip 100 and the second chip 200 here increases the number of collective tubes and avoids the use of a temporary carrier, thereby reducing the production cost.

[0050] Then, proceed to step S6: Figure 8 As shown, a plurality of penetrating metal pillars 31 are formed in the thinned first substrate (i.e., the remaining silicon cover layer 103), and the plurality of metal pillars 31 are respectively electrically connected to the power rail 16 of the first chip 100 and the buried power layer 104. The metal pillars electrically connected to the buried power layer 104 here not only transmit power, but also have the function of signal transmission, first transmitting the signal to the first chip, and then the first chip transmits it to the second chip through the signal connection layer.

[0051] Specifically, a passivation layer is first formed on the surface of the first substrate. The passivation layer is usually an oxide material or a nitride oxide to play a moisture-proof and anti-static role and protect the internal circuit. Then, the metal column 31 is prepared. The process of preparing the metal column 31 is: first, a plurality of silicon through vias are formed in the first substrate, more specifically, nano silicon through vias, and then an oxide layer is covered on the inner wall of the silicon through via. Finally, the metal column 31 is formed by filling with metal.

[0052] Step S7: Fig. 9 As shown, a metal interconnection layer 301 is formed on the surface of the thinned first substrate to electrically lead out the metal pillars 31 .

[0053] Specifically, similar to step S3, the metal interconnection layer 301 is also preferably prepared by a copper Damascene process. As an example, an insulating layer such as silicon dioxide is first deposited on the surface of the substrate, then etched to form grooves, and then metallic copper is deposited in the grooves to finally form the metal interconnection layer 301.

[0054] As a supplement, before the metal interconnection layer 301 is prepared, a capacitor and inductor layer 302 is also formed on the surface of the first substrate. Fig.10 As shown, the capacitor and inductor layer 302 is located between the first substrate and the metal interconnection layer 301. The metal interconnection layer 301 is electrically connected to the metal pillar 31 via the capacitor and inductor layer 302. The capacitor and inductor layer 302 includes multiple capacitors and inductors to achieve the regulation of the circuit, and to achieve power integrity without occupying additional area, which is conducive to controlling the size and saving space. The metal interconnection layer 301 and the capacitor and inductor layer 302 are used as the back power supply layer for power supply. At the same time, combined with the setting of the power rail 16 and the buried power layer 104, only the silicon through-hole is made in the substrate of the first chip 100 to form the metal pillar 31, so that the electrical signal can be transmitted to the transistor 201 of the upper and lower chips.

[0055] The present invention also provides a back-side powered chip stacking structure, such as Figure 9-10 As shown, the chip stacking structure can be based on the above-mentioned preparation method, but is not limited to the above-mentioned preparation method, and the chip stacking structure includes:

[0056] The first chip 100 includes a first substrate (the first substrate corresponds to the first substrate after thinning in the above-mentioned preparation method, i.e., the silicon cover layer 103), a buried power layer 104, a dielectric layer 105, and a signal connection layer 106, which are stacked in sequence from top to bottom. A plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, and a metal line is formed in the signal connection layer 106 to realize signal connection with the transistors 201;

[0057] The second chip 200 is bonded below the first chip 100, and includes a second substrate, a buried power layer 104, a dielectric layer 105, and a signal connection layer 106 stacked in sequence from bottom to top. A plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, and metal wires are formed in the signal connection layer 106 to achieve signal connection with the transistors 201;

[0058] The first chip 100 and the second chip 200 are also respectively formed with power rails 16, and the power rails 16 penetrate the dielectric layer 105 and the signal connection layer 106 to electrically connect the buried power layer 104; the signal connection layers 106 of the two chips are in contact to achieve signal connection; the power rails 16 of the two chips are in contact to achieve electrical connection.

[0059] Furthermore, the chip stacking structure further includes an isolation layer 202 formed by a shallow trench isolation process, and the isolation layer 202 is used for isolation between multiple buried power layers 104 or for electrical insulation between transistors 201 .

[0060] Furthermore, a plurality of penetrating metal pillars 31 are formed in the first substrate, and the plurality of metal pillars 31 are electrically connected to the power rail 16 of the first chip 100 and the buried power layer 104 respectively.

[0061] Furthermore, a metal interconnection layer 301 is formed on the surface of the first substrate for electrically leading out the metal pillars 31 .

[0062] Furthermore, it also includes a capacitor and inductor layer 302 , and the capacitor and inductor layer 302 is located between the first substrate and the metal interconnection layer 301 .

[0063] For specific details of the chip stacking structure, please refer to the relevant description in the above-mentioned preparation method, which will not be repeated here.

[0064] In summary, the present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure includes two chips bonded up and down, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, combined with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer on the back of the first chip as a back power supply layer, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can achieve double the number of transistors in the same area. For example, only a 14nm process can be used, combined with the upper and lower transistor stacking method of the present application, the number of transistors under a 7nm process can be achieved, and the same performance can be achieved, thereby saving process costs. In addition, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A back-side powered chip stacking structure, characterized in that: The chip stacking structure comprises: A first chip includes a first substrate, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from top to bottom, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistors; A second chip is bonded below the first chip, comprising a second substrate, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from bottom to top, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistor; The first chip and the second chip are also respectively formed with power rails, which penetrate the dielectric layer and the signal connection layer to electrically connect the buried power layer; the signal connection layers of the two chips are in contact to achieve signal connection; the power rails of the two chips are in contact to achieve electrical connection.

2. The chip stacking structure according to claim 1, characterized in that: The chip stacking structure further includes an isolation layer formed by a shallow trench isolation process, and the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

3. The chip stacking structure according to claim 1, characterized in that: A plurality of penetrating metal pillars are formed in the first substrate, and the plurality of metal pillars are electrically connected to the power rails and the buried power layer of the first chip respectively.

4. The chip stacking structure according to claim 3, characterized in that: A metal interconnection layer is formed on the surface of the first substrate for electrically leading out the metal pillars.

5. The chip stacking structure according to claim 4, characterized in that: It also includes a capacitor and inductor layer, which is located between the first substrate and the metal interconnection layer.

6. A method for preparing a back-side powered chip stacking structure, characterized in that: The preparation method comprises the following steps: S1: providing a first substrate, forming a buried power layer and a dielectric layer on the first substrate, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a first chip, wherein the buried power layer is used as a power supply channel for the transistors; S2: providing a second substrate, forming a buried power layer and a dielectric layer on the second substrate, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a second chip; S3: forming a signal connection layer on the surface of the dielectric layer of the first chip and the second chip away from the substrate, wherein a metal line is formed in the signal connection layer to achieve signal connection with the transistor; the first chip and the second chip are also respectively formed with a power rail, wherein the power rail penetrates the dielectric layer and the signal connection layer to electrically connect the buried power layer; S4: bonding the first chip and the second chip up and down to form a stacked body, so that the signal connection layers of the two chips are in contact with each other to achieve signal connection, and the power rails of the two chips are in contact with each other to achieve electrical connection.

7. The preparation method according to claim 6, characterized in that: The following steps are also included: S5: turning over the stacked body so that the first chip faces upward, and then thinning the first substrate of the first chip; S6: forming a plurality of penetrating metal pillars in the thinned first substrate, wherein the plurality of metal pillars are electrically connected to the power rails and the buried power layer of the first chip respectively; S7: forming a metal interconnection layer on the surface of the thinned first substrate to electrically lead out the metal pillars.

8. The preparation method according to claim 7, characterized in that: Before preparing the metal interconnection layer in step S7, a capacitor and inductor layer is formed on the surface of the first substrate, and the capacitor and inductor layer is located between the first substrate and the metal interconnection layer.

9. The preparation method according to claim 6, characterized in that: The first substrate in step S1 includes a silicon substrate layer, an etch stop layer and a silicon cover layer stacked in sequence, and the second substrate in step S2 is a silicon substrate layer; the silicon substrate layer and the etch stop layer are removed by thinning the first substrate in step S5.

10. The preparation method according to claim 6, characterized in that: Steps S1 and S2 also include a process of forming an isolation layer by a shallow trench isolation process. The isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

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