Semiconductor integrated circuit device and motor system

Abstract

The invention provides a semiconductor integrated circuit device and a motor system. A semiconductor integrated circuit device (11) includes: a first terminal (VB) configured to receive a first voltage; parts (Q1, Q2) of a charge pump circuit configured so as to output a second voltage obtained by reducing the first voltage received from the first terminal; at least a portion (Q3, R1, R2, REF1, AMP1) of a linear power supply circuit configured so as to output a third voltage obtained by reducing the second voltage received from the charge pump circuit; an internal circuit (1) configured so as to use the third voltage received from the linear power supply circuit as a power supply voltage; a second terminal (CPA) configured such that a first end of an external resistor (31) included in the charge pump circuit is connected to the second terminal; and a third terminal (CPB) configured such that a second end of the external resistor is connected to the third terminal.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit device and a motor system. Background Art

[0002] In the motor driving device (semiconductor integrated circuit device) described in Patent Document 1, an internal power supply circuit generates an internal power supply voltage from a power supply voltage and supplies the internal power supply voltage to each part of the motor driving device (logic circuit, etc.).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-102658 Summary of the invention

[0006] However, when the difference between the power supply voltage and the internal power supply voltage is large and the circuit current of the circuit supplying the internal power supply voltage becomes large, the heat generation of the semiconductor integrated circuit device becomes large. It is possible to consider a countermeasure of using the internal power supply circuit as a linear power supply circuit and using the output transistor of the linear power supply circuit as an external component or a countermeasure of using the internal power supply circuit as a switching regulator. However, in the case of implementing these countermeasures, adverse effects such as increased cost, increased mounting area, etc. may occur.

[0007] A semiconductor integrated circuit device of the present invention includes: a first terminal, the first terminal is configured to receive a first voltage; a part of a charge pump circuit, the charge pump circuit is configured to output a second voltage obtained by stepping down the first voltage received from the first terminal; at least a part of a linear power supply circuit, the linear power supply circuit is configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit; an internal circuit, the internal circuit is configured to use the third voltage received from the linear power supply circuit as a power supply voltage; a second terminal, the second terminal is configured so that a first end of an external resistor included in the charge pump circuit is connected to the second terminal; and a third terminal, the third terminal is configured so that a second end of the external resistor is connected to the third terminal.

[0008] A motor system of the present invention includes: a motor; and the above-mentioned semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is configured to drive the motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention.

[0010] Figure 1is a schematic diagram showing a schematic configuration of a motor system according to a first embodiment of the present invention.

[0011] Figure 2 This is an external perspective view of a semiconductor integrated circuit device.

[0012] Figure 3 is a timing chart for explaining the operation of the semiconductor integrated circuit device according to the first embodiment.

[0013] Figure 4 is a timing chart for explaining another operation of the semiconductor integrated circuit device according to the first embodiment.

[0014] Figure 5 is a timing chart for explaining still another operation of the semiconductor integrated circuit device according to the first embodiment.

[0015] Figure 6 is a schematic diagram showing the relationship between the voltage applied to the terminal VB and the power consumption of the semiconductor integrated circuit device.

[0016] Figure 7 is a schematic diagram showing a schematic configuration of a motor system according to a second embodiment of the present invention.

[0017] Figure 8 is a schematic diagram showing a schematic configuration of a motor system according to a third embodiment of the present invention.

[0018] Fig. 9 is a schematic diagram showing a schematic configuration of a motor system according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other cases, well-known methods, processes, systems, and components are not described in detail in order to avoid unnecessarily obscuring aspects of the various embodiments.

[0020] In the present invention, a metal oxide semiconductor field effect transistor (MOSFET) refers to a field effect transistor having a gate structure consisting of at least three layers, the at least three layers being selected from the group consisting of “a layer made of a conductor or semiconductor (such as polysilicon) having a low resistance value”, “an insulating layer”, and “a P-type, N-type or intrinsic semiconductor layer”. That is, the gate structure of MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0021] In the present invention, the reference voltage refers to a voltage that is constant in an ideal state, and is actually a voltage that may slightly change due to changes in temperature or the like.

[0022] <First Embodiment>

[0023] Figure 1 is a schematic diagram showing a schematic configuration of a motor system according to a first embodiment of the present invention. Figure 1 The illustrated motor system SYS1 includes a semiconductor integrated circuit device 11 , a motor 21 , a resistor 31 , and capacitors 32 and 33 .

[0024] Figure 2 1 is an external perspective view of the semiconductor integrated circuit device 11. The semiconductor integrated circuit device 11 is an electronic component formed by sealing a semiconductor integrated circuit chip in a housing (package) made of resin. A plurality of external terminals are provided to be exposed on the housing of the semiconductor integrated circuit device 11, and the plurality of external terminals include Figure 1 The terminals VB, CPA, CPB, VREG, OUT1A, OUT1B, OUT2A, OUT2B, PGND and GND are shown. Figure 2 The number of external terminals of the semiconductor integrated circuit device 11 and the appearance of the semiconductor integrated circuit device 11 shown are merely examples.

[0025] The semiconductor integrated circuit device 11 includes a control circuit 1 , a pre-driver 2 , a driver 3 , and terminals VB, OUT1A, OUT1B, OUT2A, OUT2B, PGND, and GND.

[0026] The control circuit 1 includes a control logic circuit and an analog circuit, and controls the driver 3 through the pre-driver 2 .

[0027] The pre-driver 2 performs predetermined signal processing (level shift processing, waveform shaping processing, simultaneous on prohibition processing, etc.) on the up / down pre-driver drive signal of each phase supplied from the control circuit 1, thereby generating an up / down driver drive signal of each phase and outputting it to the driver 3.

[0028] The driver 3 generates a motor drive voltage for each phase based on the up / down driver drive signal for each phase supplied from the pre-driver 2, and outputs it to the motor 21. The motor 21 is a two-phase stepping motor. The motor 21 includes a rotor RT1 and stator coils L1 and L2 corresponding to the two phases, respectively. The driver 3 is connected to a first end of the stator coil L1 via a terminal OUT1A, to a second end of the stator coil L1 via a terminal OUT1B, to a first end of the stator coil L2 via a terminal OUT2A, and to a second end of the stator coil L2 via a terminal OUT2B.

[0029] A voltage Vb is applied from a voltage source B1 to a terminal VB. The pre-driver 2 and the driver 3 are configured to use the voltage Vb received from the terminal VB as a power supply voltage.

[0030] A ground potential is applied to the terminal PGND. The driver 3 is configured to use the ground potential received from the terminal PGND as a reference potential.

[0031] A ground potential is applied to the terminal GND. The ground potential applied to the terminal GND is used as a reference potential in each portion of the semiconductor integrated circuit device 11.

[0032] The semiconductor integrated circuit device 11 further includes transistors Q1 to Q3 each of which is a P-channel MOSFET, resistors R1 and R2, an amplifier AMP1, a reference voltage source REF1, a charge and discharge control circuit 4, a switching control circuit 5, a monitoring circuit 6, and terminals CPA, CPB, and VREG.

[0033] The source of transistor Q1 is connected to terminal VB. The drain of transistor Q1 is connected to terminal CPA and the source of transistor Q2. The drain of transistor Q2 is connected to terminal CPB and the source of transistor Q3. The voltage Vreg at the drain of transistor Q3 is supplied to terminal VREG, a voltage divider circuit including resistors R1 and R2, and control circuit 1.

[0034] The charge and discharge control circuit 4 controls the transistor Q1 . The switching control circuit 5 controls the transistor Q2 . The monitoring circuit 6 monitors the voltage Vcpb of the terminal CPB and outputs the monitoring result to the charge and discharge control circuit 4 and the switching control circuit 5 .

[0035] The amplifier AMP1 controls the transistor Q3 according to the difference between the reference voltage Vref output from the reference voltage source REF1 and the voltage Vreg.

[0036] Outside the semiconductor integrated circuit device 11, a first end of the resistor 31 is connected to the terminal CPA, a second end of the resistor 31 and a first end of the capacitor 32 are connected to the terminal CPB, a first end of the capacitor 33 is connected to the terminal VREG, and a second end of the capacitor 32 and a second end of the capacitor 33 are connected to the ground potential.

[0037] The charge pump circuit including transistors Q1 and Q2 , a resistor 31 , and a capacitor 32 is configured to output a voltage Vcpb obtained by stepping down Vb received from a terminal VB.

[0038] The linear power supply circuit including the transistor Q3 , the resistors R1 and R2 , the amplifier AMP1 , and the capacitor 33 is configured to output a voltage Vreg obtained by stepping down the voltage Vcpb.

[0039] Figure 3 is a timing chart for explaining the operation of the semiconductor integrated circuit device 11. Figure 3 , the voltages Vb, Vcpb and Vreg, the state of the transistor Q1 and the state of the transistor Q2 are depicted from top to bottom. Figure 3 The voltage values ​​depicted in are merely examples and are not limited thereto.

[0040] When the voltage Vcpb drops to a first threshold (eg, 6.8V), the charge and discharge control circuit 4 turns on the transistor Q1 , and when the voltage Vcpb rises to a second threshold (eg, 7V) greater than the first threshold, the charge and discharge control circuit 4 turns off the transistor Q1 .

[0041] When the transistor Q1 is turned on, the capacitor 32 is charged and the voltage Vcpb rises, and when the transistor Q1 is turned off, the capacitor 32 is discharged and the voltage Vcpb drops. Figure 3 In the timing diagram shown, since the transistor Q2 is turned off, the power supplied to the terminal VB is distributed and consumed inside the semiconductor integrated circuit device 11 and the resistor 31. This reduces the power consumption inside the semiconductor integrated circuit device 11, and can suppress the heat generation inside the semiconductor integrated circuit device 11. In this way, since the semiconductor integrated circuit device 11 can suppress the heat generation inside the semiconductor integrated circuit device 11, the output current capability of the driver 3 can be improved.

[0042] Figure 4 1 is a timing chart for explaining another operation of the semiconductor integrated circuit device 11. Figure 4 , the voltage Vb, the voltage Vcpb, the voltage Vreg, the state of the transistor Q1, the state of the transistor Q2, and the current I_load flowing through the transistor Q1 are depicted from top to bottom. Figure 4 The voltage values ​​depicted in are merely examples and are not limited thereto.

[0043] exist Figure 4 , the transition is made in the order of period P1, period P2, and period P3. Periods P1 and P3 are periods in which the load is light and driven by the power output from the linear power supply circuit including the transistor Q3, the resistors R1 and R2, the amplifier AMP1, and the capacitor 33. Period P2 is a period in which the load is heavy and driven by the power output from the linear power supply circuit including the transistor Q3, the resistors R1 and R2, the amplifier AMP1, and the capacitor 33. For example, when a variable load is externally connected to the terminal VREG, the semiconductor integrated circuit device 11 can be as follows Figure 4 Operate as shown.

[0044] The operation of the semiconductor integrated circuit device 11 during the period P1 is similar to Figure 3 The operations shown are the same.

[0045] During the period P2, even when the transistor Q1 is turned on, the voltage Vcpb continues to drop. When the voltage Vcpb drops to a third threshold value (e.g., 5.8V) that is less than the first threshold value, the switching control circuit 5 turns on the transistor Q2. Therefore, the terminals CPA and CPB are short-circuited to reduce the resistance value of the terminals CPA and CPB, so that the charging capacity of the charge pump circuit can be improved, and the voltage Vcpb is increased compared to the state in which the terminals CPA and CPB are not short-circuited.

[0046] When the voltage Vcpb rises to a fourth threshold value (e.g., 6V) greater than the third threshold value and less than the first threshold value, the switching control circuit 5 turns off the transistor Q2. Therefore, compared with the state in which the terminals CPA and CPB are short-circuited, the charging capability of the charge pump circuit is reduced, which reduces the voltage Vcpb during the period P2 but increases the voltage Vcpb during the period P3.

[0047] In other words, by providing a switching circuit (transistor Q2 in this embodiment) configured to switch between short-circuiting and non-shorting between terminals CPA and CPB, the charge pump circuit can handle a larger load. In the case where the charge pump circuit does not need to handle a larger load, the charge pump circuit may not include a switching circuit (transistor Q2 in this embodiment) configured to switch between short-circuiting and non-shorting between terminals CPA and CPB.

[0048] Figure 5 1 is a timing chart for explaining still another operation of the semiconductor integrated circuit device 11. Figure 5 , the voltage Vb, the voltage Vcpb, the voltage Vreg, the state of the transistor Q1, the state of the transistor Q2, and the current I_load flowing through the transistor Q1 are depicted from top to bottom. Figure 5 The voltage values ​​depicted in are merely examples and are not limited thereto.

[0049] exist Figure 5 In the embodiment of the present invention, the voltage Vb gradually decreases (decreases). When the voltage Vb decreases below the first threshold value (for example, 6.8V), the voltage Vcpb does not increase even when the transistor Q1 is turned on. When the voltage Vcpb decreases to a third threshold value (for example, 5.8V) less than the first threshold value, the switching control circuit 5 turns on the transistor Q2. Therefore, the terminals CPA and CPB are short-circuited to reduce the resistance value of the terminals CPA and CPB, so that the charging capacity of the charge pump circuit can be improved, and the decrease of the voltage Vcpb is suppressed compared with the state in which the terminals CPA and CPB are not short-circuited.

[0050] When the voltage Vb drops below the target output voltage (e.g., 5 V) of the linear power supply circuit including the transistor Q3, the resistors R1 and R2, the amplifier AMP1, and the capacitor 33, the output voltage Vreg of the linear power supply circuit including the transistor Q3, the resistors R1 and R2, the amplifier AMP1, and the capacitor 33 becomes lower than the target output voltage.

[0051] By providing a switching circuit (transistor Q2 in the present embodiment) configured to switch between short-circuiting and non-shorting between terminals CPA and CPB, it is possible to improve the resistance of voltage Vb to voltage drop.

[0052] Figure 6 1 is a schematic diagram showing the relationship between the voltage Vb applied to the terminal VB and the power consumption of the semiconductor integrated circuit device 11. Figure 6 , the horizontal axis represents the voltage Vb applied to the terminal VB, and the vertical axis represents the power consumption.

[0053] Figure 6 The thin solid line W1 in indicates the power supplied to the terminal VB, that is, the power consumption of the semiconductor integrated circuit device 11 and the resistor 31 . Figure 6 The thick solid line W2 in φ indicates the power consumption of the semiconductor integrated circuit device 11 .

[0054] When transistor Q2 is turned on, Figure 6 The thin solid line W1 in Figure 6 The thick solid line W2 in the figure coincides.

[0055] When the transistor Q2 is turned off, the power consumption of the semiconductor integrated circuit device 11 becomes smaller than the power supplied to the terminal VB, and Figure 6 The thin solid line W1 and Figure 6 The difference between the thick solid line W2 in FIG. 1 and FIG. 2 is the power consumed by the resistor 31 .

[0056] <Second Embodiment>

[0057] Figure 7 is a schematic diagram showing a schematic configuration of a motor system according to a second embodiment of the present invention. Figure 7 The illustrated motor system SYS2 includes a semiconductor integrated circuit device 12 , a motor 21 , a resistor 31 , and capacitors 32 and 33 .

[0058] The semiconductor integrated circuit device 12 has a configuration in which a transistor Q4 which is a P-channel MOSFET, a switch SW1 controlled by a charge and discharge control circuit 4, and a current source CS1 are added to the semiconductor integrated circuit device 11. The transistors Q1 and Q4 constitute a current mirror circuit. When the switch SW1 is turned on, the current mirror circuit constituted by the transistors Q1 and Q4 supplies a mirror current that mirrors the output current of the current source CS1 to the terminal CPA.

[0059] In this embodiment, transistor Q1 is used as a current source. That is, in this embodiment, the current source is connected to terminal CPA. Therefore, the change of the voltage of terminal CPA becomes less steep, thereby reducing the ripple of voltage Vreg. Figures 3 to 5 , the waveform of the voltage Vreg is simplified, and illustration of the ripple of the voltage Vreg is omitted.

[0060] Similar to the semiconductor integrated circuit device 11 , the semiconductor integrated circuit device 12 can suppress heat generation inside the semiconductor integrated circuit device 12 .

[0061] <Third Embodiment>

[0062] Figure 8 is a schematic diagram showing a schematic configuration of a motor system according to a third embodiment of the present invention. Figure 8 The illustrated motor system SYS3 includes a semiconductor integrated circuit device 13 , a motor 21 , a resistor 31 , and capacitors 32 and 33 .

[0063] The semiconductor integrated circuit device 13 is different from the semiconductor integrated circuit device 11 in that the pre-driver 2 is configured to use the voltage Vreg as a power supply voltage, but is similar to the semiconductor integrated circuit device 11 in other respects.

[0064] Similar to the semiconductor integrated circuit device 11 , the semiconductor integrated circuit device 13 can suppress heat generation inside the semiconductor integrated circuit device 13 .

[0065] <Fourth Embodiment>

[0066] Fig. 9 is a schematic diagram showing a schematic configuration of a motor system according to a fourth embodiment of the present invention. Fig. 9 The illustrated motor system SYS4 includes a semiconductor integrated circuit device 14 , a motor 21 , a resistor 31 , capacitors 32 and 33 , and a driver 3 .

[0067] The semiconductor integrated circuit device 14 is different from the semiconductor integrated circuit device 13 in that the driver 3 is externally connected, but is similar to the semiconductor integrated circuit device 13 in other respects.

[0068] Similar to the semiconductor integrated circuit device 11 , the semiconductor integrated circuit device 14 can suppress heat generation inside the semiconductor integrated circuit device 14 .

[0069] <Others>

[0070] In addition to the above-mentioned embodiments, various modifications may be made to the configuration of the present invention without departing from the spirit of the present invention. The above-mentioned embodiments are illustrative in all aspects and should not be considered as restrictive, and the technical scope of the present invention is indicated by the claims rather than the description of the above-mentioned embodiments, and should be understood to include all modifications falling within the meaning and scope equivalent to the claims.

[0071] For example, in the above-mentioned various embodiments, the motor is a two-phase motor, but the motor may also be a three-phase motor.

[0072] For example, in the above-mentioned various embodiments, the pre-driver 2 uses the voltage Vb applied to the terminal VB as the power supply voltage, but a boost circuit configured to boost the voltage Vb applied to the terminal VB of the semiconductor integrated circuit device may be provided in the semiconductor integrated circuit device, and the pre-driver 2 may use the voltage obtained by boosting the voltage Vb as the power supply voltage.

[0073] <Notes>

[0074] Supplementary notes will be provided to the present invention in which specific configuration examples are shown in the above-mentioned embodiments.

[0075] The semiconductor integrated circuit device (11 to 15) of the present invention has a structure (first structure) including: a first terminal (VB) configured to receive a first voltage; a portion (Q1, Q2) of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal; at least a portion (Q3, R1, R2, REF1, AMP1) of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit; an internal circuit (1) configured to use the third voltage received from the linear power supply circuit as a power supply voltage; a second terminal (CPA) configured so that a first end of an external resistor included in the charge pump circuit is connected to the second terminal (CPA); and a third terminal (CPB) configured so that a second end of the external resistor is connected to the third terminal (CPB).

[0076] According to the semiconductor integrated circuit device of the first structure, since the power supplied to the first terminal is distributed and consumed inside the semiconductor integrated circuit device and the external resistor, the power consumption inside the semiconductor integrated circuit device is reduced and the heat generation inside the semiconductor integrated circuit device can be suppressed.

[0077] The semiconductor integrated circuit device of the first structure may have a structure (second structure) further including an output stage (2, 3) configured to use the first voltage received from the first terminal as a power supply voltage.

[0078] The semiconductor integrated circuit device of the first or second structure may have a structure (third structure) in which the charge pump circuit includes a switching circuit (Q2) configured to switch between short-circuiting and non-shorting between the second terminal and the third terminal.

[0079] The semiconductor integrated circuit device of the third structure may have a structure (fourth structure) further including a switching control circuit (5) configured to control the switching circuit based on the second voltage.

[0080] The semiconductor integrated circuit device of the fourth structure may have a structure (fifth structure) in which the switching control circuit is configured to switch from the non-short circuit to the short circuit between the second terminal and the third terminal when the second voltage drops below a predetermined value.

[0081] The semiconductor integrated circuit device of any one of the first to fifth structures may have a structure (sixth structure) further comprising a charge and discharge control circuit (4) configured to control charging and discharging of a capacitor (32) included in the charge pump circuit based on the second voltage.

[0082] The semiconductor integrated circuit device of any one of the first to sixth structures may have a structure (seventh structure) further including a current source (Q1) connected to the second terminal.

[0083] The semiconductor integrated circuit device of the second structure may have a structure (eighth structure) in which the internal circuit (1) includes a control circuit configured to directly or indirectly control the output stage.

[0084] The semiconductor integrated circuit device of the eighth structure may have a structure (ninth structure) that further includes a pre-driver (2), wherein the control circuit is configured to indirectly control the output stage via the pre-driver, and wherein the pre-driver is configured to use the first voltage received from the first terminal or a voltage obtained by boosting the first voltage as a power supply voltage.

[0085] The semiconductor integrated circuit device of the second structure may have a structure (tenth structure) further including: a control circuit (1) configured to indirectly control the output stage via a pre-driver, wherein the internal circuit includes the pre-driver.

[0086] The semiconductor integrated circuit device of the tenth structure may have a structure (eleventh structure) in which the internal circuit includes the control circuit.

[0087] The motor system (SYS1 to SYS5) of the present invention has a structure (twelfth structure) including: a motor (21); and a semiconductor integrated circuit device of any one of the first to eleventh structures, the semiconductor integrated circuit device being configured to drive the motor.

[0088] Although certain embodiments have been described, these embodiments have been presented only by way of example and are not intended to limit the scope of the present invention. In fact, the embodiments described herein can be implemented in various other forms. In addition, without departing from the spirit of the present invention, various omissions, substitutions and changes can be made to the forms of the embodiments described herein. The attached claims and their equivalents are intended to cover such forms or modifications that will fall within the scope and spirit of the present invention.

[0089] Description of Reference Numerals

[0090] 1: Control circuit

[0091] 2: Pre-driver

[0092] 3: Driver

[0093] 4: Charge and discharge control circuit

[0094] 5: Switching control circuit

[0095] 6: Monitoring circuit

[0096] 11 to 15: Semiconductor integrated circuit devices

[0097] 21: Motor

[0098] 31: Resistor

[0099] 32, 33: Capacitor

[0100] AMP: amplifier

[0101] B1: Voltage source

[0102] CS1: Current source

[0103] L1, L2: stator coil

[0104] Q1 to Q4: Transistors

[0105] R1, R2: Resistors

[0106] REF1: Reference voltage source

[0107] RT1: Rotor

[0108] SW1: Switch

[0109] SYS1 to SYS5: Motor system

[0110] VB, CPA, CPB, VREG, OUT1A, OUT1B, OUT2A, OUT2B, PGND, GND: terminals.

Claims

1. A semiconductor integrated circuit device comprising: a first terminal configured to receive a first voltage; a portion of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal; at least a portion of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit; an internal circuit configured to use the third voltage received from the linear power supply circuit as a power supply voltage; a second terminal configured such that a first end of an external resistor included in the charge pump circuit is connected to the second terminal; as well as A third terminal is configured such that the second end of the external resistor is connected to the third terminal. 2 . The semiconductor integrated circuit device according to claim 1 , further comprising an output stage configured to use the first voltage received from the first terminal as a power supply voltage.

3. The semiconductor integrated circuit device according to claim 1, wherein the charge pump circuit includes a switching circuit configured to switch between short-circuiting and non-shorting between the second terminal and the third terminal. 4 . The semiconductor integrated circuit device according to claim 3 , further comprising a switching control circuit configured to control the switching circuit based on the second voltage.

5. The semiconductor integrated circuit device according to claim 4, wherein the switching control circuit is configured to switch from the non-short circuit to the short circuit between the second terminal and the third terminal when the second voltage drops below a predetermined value. 6 . The semiconductor integrated circuit device according to claim 1 , further comprising a charge and discharge control circuit configured to control charging and discharging of a capacitor included in the charge pump circuit based on the second voltage.

7. The semiconductor integrated circuit device according to claim 1, further comprising a current source connected to the second terminal.

8. The semiconductor integrated circuit device according to claim 2, wherein the internal circuit includes a control circuit configured to directly or indirectly control the output stage.

9. The semiconductor integrated circuit device according to claim 8, further comprising a pre-driver, wherein the control circuit is configured to indirectly control the output stage via the pre-driver, and The pre-driver is configured to use the first voltage received from the first terminal or a voltage obtained by boosting the first voltage as a power supply voltage.

10. The semiconductor integrated circuit device according to claim 2, further comprising a control circuit configured to indirectly control the output stage via a pre-driver, The internal circuit includes the pre-driver.

11. The semiconductor integrated circuit device according to claim 10, wherein the internal circuit includes the control circuit.

12. A motor system comprising: motor; as well as The semiconductor integrated circuit device according to any one of claims 1 to 11, wherein the semiconductor integrated circuit device is configured to drive the motor.

Images