Embedded time sequence framework operation system and method based on DSP (Digital Signal Processor) chip

Abstract

The invention provides an embedded time sequence architecture operation system and operation method based on a DSP chip, the system comprises a power module and a control module, the power module is connected to the control module, the power module is used for electric energy conversion, the control module is used for operation distribution, and floating point operation and fixed point operation of distribution are executed in a CLA and a CPU respectively. The power module (responsible for electric energy conversion) and the control module (responsible for operation distribution) are separated, so that modular design is realized, and maintenance and upgrading of the system are facilitated. And distribution of floating point operation and fixed point operation: the CLA (control law accelerator) and the CPU of the DSP chip are utilized to distribute the floating point operation and the fixed point operation, so that the computing power of the DSP chip is fully exerted, and the overall efficiency of system data processing and logic operation is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of power conversion, and in particular relates to an embedded timing architecture operating system and an operating method based on a DSP chip. Background Art

[0002] Based on the significant improvement of the characteristics of power semiconductor devices and the continuous progress of power electronic power integration technology, high power density AC / DC converters including ACDC and DCAC are widely used in many fields, including motor drive, industrial power supply, national defense and military equipment, and new energy storage systems. Module power supplies suitable for AC / DC conversion are being widely used in the above fields due to their advantages of high efficiency, small size, light weight, high power density, and high reliability.

[0003] At present, domestic digital controllers still have shortcomings in performance, especially when facing low-cost, low-performance chips, resource utilization optimization is still a challenge. By 2024, the performance of domestic DSP chips can be stably benchmarked to the lower-end products in Ti's TMS320F28xx series. Although they have few resources, low main frequency, and slow computing speed, the existing methods have failed to fully utilize the potential of limited resources, resulting in digital algorithms and control system architectures failing to reach ideal levels in performance and competitiveness. Therefore, it is very necessary to study an efficient embedded timing architecture operation system technology to more effectively utilize existing resources under performance-constrained conditions, thereby improving the overall performance and market competitiveness of domestic digital controllers.

[0004] From the perspective of implementation, the currently widely used embedded architecture based on low-end DSP chips is: (1) The sampling-filtering-control-modulation sequence is executed in this way. This method has a long delay from sampling to drive output and a low control frequency, which cannot adapt to high-precision phase control. (2) Execute PIE-level and above interrupts in the CPU, and its service function executes related fixed-point instructions, and triggers the control law accelerator CLA interrupt through IACK to execute related floating-point operation instructions. This method improves the control cycle to a certain extent, but does not accurately plan the timing according to the actual running time. When the CLA interrupt running time is much shorter than the CPU, the CLA resource utilization is low.

[0005] The existing technology designs an embedded program framework for a three-phase PFC cascade Boost system, adopts sequential execution, and sets up two interrupts with different priorities to handle tasks of different levels. This method can make the architecture simple and clear, but there are preemption problems between different priorities, and all tasks have the same control frequency, without distinguishing the importance of execution, and no further optimization is made in the timing planning of the program.

[0006] The existing technology combines the functional advantages of the internally integrated control law accelerator (CLA) for small and medium-power digital uninterruptible power supply UPS to assist the main core CPU in sharing system tasks and realize full digital control. This method makes full use of the dual-core mechanism, effectively reduces peripheral devices and reduces costs, but the execution cycle of CLA is still consistent with that of CPU, and no further optimization is made in terms of differentiation and task allocation.

[0007] The existing technology designs an embedded program framework for high-frequency AC / DC / AC converters for UPS systems, which uses CLA for computational acceleration. This design places all algorithms in CLA and only uses CLA for computational acceleration, without making detailed allocations for the overall program and tasks, and the CPU resources are not fully utilized.

[0008] There are two widely used embedded architectures based on low-end DSP chips.

[0009] First, the sampling-filtering-control-modulation sequence is executed. This method has a long delay from sampling to drive output and a low control frequency, which cannot adapt to high-precision phase control. Second, the CPU executes PIE-level and above interrupts, and its service function executes related fixed-point instructions, and triggers the control law accelerator CLA interrupt through IACK to execute related floating-point operation instructions. This method improves the control cycle to a certain extent, but does not accurately plan the timing according to the actual running time. When the CLA interrupt running time is much shorter than the CPU, the CLA resource utilization is low. Summary of the invention

[0010] The purpose of the present invention is to provide an embedded timing architecture operating system and operating method based on a DSP chip to solve the above problems.

[0011] To achieve the above object, the present invention adopts the following technical solutions: In the first aspect, the present invention provides an embedded timing architecture operating system based on a DSP chip, including a power module and a control module. The power module is connected to the control module, the power module is used for power conversion, and the control module is used for operation allocation. The allocated floating-point operations and fixed-point operations are executed in the CLA and the CPU respectively.

[0012] Furthermore, the power module includes a source side, a source side electrical network, a converter, a load side electrical network and a load side. The source side, the source side electrical network, the converter, the load side electrical network and the load side are connected in sequence. The converter receives the electric energy transmitted from the source side electrical network, and the converted electric energy is transmitted to the load side through the load side electrical network.

[0013] Furthermore, the load-side electrical network is also connected to hardware protection, which is connected to the drive circuit. The hardware protection reads the status quantity and loads the enable or disable signal to the drive circuit and the control module.

[0014] Furthermore, the control module includes sampling signals, a main control state machine, data preprocessing, control signal coupling, modulation drive and communication. The sampling signals are output through the circuits on the source side and the load side, and are sent to the control chip through hardware filtering and the ADC port. The control chip performs floating-point operations and is executed in the CLA. The main control state machine is placed in the CPU for operation, and the output instructions of the control signals are coupled with the AC signals containing phase information after data preprocessing in the CLA for control signals, and are sent to the modulation drive. The modulation drive is performed in the CLA.

[0015] In a second aspect, the present invention provides an operation method of an embedded timing architecture operation system based on a DSP chip, comprising the following steps: Initialize system clock and interrupts; After initialization is completed, timing design is performed to obtain the actual CPU running time, timer interrupt cycle and CLA operating frequency; Based on the actual CPU running time, timer interrupt cycle and CLA running frequency, a nested interrupt execution mechanism is introduced and combined with the CPU / CLA parallel mechanism. The main processing interrupt and ADC sampling interrupt in the CPU are designed to be nested and trigger the CLA task interrupt in the ADC.

[0016] Furthermore, the system clock and interrupts are initialized, including: After CLA is initialized, CLATask8 with the lowest priority is triggered to initialize the global variables set in CLA, and a flag is set to 1 after the initialization process is completed, otherwise it remains cleared, and then the peripherals and timers are initialized and the interrupt is started.

[0017] Furthermore, after the initialization is completed, the timing design is performed to obtain the actual CPU running time, timer interrupt cycle and CLA running frequency, including: The actual running time of CPU timer Timer0 is t cpur , the ADC interrupt frequency is consistent with the switching frequency f sw , each running time is t irqa , after nesting with the timer interrupt, the CPU timer is extended to t cpup , leaving a margin t re Meet at least 1 sampling time and communication execution time t irqc, set the CPU timer interrupt period to T cpus , that is, the loop calculation frequency is f cpus In summary, the actual CPU running time t cpup satisfy (1) Use the following approximate calculation for design: (2) The timer interrupt period is T cpus satisfy: (3) The ADC interrupt frequency triggers CLA modulation every n times, and the CLA running time t clar Calculate the CLA operating frequency f clas : (4) At power frequency f g Under the AC input, we get n f = f clas / f g Drive calculation of each point.

[0018] Furthermore, the nested interrupt execution mechanism is introduced and combined with the CPU / CLA parallel mechanism. The main processing interrupt in the CPU and the ADC sampling interrupt are designed to be nested and trigger the CLA task interrupt in the ADC, including: The ADC interrupt and the CPU timer Timer0 interrupt are nested to make the ADC trigger the CLA task every n times; for the ADC interrupt, EPWMx is used to generate a SOC signal for triggering at the point where the driving waveform does not change; for the communication mechanism used for debugging, the interrupt communication method is adopted, and at the communication interrupt service function, the data is pushed into the hardware for automatic transmission and reception, so that data reading and data sending are completed in the gap between each CPU timer Timer0 interrupt and the ADC interrupt that does not participate in the nesting.

[0019] Further, specific: The CPU OS executes interrupt mechanism management. The interrupts are CPU timer interrupts, ADC interrupts, and communication interrupts. Use the multiplexed interrupts of the PIE module and set the interrupt priority using the created mask value to achieve software nested interrupts. The specific steps are as follows: (1) Set global priority: modify the IER to allow CPU interrupts from the same PIE group as the current ISR, modify the IER to allow servicing of CPU interrupts with higher user-defined priorities; (2) Set group priority: Save the current PIEIERx value to a temporary register, and then set the PIEIER register to allow servicing of interrupts with higher priority in the PIE group; (3) Enable interrupts: Enable all PIE interrupts by writing all 1s to the PIEACK register; enable global interrupts by clearing INTM; (4) The interrupt service function ISR is executed. The interrupt with a higher software priority enabled in steps (1)-(3) will be allowed to interrupt the current ISR and be serviced first; (5) Restore the PIEIERx register and exit.

[0020] Furthermore, for the CPU timer 0 interrupt, the sampling automatic debiasing program is first executed in the initial few interrupts. When the sampling automatic debiasing is completed, the bias value is transmitted to the CLA through CPUtoCLARam; secondly, the flag bit of the global variable initialization in the CLA is detected. If completed, the CLA can normally run the data preprocessing and drive modulation instructions, that is, the CPU starts to execute the control program, otherwise, the CLA will be blocked, and the interrupt nesting program is executed in the control program to assign all the PIEACK registers that are automatically cleared by the hardware to 1, that is, the OS can push the ADC interrupt instruction into the instruction stack to achieve nesting.

[0021] Compared with the prior art, the present invention has the following technical effects: The present invention realizes modular design by separating the power module (responsible for power conversion) from the control module (responsible for operation distribution), which facilitates the maintenance and upgrading of the system.

[0022] Allocation of floating-point operations and fixed-point operations: Utilizing the CLA (control law accelerator) and CPU of the DSP chip to allocate floating-point operations and fixed-point operations fully utilizes the computing power of the DSP chip and improves the overall efficiency of system data processing and logical operations.

[0023] The present invention introduces a nested interrupt execution mechanism to allow nested execution between an ADC interrupt and a CPU timer interrupt, thereby improving the flexibility and response speed of interrupt processing.

[0024] The parallel working mechanism of CPU and CLA further improves the system's processing power and response speed, especially under high load conditions, to ensure stable operation of the system.

[0025] The present invention ensures high-precision timing control of the system by accurately calculating and designing the actual CPU running time, the timer interrupt cycle and the CLA running frequency, which is crucial for the stable operation of the power conversion module. By reasonably setting the interrupt cycle, full utilization of system resources is achieved while avoiding unnecessary waste of resources.

[0026] The present invention introduces a hardware protection mechanism into the load-side power network, which can monitor the circuit status in real time and quickly take protective measures in abnormal situations, thereby ensuring the safety of the system.

[0027] The present invention abstracts the function of the power conversion module so that the system can be applied to different AC / DC conversion systems and has good versatility. By making full use of the resources of low-end domestic chips, efficient control and drive are achieved, the system cost is reduced, and the scalability of the system is improved.

[0028] In summary, this technical solution achieves efficient control and precise driving of the power conversion module by optimizing the system architecture, introducing an efficient interrupt management mechanism, precise timing design, and improving system reliability and stability, and has significant technical effects and gain effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the module abstraction design and the parallel allocation of DSP internal resources CPU-CLA adopted by the present invention.

[0030] Figure 2 This is a schematic diagram of the overall timing of the software operation used in the present invention.

[0031] Figure 3 This is an overall logic block diagram of the software used in the present invention.

[0032] Figure 4 This is a schematic diagram of the multiplexing interruption of the PIE module used in the analysis of the present invention.

[0033] Figure 5 This is a schematic diagram of the CPU main control and CLA operation logic used in the analysis of the present invention.

[0034] Figure 6 Schematic diagram of the state machine used in the analysis of the present invention.

[0035] Figure 7 This is a schematic diagram of the timing framework operation results used in the analysis of the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described below in conjunction with the accompanying drawings: Example 1, please refer to Figure 1The present invention provides an embedded timing architecture operating system based on a DSP chip, including a power module and a control module. The power module is connected to the control module, the power module is used for power conversion, and the control module is used for operation allocation. The allocated floating-point operations and fixed-point operations are executed in the CLA and the CPU respectively.

[0037] The present invention realizes modular design by separating the power module (responsible for power conversion) from the control module (responsible for operation distribution), which facilitates the maintenance and upgrading of the system.

[0038] Allocation of floating-point operations and fixed-point operations: Utilizing the CLA (control law accelerator) and CPU of the DSP chip to allocate floating-point operations and fixed-point operations fully utilizes the computing power of the DSP chip and improves the overall efficiency of system data processing and logical operations.

[0039] Embodiment 2, the present invention provides an embedded timing architecture operation system based on a DSP chip, specifically comprising: It is divided into two parts: power module and control module. The power module can be divided into five parts: source side, source side electrical network, converter, load side electrical network and load side. The electrical networks of source side and load side include filter network, sampling circuit, etc. The converter is a conversion topology built based on power semiconductor devices. Hardware protection reads the relevant state quantity and directly loads the enable or disable signal to the IO port of the drive circuit and the control chip to obtain a fast protection response in the most extreme case.

[0040] For the control module, there are mainly several parts, such as sampling, main control state machine, data preprocessing, control, modulation drive, and communication. The sampling signal of the control object is output through the circuits on the source side and the load side, and is sent to the control chip through the hardware filtering link and the ADC port. Since the AC and DC data involve relatively complex filtering calculations, frequency phase extraction, coordinate transformation and other preprocessing, it involves more floating-point operations, so the data preprocessing is placed in the CLA for execution. The main control state machine mainly involves logical operations, so it is placed in the CPU for operation. Since the closed-loop control of the DC signal in the control algorithm of the AC / DC conversion has a low loop cutoff frequency and does not require a high response speed, it is placed in the CPU for operation. The output instruction of the control signal is coupled with the AC signal containing phase information after data preprocessing in the CLA and sent to the modulation drive. Since the modulation drive algorithm, especially the space vector modulation, often involves complex floating-point operations, it is also placed in the CLA.

[0041] Therefore, complex floating-point operations and driving algorithms are placed in the CLA for processing, giving full play to the efficiency of CLA in floating-point operations and improving calculation speed and accuracy. At the same time, fixed-point operations, state machine logic, and instruction setting tasks are assigned to the CPU for processing, taking advantage of the stability and accuracy of the CPU in processing fixed-point operations to increase the efficiency of system resource utilization.

[0042] Embodiment 3, the operation method of the embedded timing architecture operation system based on the DSP chip comprises: Depend on Figure 2 The figure shows a timing architecture diagram combining the nested interrupt execution mechanism with the CPU / CLA parallel mechanism. In order to make the modulation driver running in the CLA more densely distributed in the time domain, the ADC interrupt and the CPU timer Timer0 interrupt are nested, so that the ADC triggers the CLA task every n times. For the ADC interrupt, EPWMx is used to generate a SOC signal for triggering at the point where the drive waveform does not change. For the communication mechanism used for debugging, the interrupt communication method is used. At the communication interrupt service function, the data is pushed into the hardware for self-transmission, so that data reading and data transmission are completed in the execution gap between each CPU timer Timer0 interrupt and the ADC interrupt that does not participate in the nesting.

[0043] Based on the above principles, the timing design is performed. Assume that the actual running time of CPU timer Timer0 is t cpur , the ADC interrupt frequency is consistent with the switching frequency f sw , each running time is t irqa , after nesting with the timer interrupt, the CPU timer is extended to t cpup , leaving a margin t re Meet at least 1 sampling time and communication execution time t irqc , set the CPU timer interrupt period to T cpus , that is, the loop calculation frequency is f cpus In summary, the actual CPU running time t cpup satisfy (1) The following approximate calculation can be used for design: (2) The timer interrupt period is T cpus satisfy: (3) The ADC interrupt frequency triggers CLA modulation every n times, which can be determined by the CLA running time. t clar Calculate the CLA operating frequency f clas : (4) At power frequency f g Under the AC input, we can get n f = f clas / f g Drive calculation of each point.

[0044] The specific execution process of the program is as follows Figure 3 shown.

[0045] First, initialization is performed, including initializing the system clock, interrupts, copying flash code into RAM, etc. After initializing CLA, CLATask8 with the lowest priority is triggered, initializing the global variables set in CLA, and setting a flag to 1 after the initialization process is completed, otherwise it remains cleared. Then, the relevant peripherals and timers are initialized, and the relevant interrupts are started.

[0046] The CPU OS executes interrupt mechanism management. The main interrupts are CPU timer interrupt, ADC interrupt and communication interrupt. Since DSP hardware does not support interrupt nesting, interrupt nesting is performed by software. The schematic diagram of multiplexing interrupts using PIE module is as follows Figure 4 As shown. According to the DEV USER GUIDE officially provided by Ti, the specific steps to set the interrupt priority using the created mask value to achieve software nested interrupts are: Therefore, for the CPU timer 0 interrupt, firstly, the sampling automatic debiasing program is executed in the initial several interrupts. When the sampling automatic debiasing is completed, the bias value is transferred to the CLA through CPUtoCLARam to prepare for data preprocessing. Secondly, the flag bit of the global variable initialization in the CLA is detected. If it is completed, the CLA can run the data preprocessing and drive modulation instructions normally, that is, the CPU starts to execute the control program, otherwise the CLA will be blocked. In the control program, the interrupt nesting program is executed according to the above steps, and the PIEACK register that is automatically cleared by the hardware is assigned to 1, that is, the OS can push the ADC interrupt instruction into the instruction stack to achieve nesting. Count in the ADC interrupt, and trigger the CLA through IACK every n times. The communication interrupt does not participate in the nesting, and only reads and writes the transceiver register in the remaining interrupt intervals.

[0047] like Figure 5 As shown, in the main control function of CPUtimer0, the state machine function of the object X is first executed. Then the startup function is executed, the state is set according to the instruction symbol output by the state machine, and a closed-loop operation is performed.

[0048] In the CLA task interrupt, the sampling program can be executed in the highest priority CLATask1 to ensure that the sampling program is executed first, followed by the execution of the relevant code in CLATask2, including data preprocessing, control signal coupling, modulation drive, etc., and assigning values ​​to relevant registers. The relevant signals of data preprocessing are transmitted to the CPU through CLAtoCPURam to execute the relevant algorithm instructions.

[0049] The state machine is written in the form of function pointers, and its index value X_State is declared as enum type, its element name represents the state, and the index value corresponds to the set function pointer. Compared with ifelse statements and switch statements, this method can greatly reduce instruction storage space and reduce a certain amount of running time.

[0050] For the state machine itself Figure 6 As shown in the figure, the design state enumeration elements {X_Reset, X_Run, X_StoR, X_RtoS} represent four states, namely X reset, X run, X reset to run, and X run to reset. The last two are critical states. In order to prevent the spike noise of the sampling or protection signal from causing the state machine to trigger falsely, a threshold is set in the critical state, and the counts of the trigger conditions are added or subtracted to perform de-jitter filtering to ensure the stability of the state. At the same time, the size of the threshold can be designed according to the response speed and the degree of protection.

[0051] like Figure 7 As shown in the figure, a related program architecture is built on a hardware platform according to the above method, and the IO port is used to output the execution time of each program module. The ADC interrupt frequency is 200kHz, and the CLA is triggered every 5 times. The CLA control frequency is designed to be 40kHz, and the actual measurement is 39.28kHz; the CPU timer control frequency is designed to be 12kHz, and the actual measurement is 11.7kHz, which meets the design requirements.

[0052] The present invention abstractly designs the functions of the power conversion module, allocates the part suitable for floating-point operations to be executed in the CLA, and allocates the part suitable for fixed-point operations to be executed in the CPU, thereby improving the overall efficiency of system data processing and logic operations.

[0053] The present invention introduces a nested interrupt execution mechanism combined with a CPU / CLA parallel mechanism, designs the main processing interrupt and the ADC sampling interrupt in the CPU to be designed as nested execution, and triggers the CLA task interrupt in the ADC, accurately designs the relevant interrupt cycle according to the execution time, improves the density of timing processing, and can also ensure the operating efficiency of the system under high load conditions.

[0054] The present invention compiles a main control state machine to prevent system malfunctions, including mis-startup or mis-protection. State machine instructions are compiled in a function pointer manner, which greatly reduces instruction storage space and makes the digital processing system architecture more perfect.

[0055] The embedded system architecture proposed by the present invention can greatly improve the drive update frequency of the system, and can output higher quality waveforms for AC systems, especially medium and high frequency AC systems; The embedded system architecture proposed by the present invention fully utilizes the resources of low-end domestic chips and has good versatility for any AC-DC conversion system.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. The embedded timing architecture operation system based on DSP chip is characterized by: It includes a power module and a control module. The power module is connected to the control module. The power module is used for electric energy conversion. The control module is used for operation distribution. The distributed floating-point operations and fixed-point operations are executed in CLA and CPU respectively.

2. The embedded timing architecture operation system based on DSP chip according to claim 1, characterized in that: The power module includes a source side, a source side electrical network, a converter, a load side electrical network and a load side. The source side, the source side electrical network, the converter, the load side electrical network and the load side are connected in sequence. The converter receives the electric energy transmitted from the source side electrical network, and the converted electric energy is transmitted to the load side through the load side electrical network.

3. The embedded timing architecture operation system based on DSP chip according to claim 2, characterized in that: The load-side electrical network is also connected to hardware protection, which is connected to the drive circuit. The hardware protection reads the status quantity and loads the enable or disable signal to the drive circuit and the control module.

4. The embedded timing architecture operation system based on DSP chip according to claim 2 is characterized in that: The control module includes sampling signals, a main control state machine, data preprocessing, control signal coupling, modulation drive and communication. The sampling signals are output through the circuits on the source side and the load side, and are sent to the control chip through hardware filtering and the ADC port. The control chip performs floating-point operations and executes them in the CLA. The main control state machine is placed in the CPU for operation. The output instructions of the control signals are coupled with the AC signals containing phase information after data preprocessing in the CLA, and sent to the modulation drive. The modulation drive is performed in the CLA.

5. The operating method of the embedded timing architecture operating system based on the DSP chip is characterized in that: The embedded timing architecture operation system based on the DSP chip according to any one of claims 1 to 4 comprises the following steps: Initialize system clock and interrupts; After initialization is completed, timing design is performed to obtain the actual CPU running time, timer interrupt cycle and CLA operating frequency; Based on the actual CPU running time, timer interrupt cycle and CLA running frequency, a nested interrupt execution mechanism is introduced and combined with the CPU / CLA parallel mechanism. The main processing interrupt and ADC sampling interrupt in the CPU are designed to be nested and trigger the CLA task interrupt in the ADC.

6. The operating method of the embedded timing architecture operating system based on the DSP chip according to claim 5, characterized in that: Initialize system clock and interrupts, including: After CLA is initialized, CLATask8 with the lowest priority is triggered to initialize the global variables set in CLA, and a flag is set to 1 after the initialization process is completed, otherwise it remains cleared, and then the peripherals and timers are initialized and the interrupt is started.

7. The operating method of the embedded timing architecture operating system based on the DSP chip according to claim 5, characterized in that: After initialization, the timing design is performed to obtain the actual CPU running time, timer interrupt cycle and CLA running frequency, including: The actual running time of CPU timer Timer0 is t cpur , the ADC interrupt frequency is consistent with the switching frequency f sw , each running time is t irqa , after nesting with the timer interrupt, the CPU timer is extended to t cpup , leaving a margin t re Meet at least 1 sampling time and communication execution time t irqc , set the CPU timer interrupt period to T cpus , that is, the loop calculation frequency is f cpus In summary, the actual CPU running time t cpup satisfy (1) Use the following approximate calculation for design: (2) The timer interrupt period is T cpus satisfy: (3) The ADC interrupt frequency triggers CLA modulation every n times, and the CLA running time t clar Calculate the CLA operating frequency f clas : (4) At power frequency f g Under the AC input, we get n f = f clas / f g Drive calculation of each point.

8. The operating method of the embedded timing architecture operating system based on the DSP chip according to claim 5, characterized in that: The nested interrupt execution mechanism is introduced and combined with the CPU / CLA parallel mechanism. The main processing interrupt and ADC sampling interrupt in the CPU are designed to be nested and trigger the CLA task interrupt in the ADC, including: The ADC interrupt and the CPU timer Timer0 interrupt are nested to make the ADC trigger the CLA task every n times; for the ADC interrupt, EPWMx is used to generate a SOC signal for triggering at the point where the driving waveform does not change; for the communication mechanism used for debugging, the interrupt communication method is adopted, and at the communication interrupt service function, the data is pushed into the hardware for automatic transmission and reception, so that data reading and data sending are completed in the gap between each CPU timer Timer0 interrupt and the ADC interrupt that does not participate in the nesting.

9. The operating method of the embedded timing architecture operating system based on the DSP chip according to claim 8, characterized in that: Specific: The CPU OS executes interrupt mechanism management. The interrupts are CPU timer interrupts, ADC interrupts, and communication interrupts. Use the multiplexed interrupts of the PIE module and set the interrupt priority using the created mask value to achieve software nested interrupts. The specific steps are as follows: (1) Set global priority: modify the IER to allow CPU interrupts from the same PIE group as the current ISR, modify the IER to allow servicing of CPU interrupts with higher user-defined priorities; (2) Set group priority: Save the current PIEIERx value to a temporary register, and then set the PIEIER register to allow servicing of interrupts with higher priority in the PIE group; (3) Enable interrupts: Enable all PIE interrupts by writing all 1s to the PIEACK register; enable global interrupts by clearing INTM; (4) The interrupt service function ISR is executed. The interrupt with a higher software priority enabled in steps (1)-(3) will be allowed to interrupt the current ISR and be serviced first; (5) Restore the PIEIERx register and exit.

10. The operating method of the embedded timing architecture operating system based on the DSP chip according to claim 9, characterized in that: For the CPU timer 0 interrupt, firstly, the sampling automatic debiasing program is executed in the initial few interrupts. When the sampling automatic debiasing is completed, the bias value is transferred to the CLA through CPUtoCLARam. Secondly, the flag bit of the global variable initialization in the CLA is detected. If it is completed, the CLA can normally run the data preprocessing and drive modulation instructions, that is, the CPU starts to execute the control program. Otherwise, the CLA will be blocked and the interrupt nesting program will be executed in the control program. The PIEACK register that is automatically cleared by the hardware is assigned to 1. That is, the OS can push the ADC interrupt instruction into the instruction stack to achieve nesting.

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