Motor safety control circuit

Abstract

The invention discloses a motor safety control circuit which comprises a logic circuit, a motor safety turn-off circuit and an isolation drive circuit. The first output end of the logic circuit is connected with the first input end of the motor safety turn-off circuit, the first input end of the logic circuit inputs a safety state signal, and the second input end of the logic circuit inputs a PWM control signal; the logic circuit is used for carrying out AND on the PWM control signal, the safety state signal and the power supply signal and then outputting a first control signal; the first output end of the motor safety turn-off circuit is connected with the first input end of the driving chip, the second output end of the motor safety turn-off circuit is connected with the input end of the isolation driving circuit, and the output end of the isolation driving circuit is connected with the second input end of the driving chip; the motor safety turn-off circuit is used for outputting a normal driving signal or an active short circuit signal according to the first control signal, and the active short circuit signal is used for driving the chip to carry out active short circuit. The method is high in safety, short in response time and simple in hardware design.

Description

Technical Field

[0001] The present invention relates to the field of motor control, and in particular to a motor safety control circuit. Background Art

[0002] In motor control, the drive circuit is crucial. With the development of new energy vehicles, the application of silicon carbide (SIC) modules is becoming more and more widespread. In complex motor control, the traditional discrete drive structure has become increasingly unable to meet the requirements of various car manufacturers due to its delay and reliability. The application of integrated drive chips has become a trend for various car manufacturers. In case of failure, it can be cut off immediately to meet the requirements of various car manufacturers for functional safety automotive safety integrity level D (ASIL-D). Summary of the invention

[0003] The present invention provides a motor safety control circuit, which can realize active short circuit of a driving chip when a fault occurs.

[0004] According to one aspect of the present invention, there is provided a motor safety control circuit, comprising: a logic circuit, a motor safety shutdown circuit and an isolation drive circuit;

[0005] The first output end of the logic circuit is connected to the first input end of the motor safety shutdown circuit, the first input end of the logic circuit inputs a safety state signal, and the second input end of the logic circuit inputs a PWM control signal; the logic circuit is used to output a first control signal after performing AND operation on the PWM control signal, the safety state signal and the power supply signal;

[0006] The first output end of the motor safety shutdown circuit is connected to the first input end of the driver chip, the second output end of the motor safety shutdown circuit is connected to the input end of the isolation drive circuit, and the output end of the isolation drive circuit is connected to the second input end of the driver chip; the motor safety shutdown circuit is used to output a normal drive signal or an active short-circuit signal according to the first control signal, and the active short-circuit signal is used to control the driver chip to perform an active short circuit.

[0007] Optionally, the logic circuit includes a first resistor, a first filter circuit, a first AND gate and a second filter circuit;

[0008] A first end of the first resistor is connected to an input end of the first filter circuit and connected to a PWM control signal, a second end of the first resistor is grounded, and an output end of the first filter circuit is connected to a first input end of the first AND gate;

[0009] The second input of the first AND gate is connected to the power supply signal; the input of the second filter circuit is connected to the safety status signal, and the output of the second filter circuit is connected to the third input of the first AND gate; the output of the first AND gate is connected to the first input of the motor safety shutdown circuit.

[0010] Optionally, the first filtering circuit includes a second resistor and a first capacitor;

[0011] The first end of the second resistor is connected to the first end of the first resistor, the second end of the second resistor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, and the first end of the first capacitor is connected to the first input end of the first AND gate;

[0012] The second filtering circuit includes a third resistor and a second capacitor; the first end of the third resistor is connected to the safety state signal, the second end of the third resistor is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, and the first end of the second capacitor is connected to the third input end of the first AND gate;

[0013] The logic circuit further includes a fourth resistor and a third capacitor;

[0014] The first end of the fourth resistor is connected to the output end of the first AND gate, the output end of the first AND gate outputs a first control signal, the second end of the fourth resistor is connected to the first end of the third capacitor, the second end of the third capacitor is grounded, and the first end of the third capacitor outputs a second control signal.

[0015] Optionally, the motor safety shutdown circuit includes a third filtering circuit, a first clamping and filtering circuit, a second AND gate and a first driving circuit;

[0016] The input end of the third filter circuit inputs the first input signal, and the output end of the third filter circuit is connected to the first input end of the second AND gate;

[0017] The input end of the first clamping and filtering circuit is connected to the first output end of the logic circuit, and the output end of the first clamping and filtering circuit is connected to the second input end of the second AND gate; the first clamping and filtering circuit is used to limit the signal amplitude and filter the signal;

[0018] The output end of the second AND gate is connected to the input end of the first driving circuit, and the output end of the first driving circuit is connected to the first input end of the driving chip;

[0019] The motor safety shutdown circuit also includes a second clamping and filtering circuit, a voltage dividing circuit, a comparison circuit and a second driving circuit;

[0020] The input end of the second clamping and filtering circuit is connected to the first output end of the logic circuit, the output end of the second clamping and filtering circuit is connected to the first input end of the comparison circuit, the output end of the voltage divider circuit is connected to the second input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the second drive circuit, and the output end of the second drive circuit is connected to the input end of the isolation drive circuit.

[0021] Optionally, the first clamping and filtering circuit includes a fourth capacitor, a fifth resistor, a first diode, a second diode, a sixth resistor, a fifth capacitor and a seventh resistor;

[0022] The first end of the fourth capacitor is connected to the first output end of the logic circuit, the second end of the fourth capacitor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the cathode of the first diode, the anode of the first diode is grounded, the anode of the second diode is connected to the cathode of the first diode, the cathode of the second diode is connected to the first end of the sixth resistor, the second end of the sixth resistor is grounded, the fifth capacitor is connected in parallel with the sixth resistor, the first end of the seventh resistor is connected to the first end of the fifth capacitor, and the second end of the seventh resistor is connected to the second input end of the second AND gate.

[0023] Optionally, the first driving circuit includes a ninth resistor, a tenth resistor, a seventh capacitor, a first NMOS transistor, an eleventh resistor and an eighth capacitor;

[0024] The first end of the ninth resistor is connected to the output end of the second AND gate, the second end of the ninth resistor is connected to the first end of the tenth resistor, the second end of the tenth resistor is grounded, the first end of the seventh capacitor and the first end of the tenth resistor are connected to the first electrode of the first NMOS tube, the second end of the seventh capacitor is grounded, the second electrode of the first NMOS tube is grounded, the first end of the eleventh resistor and the first end of the eighth capacitor are connected to the third electrode of the first NMOS tube, the second end of the eleventh resistor is connected to the power supply, the second end of the eighth capacitor is grounded, and the third electrode of the first NMOS tube is connected to the first input end of the driving chip.

[0025] Optionally, the second clamping and filtering circuit includes a ninth capacitor, a twelfth resistor, a third diode, a fourth diode, a thirteenth resistor and a tenth capacitor;

[0026] The first end of the ninth capacitor is connected to the first output end of the logic circuit, the second end of the ninth capacitor is connected to the first end of the twelfth resistor, the second end of the twelfth resistor is connected to the cathode of the third diode, the anode of the third diode is grounded, the anode of the fourth diode is connected to the cathode of the third diode, the cathode of the fourth diode is connected to the first end of the thirteenth resistor, the second end of the thirteenth resistor is grounded, and the tenth capacitor is connected in parallel with the thirteenth resistor.

[0027] Optionally, the voltage divider circuit includes a fourteenth resistor, a sixteenth resistor, and a seventeenth resistor;

[0028] The first end of the fourteenth resistor is grounded, the second end of the fourteenth resistor is connected to the first end of the seventeenth resistor, the second end of the seventeenth resistor is connected to the first end of the sixteenth resistor, and the second end of the sixteenth resistor is connected to the power signal.

[0029] Optionally, the comparison circuit includes an eleventh capacitor, a fifteenth resistor, a first comparator, a twelfth capacitor, a second comparator and an eighteenth resistor;

[0030] The first end of the eleventh capacitor is connected to the second end of the fourteenth resistor, and the second end of the eleventh capacitor is grounded. The first end of the fifteenth resistor is connected to the first end of the eleventh capacitor, and the second end of the fifteenth resistor is connected to the output end of the first comparator. The first input end of the first comparator is connected to the output end of the second clamping and filtering circuit, and the second input end of the first comparator is connected to the first end of the eleventh capacitor. The first end of the twelfth capacitor is connected to the second end of the seventeenth resistor, and the second end of the twelfth capacitor is grounded. The first end of the eighteenth resistor is connected to the first end of the twelfth capacitor, and the second end of the eighteenth resistor is connected to the output end of the second comparator. The first input end of the second comparator is connected to the first end of the twelfth capacitor, and the second input end of the second comparator is connected to the output end of the second clamping and filtering circuit.

[0031] Optionally, the second driving circuit includes a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a fourteenth capacitor, a fifteenth capacitor and a second NMOS transistor;

[0032] A first end of the nineteenth resistor is connected to the output end of the comparison circuit, a second end of the nineteenth resistor is connected to a power supply signal, a first end of the twentieth resistor is connected to the first end of the nineteenth resistor, a second end of the twentieth resistor is connected to the first end of the fourteenth capacitor, a second end of the fourteenth capacitor is grounded, a first electrode of the second NMOS tube is connected to the first end of the fourteenth capacitor, a second electrode of the second NMOS tube is grounded, a third electrode of the second NMOS tube is connected to the first end of the twenty-first resistor, a second end of the twenty-first resistor is connected to a power supply signal, a first end of the fifteenth capacitor is connected to the first end of the twenty-first resistor, and a second end of the fifteenth capacitor is grounded.

[0033] The technical solution of the embodiment of the present invention is through a logic circuit, a motor safety shutdown circuit and an isolation drive circuit; the logic circuit is connected to the motor safety shutdown circuit, and the logic circuit outputs a first control signal after the PWM control signal, the safety status signal and the power supply signal are ANDed; the motor safety shutdown circuit is connected to the drive chip and the isolation drive circuit, and the isolation drive circuit is connected to the drive chip; the motor safety shutdown circuit outputs a normal drive signal or an active short-circuit signal according to the first control signal. If there is no fault, the motor safety shutdown circuit outputs a normal drive signal, and the drive chip drives the motor to operate normally. When a fault occurs, the motor safety shutdown circuit outputs an active short-circuit signal to control the drive chip to perform an active short circuit. The technical solution of the embodiment of the present invention has high safety, fast response time of the drive chip, simple hardware design logic, few discrete devices used, and less area required for layout.

[0034] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of the structure of a motor safety control circuit provided according to an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a logic circuit provided according to an embodiment of the present invention;

[0038] Figure 3A schematic diagram of a partial circuit of a motor safety shutdown circuit provided according to an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of another circuit portion of a motor safety shutdown circuit provided according to an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of an isolation driving circuit provided for implementing an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Figure 1 This is a schematic diagram of the structure of a motor safety control circuit provided by an embodiment of the present invention. This embodiment can be applied to the case of protecting the drive circuit in motor control. The circuit can be implemented in the form of hardware and / or software. The circuit can be configured in industries and fields involving motor applications, such as household appliances, medical equipment, industrial automation, and new energy vehicles. Figure 1 As shown, the circuit includes: a logic circuit 101 , a motor safety shutdown circuit 102 and an isolation drive circuit 103 .

[0044] The first output end of the logic circuit 101 is connected to the first input end of the motor safety shutdown circuit 102, the first input end of the logic circuit 101 inputs the safety status signal EN, and the second input end of the logic circuit 101 inputs the PWM control signal; the logic circuit 101 is used to output a first control signal after performing AND operation on the PWM control signal, the safety status signal EN and the power supply signal.

[0045] The first output end of the motor safety shutdown circuit 102 is connected to the first input end of the driver chip 104, the second output end of the motor safety shutdown circuit 102 is connected to the input end of the isolation drive circuit 103, and the output end of the isolation drive circuit 103 is connected to the second input end of the driver chip 104; the motor safety shutdown circuit 102 is used to output a normal drive signal or an active short-circuit signal according to the first control signal, and the active short-circuit signal is used to control the driver chip 104 to perform an active short circuit.

[0046] Among them, the driver chip 104 can be an integrated driver chip, and the integrated driver chip generally refers to integrating the drive circuit and the control circuit on one chip, which can reduce the number of external components, simplify the design, and improve reliability. The first input terminal of the driver chip 104 corresponds to the low-voltage side (DIS) shutdown pin of the driver chip, and the second input terminal of the driver chip 104 corresponds to the high-voltage side (BRK) shutdown pin of the driver chip. The motor active short circuit (Active Short Circuit, ASC) is used to ensure the safety of the electric drive system under specific conditions. When the electric drive system fails, ASC can ensure that the system enters a safe working state to prevent damage and potential safety risks. The working principle of ASC is to control the power module (such as IGBT) in the motor controller so that the motor stator winding forms a closed loop, thereby releasing the back electromotive force energy generated by the motor through the stator winding. Active short circuit can generally be divided into two modes: upper ASC and lower ASC. Specifically, the active short circuit protection safety working state can be achieved by turning off the three tubes SIC of the upper bridge arm and opening the three tubes of the lower bridge arm (lower ASC), or turning on the three tubes of the upper bridge arm and turning off the three tubes of the lower bridge arm (upper ASC). The motor safety control circuit provided by the embodiment of the present invention adopts the safety control strategy of the lower ASC, which enables the driver chip to respond quickly in the event of a fault, cuts off the three upper tubes (SIC), and turns on the three lower tubes (SIC). Because the lower ASC is grounded, it has more advantages when the motor releases energy. In the event of a fault, the DIS shutdown pin and the BRK shutdown pin of the driver chip are actively short-circuited, where the shutdown priority of the driver chip BRK is higher than that of DIS. That is, when the upper bridge BRK is grounded, the upper bridge DIS is high, the internal register defaults to 0, and the shutdown is executed (SIC is not turned on); when the lower bridge BRK is high, the internal register defaults to 1, and the turn-on is executed (SIC is turned on). When the lower bridge DIS is set high, the DIS internal register is set to 1 through software, and the turn-on is executed (SIC is turned on). Through the redundant design of BRK and DIS, the SIC conduction is double-controlled, which makes it safer.

[0047] The safety status signal EN is sent from the motor control system to indicate whether the motor is running under safe conditions and whether measures need to be taken to prevent potential dangerous situations. The safety status signal EN may include but is not limited to the detection and indication of abnormal conditions such as overload, overheating, overvoltage, undervoltage, short circuit, etc. After the PWM control signal, the safety status signal EN and the power supply signal are ANDed, the logic circuit 101 determines whether any one of them is faulty. If there is no fault, the first control signal is sent to the motor safety shutdown circuit 102, the motor safety shutdown circuit 102 outputs a normal drive signal, and the driver chip 104 drives the motor to operate normally. If any one of them fails, the first control signal is transmitted to the motor safety shutdown circuit 102, the motor safety shutdown circuit 102 outputs an active short-circuit signal, and the driver chip 104 is controlled to perform an active short-circuit. The microcontroller unit (MCU) is connected to the logic circuit 101, the motor safety shutdown circuit 102 and the driver chip 104 respectively. When the MCU reads any abnormal signal such as the upper bridge error feedback signal and the lower bridge error feedback signal and the overvoltage signal output by the logic circuit 101 and the driver chip 104, the safety control strategy of the lower ASC is implemented. Among them, the upper bridge error feedback signal and the lower bridge error feedback signal are used to feedback the error signal recognized by the driver chip.

[0048] The technical solution of the embodiment of the present invention is through a logic circuit, a motor safety shutdown circuit and an isolation drive circuit; through a logic circuit, a motor safety shutdown circuit and an isolation drive circuit; the logic circuit is connected to the motor safety shutdown circuit, and the logic circuit outputs a first control signal after the PWM control signal, the safety state signal and the power supply signal are ANDed; the motor safety shutdown circuit is connected to the driver chip and the isolation drive circuit, and the isolation drive circuit is connected to the driver chip; the motor safety shutdown circuit outputs a normal drive signal or an active short-circuit signal according to the first control signal, and if there is no fault, the first control signal is sent to the motor safety shutdown circuit, the motor safety shutdown circuit outputs a normal drive signal, and the driver chip drives the motor to operate normally. When a fault occurs, the first control signal is transmitted to the motor safety shutdown circuit, the motor safety shutdown circuit outputs an active short-circuit signal, and the driver chip is controlled to perform an active short circuit. The technical solution of the embodiment of the present invention has high safety, fast response time of the driver chip, simple hardware design logic, few discrete devices used, and less area required for layout.

[0049] Figure 2 FIG. 1 is a schematic diagram of a logic circuit provided according to an embodiment of the present invention. Figure 2 As shown, the circuit includes: a first resistor R1, a first filter circuit 201, a first AND gate U1 and a second filter circuit 202.

[0050] A first end of the first resistor R1 is connected to an input end of the first filter circuit 201 and receives a PWM control signal. A second end of the first resistor R1 is grounded. An output end of the first filter circuit 201 is connected to a first input end A of the first AND gate U1 .

[0051] The second input terminal B of the first AND gate U1 is connected to the power supply signal V1; the input terminal of the second filter circuit 202 is connected to the safety status signal EN, and the output terminal of the second filter circuit 202 is connected to the third input terminal C of the first AND gate U1; the output terminal Y of the first AND gate U1 is connected to the first input terminal of the motor safety shutdown circuit.

[0052] Among them, the first AND gate U1 is a three-input AND gate with three input terminals (A, B and C) and an output terminal Y. Only when the three input terminals are at a high level (logic 1) at the same time, the output terminal Y is at a high level (logic 1). If any input terminal is at a low level (logic 0), the output terminal Y is at a low level (logic 0). The first resistor R1 is a pull-down resistor, and the purpose is to make the initial state PWM low level valid. The power signal V1 can be a 5V power supply. When one or more of the PWM control signal, power signal V1 or safety status signal EN is at a low level, according to the characteristics of the AND gate logic device, the output is at a low level, indicating that the motor is working abnormally. When the system is working normally, the PWM control signal frequency given by the MCU is: 330KHZ, and the duty cycle is 50%. The power signal V1 is at a high level, the safety status signal EN is at a high level, and the output first control signal BRK_CTL is the same as the PWM control signal.

[0053] Optionally, the first filtering circuit 201 includes a second resistor R2 and a first capacitor C1;

[0054] A first end of the second resistor R2 is connected to a first end of the first resistor R1, a second end of the second resistor R2 is connected to a first end of the first capacitor C1, a second end of the first capacitor C1 is grounded, and a first end of the first capacitor C1 is connected to a first input end A of the first AND gate U1;

[0055] The second filtering circuit 202 includes a third resistor R3 and a second capacitor C2; a first end of the third resistor R3 is connected to the safety state signal EN, a second end of the third resistor R3 is connected to a first end of the second capacitor C2, a second end of the second capacitor C2 is grounded, and a first end of the second capacitor C2 is connected to a third input end C of the first AND gate U1;

[0056] Optionally, the logic circuit further includes a fourth resistor R4 and a third capacitor C3;

[0057] A first end of the fourth resistor R4 is connected to the output end Y of the first AND gate U1, and the output end Y of the first AND gate U1 outputs the first control signal BRK_CTL. A second end of the fourth resistor R4 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is grounded. The first end of the third capacitor C3 outputs the second control signal BRK_CTL_FB.

[0058] The fourth resistor R4 and the third capacitor C3 also form a first-level filter circuit, which is used for signal filtering processing like the first filter circuit 201 and the second filter circuit 202. The second control signal BRK_CTL_FB is fed back to the MCU in real time to increase safety.

[0059] Figure 3 A schematic diagram of a partial circuit of a motor safety shutdown circuit provided according to an embodiment of the present invention. Figure 4 FIG. 1 is a schematic diagram of another part of a motor safety shutdown circuit provided according to an embodiment of the present invention. Figure 3 As shown, the motor safety shutdown circuit includes a third filter circuit 301, a first clamp and filter circuit 302, a second AND gate U2 and a first drive circuit 303;

[0060] The input terminal of the third filter circuit 301 inputs the first input signal DIS_H, and the output terminal of the third filter circuit 301 is connected to the first input terminal A1 of the second AND gate U2;

[0061] The input end of the first clamping and filtering circuit 302 is connected to the first output end of the logic circuit, and the output end of the first clamping and filtering circuit 302 is connected to the second input end B1 of the second AND gate U2; the first clamping and filtering circuit 302 is used to limit the signal amplitude and filter the signal;

[0062] The output terminal Y1 of the second AND gate U2 is connected to the input terminal of the first driving circuit 303, and the output terminal of the first driving circuit 303 is connected to the first input terminal of the driving chip;

[0063] Among them, the first input signal DIS_H is filtered by the third filter circuit 301 and then input to the first input terminal A1 of the second AND gate U2. The first control signal BRK_CTL output by the logic circuit is limited in signal amplitude and filtered by the first clamp and filter circuit 302, and then input to the second input terminal B1 of the second AND gate U2. The output terminal Y1 of the second AND gate U2 is connected to the input terminal of the first drive circuit 303. The output terminal of the first drive circuit 303 is connected to the first input terminal of the driver chip. The first input terminal of the driver chip corresponds to the DIS shutdown pin of the driver chip. The embodiment of the present invention adopts a redundant design of BRK and DIS. The priority of BRK shutdown is higher than that of DIS. Therefore, the DIS shutdown pin is used as a redundant standby to better protect the various components in the system. Figure 4 As shown, the motor safety shutdown circuit also includes a second clamping and filtering circuit 401, a voltage dividing circuit 402, a comparison circuit 403 and a second driving circuit 404;

[0064] The input end of the second clamping and filtering circuit 401 is connected to the first output end of the logic circuit, the output end of the second clamping and filtering circuit 401 is connected to the first input end of the comparison circuit 403, the output end of the voltage divider circuit 402 is connected to the second input end of the comparison circuit 403, the output end of the comparison circuit 403 is connected to the input end of the second drive circuit, and the output end of the second drive circuit 404 is connected to the input end of the isolation drive circuit.

[0065] The first control signal BRK_CTL output by the logic circuit is input to the comparison circuit 403 after being limited and filtered by the second clamping and filtering circuit 401, and then input to the second driving circuit after the voltage is compared by the comparison circuit 403. The second driving circuit 404 controls the second input end of the driving chip through the isolation driving circuit, and the second input end of the driving chip corresponds to the BRK shutdown pin of the driving chip. Through the redundant design of BRK and DIS, the SIC is double-controlled to be turned on, which makes it safer.

[0066] In some optional embodiments of the present invention, continue to refer to Figure 3 , the first clamping and filtering circuit 302 includes a fourth capacitor C4, a fifth resistor R5, a first diode D1, a second diode D2, a sixth resistor R6, a fifth capacitor C5 and a seventh resistor R7;

[0067] A first end of the fourth capacitor C4 is connected to the first output end of the logic circuit, a second end of the fourth capacitor C4 is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a cathode of the first diode D1, an anode of the first diode D1 is grounded, an anode of the second diode D2 is connected to the cathode of the first diode D1, a cathode of the second diode D2 is connected to a first end of the sixth resistor R6, a second end of the sixth resistor R5 is grounded, the fifth capacitor C5 is connected in parallel with the sixth resistor R6, a first end of the seventh resistor R7 is connected to a first end of the fifth capacitor C5, and a second end of the seventh resistor R7 is connected to a second input end B of the second AND gate U2.

[0068] When the first control signal BRK_CTL is a square wave signal, the voltage of the fourth capacitor C4, the fifth resistor R5, the first diode D1, the second diode D2, the sixth resistor R6, and the fifth capacitor C5 fluctuates within a very small range, and the voltage value is determined according to the resistance and capacitance values. The first clamping and filtering circuit 302 utilizes the charging and discharging characteristics of the capacitor and the unidirectional conduction characteristics of the diode.

[0069] In some optional embodiments of the present invention, continue to refer to Figure 3, the first driving circuit 303 includes a ninth resistor R9, a tenth resistor R10, a seventh capacitor C7, a first NMOS transistor M1, an eleventh resistor R11 and an eighth capacitor C8;

[0070] A first end of the ninth resistor R9 is connected to the output end Y of the second AND gate U2, a second end of the ninth resistor R9 is connected to a first end of the tenth resistor R10, a second end of the tenth resistor R10 is grounded, a first end of the seventh capacitor C7 and a first end of the tenth resistor R10 are connected to a first electrode of the first NMOS tube M1, a second end of the seventh capacitor C7 is grounded, a second electrode of the first NMOS tube M1 is grounded, a first end of the eleventh resistor R11 and a first end of the eighth capacitor C8 are connected to a third electrode of the first NMOS tube M1, a second end of the eleventh resistor R11 is connected to a power supply V1, a second end of the eighth capacitor C8 is grounded, and a third electrode of the first NMOS tube M1 is connected to a first input end of the driving chip.

[0071] Among them, the ninth resistor R9 is a gate resistor, the tenth resistor R10 is a bias resistor, the seventh capacitor C7 is a bias capacitor, the eleventh resistor R11 is a pull-up resistor, and the eighth capacitor C8 is a filter capacitor. The gate of the first NMOS tube M1 is connected to the first end of the seventh capacitor C7, the source of the first NMOS tube M1 is grounded, the drain of the first NMOS tube M1 is connected to the first end of the eleventh resistor R11, and the drain of the first NMOS tube M1 is connected to the first input end of the driver chip, and the third control signal DIS_xH is output. The first NMOS tube M1 is inverted and the driving capability is enhanced at the same time. The first input end of the driver chip corresponds to the DIS shutdown pin of the driver chip, and the safety strategy of the ASC is implemented, that is, DIS_xH needs to be high.

[0072] Specifically, when the system is working normally, the first control signal BRK_CTL output by the logic circuit is input to the second input terminal A1 of the second AND gate U2, the first input signal DIS_H is input to the second input terminal B1 of the second AND gate U2, the first control signal BRK_CTL and the first input signal DIS_H are both high level, the first NMOS tube M1 is turned on, and the output third control signal DIS_xH is low level. When the system recognizes a fault, at this time, the first control signal BRK_CTL or the first input signal DIS_H is pulled low or both are pulled low at the same time, the second AND gate U2 outputs a low level, the first NMOS tube M1 is not turned on, and the output third control signal DIS_xH is a high level voltage.

[0073] In some optional embodiments of the present invention, continue to refer to Figure 4 , the second clamping and filtering circuit 401 includes a ninth capacitor C9, a twelfth resistor R15, a third diode D3, a fourth diode D4, a thirteenth resistor R16 and a tenth capacitor C10;

[0074] The first end of the ninth capacitor C9 is connected to the first output end of the logic circuit, the second end of the ninth capacitor C9 is connected to the first end of the twelfth resistor R15, the second end of the twelfth resistor R15 is connected to the cathode of the third diode D3, the anode of the third diode D3 is grounded, the anode of the fourth diode D4 is connected to the cathode of the third diode D3, the cathode of the fourth diode D4 is connected to the first end of the thirteenth resistor R13, the second end of the thirteenth resistor R16 is grounded, and the tenth capacitor C10 is connected in parallel to the thirteenth resistor R16.

[0075] Among them, when the first control signal BRK_CTL is a square wave signal, when passing through the ninth capacitor C9, the twelfth resistor R15, the third diode D3, the fourth diode D4, the thirteenth resistor R16 and the tenth capacitor C10, the voltage fluctuates in a very small range, and the voltage value is determined according to the values ​​of each resistor and capacitor.

[0076] In some optional embodiments of the present invention, continue to refer to Figure 4 The voltage divider circuit 402 includes a fourteenth resistor R17, a sixteenth resistor R19, and a seventeenth resistor R20.

[0077] The first end of the fourteenth resistor R17 is grounded, the second end of the fourteenth resistor R17 is connected to the first end of the seventeenth resistor R20, the second end of the seventeenth resistor R20 is connected to the first end of the sixteenth resistor R19, and the second end of the sixteenth resistor R19 is connected to the power signal V1.

[0078] The fourteenth resistor R17 , the sixteenth resistor R19 , and the seventeenth resistor R20 are voltage-dividing resistors of the comparison circuit 403 , and the resistance values ​​of the voltage-dividing resistors depend on system requirements.

[0079] In some optional embodiments of the present invention, continue to refer to Figure 4 The comparison circuit 403 includes an eleventh capacitor C11, a fifteenth resistor R18, a first comparator P1, a twelfth capacitor C12, a second comparator P2 and an eighteenth resistor R21.

[0080] A first end of the eleventh capacitor C11 is connected to a second end of the fourteenth resistor R17, a second end of the eleventh capacitor C11 is grounded, a first end of the fifteenth resistor R18 is connected to a first end of the eleventh capacitor C11, a second end of the fifteenth resistor R18 is connected to an output end of the first comparator P1, a first input end of the first comparator P1 is connected to an output end of the second clamping and filtering circuit 401, a second input end of the first comparator P1 is connected to a first end of the eleventh capacitor C11, a first end of the twelfth capacitor C12 is connected to a second end of the seventeenth resistor R20, a second end of the twelfth capacitor C12 is grounded, a first end of the eighteenth resistor R21 is connected to a first end of the twelfth capacitor C12, a second end of the eighteenth resistor R21 is connected to an output end of the second comparator P2, a first input end of the second comparator P2 is connected to a first end of the twelfth capacitor C12, and a second input end of the second comparator P2 is connected to an output end of the second clamping and filtering circuit 401.

[0081] Among them, the eleventh capacitor C11 and the twelfth capacitor C12 are filter capacitors, the fifteenth resistor R18 and the eighteenth resistor R21 are feedback resistors. The third input terminal of the second comparator P2 is connected to the power signal V1, and is connected to the first terminal of the thirteenth capacitor at the same time. The second terminal of the thirteenth capacitor is grounded, the fourth input terminal of the second comparator P2 is grounded, and the thirteenth capacitor C13 is a filter capacitor. Reference Figure 4 When the system is working normally, the first control signal BRK_CTL output by the logic circuit is used as the input of the comparison circuit 403. When the voltage at the TP1 point of the comparison circuit 403 is between V1*R17 / (R19+R20+R17) and V1*(R17+R20),

[0082] / (R19+R20+R17), the comparison circuit 403 outputs a high level. When the system recognizes a fault, the first control signal BRK_CTL is pulled low, and the voltage value at the TP1 point is less than

[0083] V1*R17 / (R19+R20+R17), the comparison circuit 403 outputs a low level. If the PWM control signal output by the MCU is abnormal, the voltage at the TP1 point of the comparison circuit 403 will be higher than V1*(R17+R20).

[0084] / (R19+R20+R17), the comparison circuit 403 will also output a low level.

[0085] In some optional embodiments of the present invention, continue to refer to Figure 4 , the second driving circuit 404 includes a nineteenth resistor R22, a twentieth resistor R23, a twenty-first resistor R24, a fourteenth capacitor C14, a fifteenth capacitor C15 and a second NMOS transistor M2;

[0086] A first end of the nineteenth resistor R22 is connected to the output end of the comparison circuit 403, a second end of the nineteenth resistor R22 is connected to the power signal V1, a first end of the twentieth resistor R23 is connected to the first end of the nineteenth resistor R22, a second end of the twentieth resistor R23 is connected to the first end of the fourteenth capacitor C14, a second end of the fourteenth capacitor C14 is grounded, a first electrode of the second NMOS tube M2 is connected to the first end of the fourteenth capacitor C14, a second electrode of the second NMOS tube M2 is grounded, a third electrode of the second NMOS tube M2 is connected to the first end of the twenty-first resistor R24, a second end of the twenty-first resistor R23 is connected to the power signal V1, a first end of the fifteenth capacitor C15 is connected to the first end of the twenty-first resistor R24, and a second end of the fifteenth capacitor is grounded.

[0087] Among them, the fifteenth resistor R18 and the nineteenth resistor R22, the twentieth resistor R23 are gate-level resistors, the twenty-first resistor R24 ​​is a pull-up resistor, the fourteenth capacitor C14 is a bias capacitor, the fifteenth capacitor C15 is a filter capacitor, the gate of the second NMOS tube M2 is connected to the first end of the fourteenth capacitor C14, the source of the second NMOS tube M2 is grounded, the drain of the second NMOS tube M2 is connected to the first end of the twenty-first resistor R24, and is connected to the second input end of the driver chip, outputs the fourth control signal BRK_xL, and the first NMOS tube M1 is inverted and the driving capability is enhanced at the same time. The second input end of the driver chip corresponds to the BRK shutdown pin of the driver chip, and the safety strategy of the ASC is implemented, that is, the third control signal DIS_xH and the fourth control signal BRK_xL need to be high at the same time.

[0088] Specifically, when the system is working normally, the first control signal BRK_CTL output by the logic circuit is used as the input of the comparison circuit 403. When the voltage at the TP1 point of the comparison circuit 403 is between V1*R17 / (R19+R20+R17) and V1*(R17+R20) / (R19+R20+R17), the comparison circuit 403 outputs a high level, the second NMOS tube M2 is turned on, and the fourth control signal BRK_xL is a low level. When the system identifies a fault, the first control signal BRK_CTL is pulled low, the voltage value at the TP1 point is less than V1*R17 / (R19+R20+R17), the comparison circuit 403 outputs a low level, the second NMOS tube M2 is not turned on, and the fourth control signal BRK_xL is a high level. If the PWM control signal output by the MCU is abnormal, causing the voltage at point TP1 of the comparison circuit 403 to be higher than V1*(R17+R20) / (R19+R20+R17), the comparison circuit 403 outputs a low level, the second NMOS tube M2 is not turned on, and the fourth control signal BRK_xL is a high level.

[0089] Figure 5A schematic diagram of an isolation driving circuit provided in an embodiment of the present invention is provided. Figure 5 As shown, the isolation drive circuit is composed of an isolation chip 501 and a drive unit 502. Since BRK is a high-voltage side shutdown pin, an isolation chip 501 is required. At the same time, a drive unit 502 is added, and the fourth control signal BRK_xL outputs a fifth control signal BRK_L through the isolation chip 501 and the drive unit 502 to control the shutdown pin of the driver chip BRK, thereby improving the driving capability of BRK. Because the shutdown priority of BRK is higher than DIS, this solution uses the BRK pin for shutdown, and the DIS pin is used as a redundant standby, which is safer and more reliable, and has a shorter response time, and better protects the various components in the system to avoid damage due to failure.

[0090] The embodiment of the present invention provides a motor safety control circuit, which implements the ASC safety strategy when the system fails, that is, the third control signal DIS_xH and the fourth control signal BRK_xL output by the motor safety shutdown circuit are required to be high at the same time. Figure 2 As shown, when one or more of the PWM control signal, power signal V1 or safety status signal EN is at a low level, the logic circuit outputs the first control signal BRK_CTL as a low level according to the logic characteristics of the first AND gate U1, and sends it to the motor safety shutdown circuit, and sends the second control signal BRK_CTL_FB to the MCU. When the MCU reads any abnormal signal such as the abnormal feedback signal output by the logic circuit, the upper bridge error feedback signal and the lower bridge error feedback signal output by the driver chip, and the overvoltage signal, the system fails. Figure 3 As shown, the first input signal DIS_H or the first control signal BRK_CTL is pulled low or both are pulled low at the same time, at this time, the second AND gate U2 outputs a low level, the first NMOS tube M1 is not turned on, and the third control signal DIS_xH outputs a high level. Figure 4 As shown, when the first control signal BRK_CTL is at a low level, the comparison circuit is input, the voltage value at the TP1 point in the comparison circuit is less than V1*R17 / (R19+R20+R17), the comparison circuit outputs a low level, the second NMOS tube M2 is not turned on, and the fourth control signal BRK_xL is at a high level. Figure 5 As shown, the fourth control signal BRK_xL outputs the fifth control signal BRK_L as a high level through the isolation chip 501 and the driving unit 502. At this time, the driving chip responds quickly, cuts off the three upper SICs, and turns on the three lower SICs to implement the safety control strategy of the lower SIC. Through the redundant design of BRK and DIS, the double control SIC conduction makes the safety higher.

[0091] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0092] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A motor safety control circuit, characterized in that: include: Logic circuits, motor safety shutdown circuits, and isolation drive circuits; The first output end of the logic circuit is connected to the first input end of the motor safety shutdown circuit, the first input end of the logic circuit inputs a safety state signal, and the second input end of the logic circuit inputs a PWM control signal; the logic circuit is used to output a first control signal after performing AND operation on the PWM control signal, the safety state signal and the power supply signal; The first output end of the motor safety shutdown circuit is connected to the first input end of the driver chip, the second output end of the motor safety shutdown circuit is connected to the input end of the isolation drive circuit, and the output end of the isolation drive circuit is connected to the second input end of the driver chip; The motor safety shutdown circuit is used to output a normal driving signal or an active short-circuit signal according to the first control signal, and the active short-circuit signal is used to control the driving chip to perform an active short circuit.

2. The motor safety control circuit according to claim 1, characterized in that: The logic circuit includes a first resistor, a first filter circuit, a first AND gate, and a second filter circuit; A first end of the first resistor is connected to an input end of the first filter circuit and connected to a PWM control signal, a second end of the first resistor is grounded, and an output end of the first filter circuit is connected to a first input end of the first AND gate; The second input terminal of the first AND gate is connected to a power signal; The input end of the second filter circuit is connected to the safety state signal, and the output end of the second filter circuit is connected to the third input end of the first AND gate; the output end of the first AND gate is connected to the first input end of the motor safety shutdown circuit.

3. The motor safety control circuit according to claim 2, characterized in that: The first filtering circuit includes a second resistor and a first capacitor; The first end of the second resistor is connected to the first end of the first resistor, the second end of the second resistor is connected to the first end of the first capacitor, the second end of the first capacitor is grounded, and the first end of the first capacitor is connected to the first input end of the first AND gate; The second filtering circuit includes a third resistor and a second capacitor; the first end of the third resistor is connected to the safety state signal, the second end of the third resistor is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, and the first end of the second capacitor is connected to the third input end of the first AND gate; The logic circuit further includes a fourth resistor and a third capacitor; The first end of the fourth resistor is connected to the output end of the first AND gate, the output end of the first AND gate outputs a first control signal, the second end of the fourth resistor is connected to the first end of the third capacitor, the second end of the third capacitor is grounded, and the first end of the third capacitor outputs a second control signal.

4. The motor safety control circuit according to claim 1, characterized in that: The motor safety shutdown circuit includes a third filter circuit, a first clamp and filter circuit, a second AND gate and a first drive circuit; The input end of the third filter circuit inputs the first input signal, and the output end of the third filter circuit is connected to the first input end of the second AND gate; The input end of the first clamping and filtering circuit is connected to the first output end of the logic circuit, and the output end of the first clamping and filtering circuit is connected to the second input end of the second AND gate; the first clamping and filtering circuit is used to limit the signal amplitude and filter the signal; The output end of the second AND gate is connected to the input end of the first driving circuit, and the output end of the first driving circuit is connected to the first input end of the driving chip; The motor safety shutdown circuit also includes a second clamping and filtering circuit, a voltage dividing circuit, a comparison circuit and a second driving circuit; The input end of the second clamping and filtering circuit is connected to the first output end of the logic circuit, the output end of the second clamping and filtering circuit is connected to the first input end of the comparison circuit, the output end of the voltage divider circuit is connected to the second input end of the comparison circuit, the output end of the comparison circuit is connected to the input end of the second drive circuit, and the output end of the second drive circuit is connected to the input end of the isolation drive circuit.

5. The motor safety control circuit according to claim 4, characterized in that: The first clamping and filtering circuit includes a fourth capacitor, a fifth resistor, a first diode, a second diode, a sixth resistor, a fifth capacitor and a seventh resistor; the first end of the fourth capacitor is connected to the first output end of the logic circuit, the second end of the fourth capacitor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the cathode of the first diode, the anode of the first diode is grounded, the anode of the second diode is connected to the cathode of the first diode, the cathode of the second diode is connected to the first end of the sixth resistor, the second end of the sixth resistor is grounded, the fifth capacitor is connected in parallel with the sixth resistor, the first end of the seventh resistor is connected to the first end of the fifth capacitor, and the second end of the seventh resistor is connected to the second input end of the second AND gate.

6. The motor safety control circuit according to claim 4, characterized in that: The first driving circuit includes a ninth resistor, a tenth resistor, a seventh capacitor, a first NMOS transistor, an eleventh resistor and an eighth capacitor; The first end of the ninth resistor is connected to the output end of the second AND gate, the second end of the ninth resistor is connected to the first end of the tenth resistor, the second end of the tenth resistor is grounded, the first end of the seventh capacitor and the first end of the tenth resistor are connected to the first electrode of the first NMOS tube, the second end of the seventh capacitor is grounded, the second electrode of the first NMOS tube is grounded, the first end of the eleventh resistor and the first end of the eighth capacitor are connected to the third electrode of the first NMOS tube, the second end of the eleventh resistor is connected to the power supply, the second end of the eighth capacitor is grounded, and the third electrode of the first NMOS tube is connected to the first input end of the driving chip.

7. The motor safety control circuit according to claim 4, characterized in that: The second clamping and filtering circuit includes a ninth capacitor, a twelfth resistor, a third diode, a fourth diode, a thirteenth resistor and a tenth capacitor; The first end of the ninth capacitor is connected to the first output end of the logic circuit, the second end of the ninth capacitor is connected to the first end of the twelfth resistor, the second end of the twelfth resistor is connected to the cathode of the third diode, the anode of the third diode is grounded, the anode of the fourth diode is connected to the cathode of the third diode, the cathode of the fourth diode is connected to the first end of the thirteenth resistor, the second end of the thirteenth resistor is grounded, and the tenth capacitor is connected in parallel with the thirteenth resistor.

8. The motor safety control circuit according to claim 4, characterized in that: The voltage divider circuit includes a fourteenth resistor, a sixteenth resistor, and a seventeenth resistor; The first end of the fourteenth resistor is grounded, the second end of the fourteenth resistor is connected to the first end of the seventeenth resistor, the second end of the seventeenth resistor is connected to the first end of the sixteenth resistor, and the second end of the sixteenth resistor is connected to the power signal.

9. The motor safety control circuit according to claim 8, characterized in that: The comparison circuit includes an eleventh capacitor, a fifteenth resistor, a first comparator, a twelfth capacitor, a second comparator and an eighteenth resistor; The first end of the eleventh capacitor is connected to the second end of the fourteenth resistor, and the second end of the eleventh capacitor is grounded. The first end of the fifteenth resistor is connected to the first end of the eleventh capacitor, and the second end of the fifteenth resistor is connected to the output end of the first comparator. The first input end of the first comparator is connected to the output end of the second clamping and filtering circuit, and the second input end of the first comparator is connected to the first end of the eleventh capacitor. The first end of the twelfth capacitor is connected to the second end of the seventeenth resistor, and the second end of the twelfth capacitor is grounded. The first end of the eighteenth resistor is connected to the first end of the twelfth capacitor, and the second end of the eighteenth resistor is connected to the output end of the second comparator. The first input end of the second comparator is connected to the first end of the twelfth capacitor, and the second input end of the second comparator is connected to the output end of the second clamping and filtering circuit.

10. The motor safety control circuit according to claim 4, characterized in that: The second driving circuit includes a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a fourteenth capacitor, a fifteenth capacitor and a second NMOS transistor; A first end of the nineteenth resistor is connected to the output end of the comparison circuit, a second end of the nineteenth resistor is connected to a power supply signal, a first end of the twentieth resistor is connected to the first end of the nineteenth resistor, a second end of the twentieth resistor is connected to the first end of the fourteenth capacitor, a second end of the fourteenth capacitor is grounded, a first electrode of the second NMOS tube is connected to the first end of the fourteenth capacitor, a second electrode of the second NMOS tube is grounded, a third electrode of the second NMOS tube is connected to the first end of the twenty-first resistor, a second end of the twenty-first resistor is connected to a power supply signal, a first end of the fifteenth capacitor is connected to the first end of the twenty-first resistor, and a second end of the fifteenth capacitor is grounded.

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