Power amplifier circuit

Abstract

The invention provides a power amplifier circuit capable of suppressing deterioration of output characteristics. A power amplifier circuit includes: a first transistor formed on a semiconductor substrate; a second transistor which is formed on the semiconductor substrate, has a base supplied with a first current, which is a part of the control current, and supplies a bias current, which is based on the first current, to the first transistor; a third transistor formed on the semiconductor substrate, a second current being a part of the control current being supplied to a collector of the third transistor, and a third current based on the second current being output from an emitter of the third transistor; a first metal member electrically connected to the emitter of the first transistor and provided so as to overlap a first arrangement region in which the first transistor is arranged in plan view of the semiconductor substrate; and a second metal member electrically connected to the emitter of the third transistor. The third transistor is provided so as to overlap the first metal member in plan view.

Description

Technical Field

[0001] The present disclosure relates to a power amplifier circuit. Background Art

[0002] Patent Document 1 describes a power amplifier circuit capable of alleviating the influence of stress.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-125870

[0006] If a transistor for amplification is biased or amplifies a high-frequency signal, it will generate heat. If the transistor for amplification generates heat, the threshold of the base-emitter voltage will change, the operating point will change, the gain will change, and the linearity will be affected. As a result, the output characteristics of the power amplifier circuit will deteriorate.

[0007] The power amplifier circuit described in Patent Document 1 takes into consideration the situation where the amplification transistor and the biasing transistor are subjected to stress, but does not take into consideration the situation where the amplification transistor generates heat. Summary of the invention

[0008] Problem that the invention aims to solve

[0009] The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress the deterioration of the output characteristics of a power amplifier circuit.

[0010] Technical solutions to solve problems

[0011] A power amplifier circuit according to one aspect of the present disclosure includes: a first transistor formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, a first current as a part of a control current being supplied to a base of the second transistor, and a bias current based on the first current being supplied to the first transistor; a third transistor formed on the semiconductor substrate, a second current as a part of a control current being supplied to a collector of the third transistor, and a third current based on the second current being output from an emitter of the third transistor; a first metal member electrically connected to an emitter of the first transistor and arranged to overlap with a first configuration region where the first transistor is arranged in a plan view of the semiconductor substrate; and a second metal member electrically connected to an emitter of the third transistor. The third transistor is arranged to overlap with the first metal member in a plan view.

[0012] Effects of the Invention

[0013] According to the present disclosure, it is possible to suppress the deterioration of the output characteristics of the power amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing a circuit configuration of a power amplifier circuit according to the first embodiment.

[0015] Figure 2 It is a diagram showing the layout of the power amplifier circuit according to the first embodiment.

[0016] Figure 3 It is a cross-sectional view of the power amplifier circuit according to the first embodiment.

[0017] Figure 4 It is a diagram showing a circuit configuration of a power amplifier circuit according to a second embodiment.

[0018] Figure 5 It is a diagram showing the layout of the power amplifier circuit according to the second embodiment.

[0019] Figure 6 It is a diagram showing a circuit configuration of a power amplifier circuit according to a third embodiment.

[0020] Figure 7 It is a diagram showing the layout of the power amplifier circuit according to the third embodiment.

[0021] Figure 8 It is a diagram showing a circuit configuration of a power amplifier circuit according to a fourth embodiment.

[0022] Fig. 9 It is a diagram showing the layout of the power amplifier circuit according to the fourth embodiment.

[0023] Fig.10 It is a cross-sectional view of a power amplifier circuit according to a fourth embodiment.

[0024] Fig.11 It is a diagram showing the layout of the power amplifier circuit according to the fifth embodiment.

[0025] Description of Reference Numerals

[0026] 1. 1A, 1B, 1C, 1D: power amplifier circuit;

[0027] 11: Input matching circuit;

[0028] 12, 15, 18: Amplifying transistors;

[0029] 12a, 15a: unit transistor;

[0030] 13, 16, 19: bias circuit;

[0031] 14: Inter-stage matching circuit;

[0032] 17: Output matching circuit;

[0033] 21, 22, 23, 24, 31, 32, 33, 34, 41, 42, 43: transistors;

[0034] 71: semiconductor substrate;

[0035] 72: insulation layer;

[0036] BMP11, BMP12, BMP13, BMP14, BMP21: Bump. DETAILED DESCRIPTION

[0037] Hereinafter, the embodiments of the present disclosure will be described in detail based on the accompanying drawings. In addition, the present invention is not limited to the embodiments. Each embodiment is an illustration, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed. After the second embodiment, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects based on the same structure will not be mentioned one by one in each embodiment.

[0038] <First Embodiment>

[0039] (Circuit Structure)

[0040] Figure 1 1 is a diagram showing a circuit configuration of a power amplifier circuit according to Embodiment 1. The power amplifier circuit 1 amplifies a high-frequency signal RFin and outputs a high-frequency signal RFout.

[0041] The power amplifier circuit 1 includes an input matching circuit 11 , an amplifier transistor 12 at a primary stage (driver stage), a bias circuit 13 , an inter-stage matching circuit 14 , an amplifier transistor 15 at a final stage (power stage), a bias circuit 16 , and an output matching circuit 17 .

[0042] The amplifier transistor 12 and the amplifier transistor 15 each correspond to an example of the “first transistor” in the present disclosure.

[0043] Each transistor is a bipolar transistor, but the present disclosure is not limited to this. The transistor may be, for example, a field effect transistor. Regarding the bipolar transistor, a heterojunction bipolar transistor (HBT) may be exemplified, but the present disclosure is not limited to this. The transistor may also be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. The so-called unit transistor refers to the minimum structure that can constitute a transistor.

[0044] When each transistor is a field effect transistor, the source corresponds to the emitter of the bipolar transistor, the gate corresponds to the base of the bipolar transistor, and the drain corresponds to the collector of the bipolar transistor.

[0045] In the embodiment, the amplifier transistor 12 and the amplifier transistor 15 are each a multi-finger transistor, but the present disclosure is not limited thereto. The amplifier transistor 12 and the amplifier transistor 15 may each be a unit transistor.

[0046] In the embodiment, the number of stages of the power amplifier circuit 1 is set to two, but the present disclosure is not limited thereto. The number of stages of the power amplifier circuit 1 may be one, or three or more.

[0047] A high frequency signal RFin is input to one end of the input matching circuit 11. The other end of the input matching circuit 11 is electrically connected to the base of the amplifier transistor 12. The high frequency signal RFin that has passed through the input matching circuit 11 is input to the base of the amplifier transistor 12.

[0048] The bias circuit 13 provides a bias to the amplifier transistor 12. The bias circuit 13 includes transistors 21 to 23.

[0049] The transistor 23 corresponds to an example of the “second transistor” in the present disclosure. The transistor 22 corresponds to an example of the “third transistor” in the present disclosure. The transistor 21 corresponds to an example of the “fifth transistor” in the present disclosure.

[0050] In the embodiment, each of the transistors 21 to 23 is a unit transistor, but the present disclosure is not limited thereto. Each of the transistors 21 to 23 may be a multi-finger transistor.

[0051] The collector and base of transistor 21 are electrically connected to node N11. That is, transistor 21 is diode-connected. The emitter of transistor 21 is electrically connected to the collector and base of transistor 22. That is, transistor 22 is diode-connected. Instead of transistor 21 and transistor 22, a transistor having a feedback circuit between the base and the collector may be used. The emitter of transistor 22 is electrically connected to bump BMP21 (described later). Bump BMP21 is electrically connected to a reference potential. That is, the emitter of transistor 22 is electrically connected to the reference potential via bump BMP21. Regarding the reference potential, a ground potential may be exemplified, but the present disclosure is not limited thereto.

[0052] The base of the transistor 23 is electrically connected to the node N11. The collector of the transistor 23 is electrically connected to the power supply potential Vcc1 and is supplied with power. The emitter of the transistor 23 is electrically connected to one end of the resistor 53. That is, the transistor 23 and the resistor 53 are connected in an emitter follower manner. The other end of the resistor 53 is electrically connected to the base of the amplifier transistor 12.

[0053] A current I11 is input to the node N11 from the current source 51. The current I11 is divided into a current I12 and a current I13. That is, I11=I12+I13.

[0054] The current I11 corresponds to an example of the “control current” of the present disclosure. The current I12 corresponds to an example of the “fifth current” of the present disclosure. The current I13 corresponds to an example of the “first current” of the present disclosure.

[0055] Current I12 is input to the collector and base of transistor 21. Transistor 21 outputs current I14 from the emitter to the collector and base of transistor 22. That is, I12=I14. Transistor 22 outputs current I15 from the emitter to bump BMP21. That is, I14=I15. Transistor 21 and transistor 22 generate voltage at node N11.

[0056] The current I14 corresponds to an example of the “second current” in the present disclosure. The current I15 corresponds to an example of the “third current” in the present disclosure.

[0057] The transistor 23 outputs a current I16 corresponding to the current I13 to the base of the amplifier transistor 12 via the resistor 53. The base of the amplifier transistor 12 is biased by the current I16. That is, the current I16 is a base bias current of the amplifier transistor 12.

[0058] The emitter of the amplifier transistor 12 is electrically connected to a bump BMP11 (described later). The bump BMP11 is electrically connected to a reference potential. That is, the emitter of the amplifier transistor 12 is electrically connected to the reference potential via the bump BMP11. The collector of the amplifier transistor 12 is electrically connected to the power supply potential Vcc2 via the choke coil 55 and is supplied with power. In addition, the collector of the amplifier transistor 12 is electrically connected to one end of the inter-stage matching circuit 14. The amplifier transistor 12 amplifies the high-frequency signal RFin input to the base, and outputs the amplified high-frequency signal RF1 from the collector to one end of the inter-stage matching circuit 14.

[0059] The other end of the inter-stage matching circuit 14 is electrically connected to the base of the amplifier transistor 15. The high-frequency signal RF1 having passed through the inter-stage matching circuit 14 is input to the base of the amplifier transistor 15.

[0060] The bias circuit 16 provides a bias to the amplifier transistor 15. The bias circuit 16 includes transistors 31 to 33.

[0061] The transistor 33 corresponds to an example of the “second transistor” in the present disclosure. The transistor 32 corresponds to an example of the “third transistor” in the present disclosure. The transistor 31 corresponds to an example of the “fifth transistor” in the present disclosure.

[0062] In the embodiment, each of the transistors 31 to 33 is a unit transistor, but the present disclosure is not limited thereto. Each of the transistors 31 to 33 may be a multi-finger transistor.

[0063] The collector and base of transistor 31 are electrically connected to node N21. That is, transistor 31 is diode-connected. The emitter of transistor 31 is electrically connected to the collector and base of transistor 32. That is, transistor 32 is diode-connected. Instead of transistor 31 and transistor 32, a transistor having a feedback circuit between the base and the collector may be used. The emitter of transistor 32 is electrically connected to bump BMP21 (described later). Bump BMP21 is electrically connected to a reference potential. That is, the emitter of transistor 32 is electrically connected to the reference potential via bump BMP21.

[0064] The base of the transistor 33 is electrically connected to the node N21. The collector of the transistor 33 is electrically connected to the power supply potential Vcc3 and is supplied with power. The emitter of the transistor 33 is electrically connected to one end of the resistor 54. That is, the transistor 33 and the resistor 54 are connected in an emitter follower manner. The other end of the resistor 54 is electrically connected to the base of the amplifier transistor 15.

[0065] A current I21 is input to the node N21 from the current source 52. The current I21 is divided into a current I22 and a current I23. That is, I21=I22+I23.

[0066] The current I21 corresponds to an example of the “control current” of the present disclosure. The current I22 corresponds to an example of the “fifth current” of the present disclosure. The current I23 corresponds to an example of the “first current” of the present disclosure.

[0067] Current I22 is input to the collector and base of transistor 31. Transistor 31 outputs current I24 from the emitter to the collector and base of transistor 32. That is, I22=I24. Transistor 32 outputs current I25 from the emitter to bump BMP21. That is, I24=I25. Transistor 31 and transistor 32 generate voltage at node N21.

[0068] The current I24 corresponds to an example of the “second current” in the present disclosure. The current I25 corresponds to an example of the “third current” in the present disclosure.

[0069] The transistor 33 outputs a current I26 corresponding to the current I23 to the base of the amplifier transistor 15 via the resistor 54. The base of the amplifier transistor 15 is biased by the current I26. That is, the current I26 is a base bias current of the amplifier transistor 15.

[0070] The emitter of the amplifier transistor 15 is electrically connected to a bump BMP12 (described later). The bump BMP12 is electrically connected to a reference potential. That is, the emitter of the amplifier transistor 15 is electrically connected to the reference potential via the bump BMP12. The collector of the amplifier transistor 15 is electrically connected to the power supply potential Vcc4 via the choke coil 56 and is supplied with power. In addition, the collector of the amplifier transistor 15 is electrically connected to one end of the output matching circuit 17. The amplifier transistor 15 amplifies the high-frequency signal RF1 input to the base, and outputs the amplified high-frequency signal RFout from the collector to one end of the output matching circuit 17. The high-frequency signal RFout is output from the other end of the output matching circuit 17.

[0071] (layout)

[0072] Figure 2 1 is a diagram showing the layout of the power amplifier circuit according to the first embodiment. The power amplifier circuit 1 is formed on a semiconductor substrate 71 . Figure 2 This is a top view of the semiconductor substrate 71 viewed from a direction perpendicular to the main surface. Figure 2 In FIG. 1 , description of the region where the output matching circuit 17 is formed is omitted.

[0073] A bias circuit region 81 is provided along the left side (the side on the base end side of the X-axis and along the Y-axis) of the semiconductor substrate 71 in the figure. The long dimension direction of the bias circuit region 81 is the Y-axis direction, and the short dimension direction is the X-axis direction. The bias circuit region 81 is a region where the transistors 21 and 23 in the bias circuit 13 and the transistors 31 and 33 in the bias circuit 16 are formed.

[0074] In an upper layer (layer closer to the outside of the paper) substantially at the center of the bias circuit region 81 , a bump BMP 21 is formed via an insulating layer (described later).

[0075] The bump BMP21 corresponds to an example of the “second metal member” in the present disclosure.

[0076] The bump BMP 21 may be made of copper (Cu). In addition to copper, the bump BMP 21 may be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0077] An under bump metal (UBM) may be formed between the insulating layer and the bump BMP 21. The under bump metal is formed of a material including at least one of Ti, Cr, Cu, Au, Ni, and Pd, for example.

[0078] An input matching circuit region 82 is provided on the right side (X-axis direction side) of the upper portion (the base end side of the Y-axis) of the bias circuit region 81 in the figure. The input matching circuit region 82 has a long dimension in the X-axis direction and a short dimension in the Y-axis direction. The input matching circuit region 82 is a region where the input matching circuit 11 is formed.

[0079] A region 83 is provided on the right side (X-axis direction side) of the center portion (the center portion in the Y-axis direction) of the bias circuit region 81 in the figure and on the lower side (Y-axis direction side) of the input matching circuit region 82 in the figure. The long dimension direction of the region 83 is the X-axis direction, and the short dimension direction is the Y-axis direction. The transistor 22 and a plurality of unit transistors 12a are formed in the region 83. The plurality of unit transistors 12a constitute the amplifier transistor 12.

[0080] The area 83 corresponds to an example of the “first arrangement area” in the present disclosure.

[0081] A transistor 22 is formed along the left side of the region 83 in the figure (the side on the base end side of the X-axis). In addition, a plurality of unit transistors 12a are formed on the right side of the transistor 22 in the figure (the side in the X-axis direction). The long dimension direction of the transistor 22 and the plurality of unit transistors 12a are respectively in the Y-axis direction and the short dimension direction is in the X-axis direction. The transistor 22 and the plurality of unit transistors 12a are arranged in the long dimension direction (X-axis direction) of the region 83.

[0082] The emitter of the transistor 22 is electrically connected to the bump BMP21 via a wiring 91 formed on the semiconductor substrate 71 .

[0083] In the upper layer (the layer on the outer side of the paper) of the region 83, a bump BMP11 is formed via an insulating layer (described later). The bump BMP11 overlaps with the region 83 (the transistor 22 and the plurality of unit transistors 12a) in a plan view. Here, the so-called plan view refers to observing the semiconductor substrate 71 from a direction perpendicular to the main surface of the semiconductor substrate 71 (a direction opposite to the Z-axis direction).

[0084] The bump BMP11 corresponds to an example of the “first metal member” in the present disclosure.

[0085] The bump BMP11 may be made of copper (Cu). In addition to copper, the bump BMP11 may be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0086] An under bump metallurgy may be formed between the insulating layer and the bump BMP11 .

[0087] The emitters of the plurality of unit transistors 12 a are electrically connected to the bumps BMP11 through vias (described later).

[0088] An inter-stage matching circuit region 84 is provided on the right side (X-axis direction side) of the lower portion (Y-axis direction side) of the bias circuit region 81 in the figure and on the lower side (Y-axis direction side) of the region 83 in the figure. The long dimension direction of the inter-stage matching circuit region 84 is the X-axis direction, and the short dimension direction is the Y-axis direction. The inter-stage matching circuit 14 is formed in the inter-stage matching circuit region 84.

[0089] A region 85 is provided on the lower side (Y-axis direction side) of the bias circuit region 81 and the inter-stage matching circuit region 84 in the figure. The long dimension direction of the region 85 is the X-axis direction, and the short dimension direction is the Y-axis direction. The transistor 32 and a plurality of unit transistors 15a are formed in the region 85. The plurality of unit transistors 15a constitute the amplifier transistor 15.

[0090] The region 85 corresponds to an example of the “first arrangement region” in the present disclosure.

[0091] A transistor 32 is formed along the left side of the region 85 in the figure (the side on the base end side of the X-axis). In addition, a plurality of unit transistors 15a are formed on the right side of the transistor 32 in the figure (the side in the X-axis direction). The long dimension direction of the transistor 32 and the plurality of unit transistors 15a are respectively in the Y-axis direction and the short dimension direction is in the X-axis direction. The transistor 32 and the plurality of unit transistors 15a are arranged in the long dimension direction (X-axis direction) of the region 85.

[0092] The emitter of the transistor 32 is electrically connected to the bump BMP21 via a wiring 92 formed on the semiconductor substrate 71 .

[0093] In the upper layer (the layer on the outer side of the paper) of the region 85, a bump BMP12 is formed via an insulating layer (described later). The bump BMP12 overlaps with the region 85 (the transistor 32 and the plurality of unit transistors 15a) in a plan view. Here, the so-called plan view refers to observing the semiconductor substrate 71 from a direction perpendicular to the main surface of the semiconductor substrate 71 (a direction opposite to the Z-axis direction).

[0094] The bump BMP12 corresponds to an example of the “first metal member” in the present disclosure.

[0095] The bump BMP 12 may be made of copper (Cu). Alternatively, the bump BMP 12 may be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0096] An under bump metallurgy may be formed between the insulating layer and the bump BMP12 .

[0097] The emitters of the plurality of unit transistors 15 a are electrically connected to the bumps BMP12 via vias (described later).

[0098] Figure 3It is a cross-sectional view of the power amplifier circuit according to the first embodiment. Figure 3 yes Figure 2 Sectional view at line AB in .

[0099] exist Figure 3 , the cross-section of the transistor 32, the plurality of unit transistors 15a, and the bump BMP12 is shown, but the cross-section of the transistor 22, the plurality of unit transistors 12a, and the bump BMP11 is the same, and thus illustration and description thereof are omitted.

[0100] A transistor 32 and a plurality of unit transistors 15a are formed on a semiconductor substrate 71. An insulating layer 72 is formed on the upper layer (layer in the Z-axis direction) of the transistor 32 and the plurality of unit transistors 15a. A bump BMP12 is formed on the upper layer (layer in the Z-axis direction) of the insulating layer 72. The emitters of the plurality of unit transistors 15a are electrically connected to the bump BMP12 via a plurality of vias 101a.

[0101] An under bump metal may be formed between the insulating layer 72 and the bump BMP12. In this case, the plurality of vias 101a are electrically connected to the under bump metal.

[0102] In addition, the emitter of the transistor 32 is connected via the wiring 92 (see Figure 2 ) and bump BMP21 (refer to Figure 2 ) is electrically connected, and therefore is not electrically connected to the bump BMP12.

[0103] (Effect)

[0104] When the amplifier transistor 15 (a plurality of unit transistors 15a) is biased or amplifies a high frequency signal, it generates heat. When the amplifier transistor 15 generates heat, the threshold of the base-emitter voltage decreases, the operating point changes, the quiescent current changes, the gain changes, and the linearity deteriorates.

[0105] Reference Figure 3 The heat generated from the plurality of unit transistors 15a is transferred to the transistor 32 via the semiconductor substrate 71 and the insulating layer 72. That is, the plurality of unit transistors 15a and the transistor 32 are thermally coupled. When the temperature of the transistor 32 rises due to the heat transfer, the threshold of the base-emitter voltage decreases.

[0106] Reference Figure 1. If the threshold value of the base-emitter voltage of the transistor 32 decreases, the current I25 increases, the current I24 increases, and the current I22 increases. Therefore, the current I23 decreases. If the current I23 decreases, the transistor 33 decreases the current I26. That is, the base bias current (current I26) supplied to the amplifier transistor 15 decreases. Therefore, in the amplifier transistor 15, the change in the threshold value of the base-emitter voltage caused by the temperature rise is compensated by the reduction of the base bias current (current I26).

[0107] Thus, even if the amplifying transistor 15 generates heat, the power amplifier circuit 1 can suppress the deterioration of the output characteristics.

[0108] In the above description, the amplifier transistor 15 and the bias circuit 16 are described, but the amplifier transistor 12 and the bias circuit 13 also operate in the same manner. Therefore, even if the amplifier transistor 12 generates heat, the power amplifier circuit 1 can suppress the deterioration of the output characteristics.

[0109] In the first embodiment, the technology of the present disclosure is applied to two stages of the multi-stage amplifier circuit (amplifier transistor 12 and bias circuit 13, and amplifier transistor 15 and bias circuit 16), but the present disclosure is not limited to this. The technology of the present disclosure may also be applied to at least one stage of the multi-stage amplifier circuit.

[0110] <Second Embodiment>

[0111] (Circuit Structure)

[0112] Figure 4 It is a diagram showing a circuit configuration of a power amplifier circuit according to a second embodiment.

[0113] The power amplifier circuit 1A and the power amplifier circuit 1 (refer to Figure 1 ) includes a bias circuit 13A instead of the bias circuit 13. In addition, the power amplifier circuit 1A includes a bias circuit 16A instead of the bias circuit 16.

[0114] Compared with the bias circuit 13 , the bias circuit 13A further includes a transistor 24 .

[0115] The transistor 24 corresponds to an example of the “fourth transistor” in the present disclosure.

[0116] In the embodiment, the transistor 24 is a unit transistor, but the present disclosure is not limited thereto. The transistor 24 may also be a multi-finger transistor.

[0117] The collector and base of the transistor 24 are electrically connected to a node N12 between the emitter of the transistor 21 and the collector of the transistor 22. That is, the transistor 24 is diode-connected. The emitter of the transistor 24 is electrically connected to the bump BMP21.

[0118] That is, the transistor 22 and the transistor 24 are connected in parallel.

[0119] The size of transistor 22 and the size of transistor 24 may be different or the same.

[0120] The transistor 21 outputs a current I14 to the node N12. The current I14 is divided into a current I17 and a current I18. That is, I14=I17+I18.

[0121] The current I14 corresponds to an example of the “second current” in the present disclosure.

[0122] The current I17 is input to the collector and base of the transistor 22. The transistor 22 outputs a current I19 from the emitter to the bump BMP21. That is, I17=I19.

[0123] The current I18 is input to the collector and base of the transistor 24. The transistor 24 outputs a current I20 from the emitter to the bump BMP21. That is, I18=I20.

[0124] The current I20 corresponds to an example of the “fourth current” in the present disclosure.

[0125] Compared with the bias circuit 16 , the bias circuit 16A further includes a transistor 34 .

[0126] The transistor 34 corresponds to an example of the “fourth transistor” in the present disclosure.

[0127] In the embodiment, the transistor 34 is a unit transistor, but the present disclosure is not limited thereto. The transistor 34 may also be a multi-finger transistor.

[0128] The collector and base of the transistor 34 are electrically connected to a node N22 between the emitter of the transistor 31 and the collector of the transistor 32. That is, the transistor 34 is diode-connected. The emitter of the transistor 34 is electrically connected to the bump BMP21.

[0129] That is, the transistor 32 and the transistor 34 are connected in parallel.

[0130] The size of transistor 32 and the size of transistor 34 may be different or the same.

[0131] The transistor 31 outputs a current I24 to the node N22. The current I24 is divided into a current I27 and a current I28. That is, I24=I27+I28.

[0132] The current I24 corresponds to an example of the “second current” in the present disclosure.

[0133] The current I27 is input to the collector and base of the transistor 32. The transistor 32 outputs a current I29 from the emitter to the bump BMP21. That is, I27=I29.

[0134] The current I28 is input to the collector and base of the transistor 34. The transistor 34 outputs the current I30 from the emitter to the bump BMP21. That is, I28=I30.

[0135] The current I30 corresponds to an example of the “fourth current” in the present disclosure.

[0136] (layout)

[0137] Figure 5 1A is a diagram showing the layout of a power amplifier circuit according to the second embodiment. The power amplifier circuit 1A is formed on a semiconductor substrate 71 . Figure 5 This is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface.

[0138] The power amplifier circuit 1A and the power amplifier circuit 1 (refer to Figure 2 ) In comparison, the transistor 24 is formed in the upper portion of the bias circuit region 81 in the figure (the portion on the base end side of the Y axis). The emitter of the transistor 24 is electrically connected to the bump BMP21 via a wiring 93 formed on the semiconductor substrate 71.

[0139] The transistor 34 is formed in the lower portion of the bias circuit region 81 in the figure (the portion on the Y-axis direction side). The emitter of the transistor 34 is electrically connected to the bump BMP21 via a wiring 94 formed in the semiconductor substrate 71 .

[0140] The transistor 24 and the transistor 34 may overlap the bump BMP 21 in a plan view. Here, the plan view refers to observing the semiconductor substrate 71 from a direction perpendicular to the main surface of the semiconductor substrate 71 (a direction opposite to the Z-axis direction).

[0141] (Effect)

[0142] Since the transistor 32 is thermally coupled to the plurality of unit transistors 15a, the bias circuit 16 of the first embodiment may be too sensitive to the heat generated by the plurality of unit transistors 15a. In other words, the power amplifier circuit 1 may be too sensitive to the heat generated by the amplifier transistor 15.

[0143] On the other hand, in the bias circuit 16A of the second embodiment, in addition to the transistor 32 that is thermally coupled to the plurality of unit transistors 15a, a transistor 34 that is not thermally coupled to the plurality of unit transistors 15a is included. The transistor 32 and the transistor 34 are connected in parallel. The transistor 34 does not bear the heat generated by the plurality of unit transistors 15a, so the emitter current (current I30) of the transistor 34 is not affected by the heat generated by the plurality of unit transistors 15a. Therefore, compared with the first embodiment, the variation of the base bias current (current I26) of the amplifier transistor 15 can be suppressed.

[0144] Thus, the bias circuit 16A can suppress the response to the heat generated by the amplifier transistor 15 from becoming too sensitive. That is, the power amplifier circuit 1A can suppress the response to the heat generated by the amplifier transistor 15 from becoming too sensitive.

[0145] Furthermore, if the transistors 24 and 34 overlap with the bump BMP21 in a plan view, stress is also applied to the transistors 24 and 34 , and the influence of the stress on the amplifier transistor 15 is reduced, thereby suppressing the deterioration of the output characteristics.

[0146] Furthermore, the bias circuit 16A can adjust the response to the heat generated by the amplifier transistor 15 by adjusting the size of the transistor 32 and the size of the transistor 34. In the present disclosure, the size of the transistor 32 and the transistor 34 refers to the emitter area.

[0147] In the above description, the bias circuit 16A is described, but the bias circuit 13A also operates in the same manner. Thus, the power amplifier circuit 1A can suppress the response to the heat generated by the amplifier transistor 12 from becoming too sensitive.

[0148] In addition, the bias circuit 13A can adjust the response to the heat generated by the amplifier transistor 12 by adjusting the size of the transistor 22 and the size of the transistor 24. In the present disclosure, the size of the transistor 22 and the transistor 24 refers to the emitter area.

[0149] In the second embodiment, the technology of the present disclosure is applied to two stages of the multi-stage amplifier circuit (amplifier transistor 12 and bias circuit 13A and amplifier transistor 15 and bias circuit 16A), but the present disclosure is not limited to this. The technology of the present disclosure may also be applied to at least one stage of the multi-stage amplifier circuit.

[0150] <Third Embodiment>

[0151] (Circuit Structure)

[0152] Figure 6It is a diagram showing a circuit configuration of a power amplifier circuit according to a third embodiment.

[0153] The power amplifier circuit 1B is similar to the power amplifier circuit 1 (refer to Figure 1 ) also includes an amplifier transistor 18 and a bias circuit 19.

[0154] In the embodiment, the amplifier transistor 18 is a multi-finger transistor, but the present disclosure is not limited thereto. The amplifier transistor 18 may also be a unit transistor.

[0155] The amplifier transistor 15 and the amplifier transistor 18 are connected in parallel. That is, the final stage (power stage) of the power amplifier circuit 1B includes the amplifier transistor 15 and the amplifier transistor 18 connected in parallel.

[0156] The bias circuit 19 provides a bias to the amplifier transistor 18. The bias circuit 19 includes transistors 41 to 43.

[0157] In the embodiment, each of the transistors 41 to 43 is a unit transistor, but the present disclosure is not limited thereto. Each of the transistors 41 to 43 may be a multi-finger transistor.

[0158] The collector and base of transistor 41 are electrically connected to node N31. That is, transistor 41 is diode-connected. The emitter of transistor 41 is electrically connected to the collector and base of transistor 42. That is, transistor 42 is diode-connected. The emitter of transistor 42 is electrically connected to bump BMP21. That is, the emitter of transistor 42 is electrically connected to the reference potential via bump BMP21.

[0159] The base of the transistor 43 is electrically connected to the node N31. The collector of the transistor 43 is electrically connected to the power supply potential Vcc5 and is supplied with power. The emitter of the transistor 43 is electrically connected to one end of the resistor 59. That is, the transistor 43 and the resistor 59 are connected in an emitter follower manner. The other end of the resistor 59 is electrically connected to the base of the amplifier transistor 18.

[0160] A current I31 is input to the node N31 from the current source 52. The current I31 is divided into a current I32 and a current I33. That is, I31=I32+I33.

[0161] Current I32 is input to the collector and base of transistor 41. Transistor 41 outputs current I34 from the emitter to the collector and base of transistor 42. That is, I32=I34. Transistor 42 outputs current I35 from the emitter to bump BMP21. That is, I34=I35. Transistors 41 and 42 generate voltage at node N31.

[0162] The transistor 43 outputs a current I36 corresponding to the current I33 to the base of the amplifier transistor 18 via the resistor 59. The base of the amplifier transistor 18 is biased by the current I36. That is, the current I36 is a base bias current of the amplifier transistor 18.

[0163] The emitter of the amplifier transistor 18 is electrically connected to a bump BMP13 (described later). The bump BMP13 is electrically connected to a reference potential. That is, the emitter of the amplifier transistor 18 is electrically connected to the reference potential via the bump BMP13. The collector of the amplifier transistor 18 is electrically connected to the power supply potential Vcc6 via the choke coil 60 and is supplied with power.

[0164] A DC blocking capacitor 57 is added between the other end of the inter-stage matching circuit 14 and the base of the amplifier transistor 15. A DC blocking capacitor 58 is added between the other end of the inter-stage matching circuit 14 and the base of the amplifier transistor 18.

[0165] The collector of the amplifier transistor 15 is electrically connected to the node N1. The amplifier transistor 15 amplifies the high-frequency signal RF1 input to the base, and outputs the amplified high-frequency signal RF2 from the collector to the node N1.

[0166] The collector of the amplifier transistor 18 is electrically connected to the node N1. The amplifier transistor 18 amplifies the high-frequency signal RF1 input to the base, and outputs the amplified high-frequency signal RF3 from the collector to the node N1.

[0167] The high-frequency signal RF2 and the high-frequency signal RF3 are superimposed at the node N1 to become the high-frequency signal RFout.

[0168] One end of the output matching circuit 17 is electrically connected to the node N1 , and the other end of the output matching circuit 17 outputs a high-frequency signal RFout.

[0169] (layout)

[0170] Figure 7 1B is a diagram showing the layout of a power amplifier circuit according to the third embodiment. The power amplifier circuit 1B is formed on a semiconductor substrate 71 . Figure 7 This is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface.

[0171] A region 85 is provided on the lower side (Y-axis direction side) of the bias circuit region 81 and the inter-stage matching circuit region 84 in the figure. The long dimension direction of the region 85 is the X-axis direction, and the short dimension direction is the Y-axis direction. The transistor 32 and a plurality of unit transistors 15a are formed in the region 85. The plurality of unit transistors 15a constitute the amplifier transistor 15.

[0172] A transistor 32 is formed along the right side (the side on the X-axis direction) of the region 85 in the figure. In addition, a plurality of unit transistors 15a are formed on the left side (the base end side of the X-axis) of the transistor 32 in the figure. The long dimension direction of the transistor 32 and the plurality of unit transistors 15a are respectively in the Y-axis direction and the short dimension direction is in the X-axis direction. The transistor 32 and the plurality of unit transistors 15a are arranged in the long dimension direction (X-axis direction) of the region 85.

[0173] The emitter of the transistor 32 is electrically connected to the bump BMP21 via a wiring 92 formed on the semiconductor substrate 71 .

[0174] The wiring 92 corresponds to an example of the “first wiring” in the present disclosure.

[0175] The bases of the plurality of unit transistors 15 a are electrically connected to the inter-stage matching circuit 14 in the inter-stage matching circuit region 84 via a wiring 95 formed in a layer different from the wiring 92 of the semiconductor substrate 71 .

[0176] The wiring 95 corresponds to an example of the “second wiring” in the present disclosure.

[0177] The wiring 92 and the wiring 95 intersect in the region 151. In the region 151, there is a possibility that parasitic capacitance is generated between the wiring 92 and the wiring 95.

[0178] A region 86 is provided on the right side (X-axis direction side) of the region 85 in the figure and on the lower side (Y-axis direction side) of the inter-stage matching circuit region 84 in the figure. The long dimension direction of the region 86 is the X-axis direction, and the short dimension direction is the Y-axis direction. The transistor 42 and a plurality of unit transistors 18a are formed in the region 86. The plurality of unit transistors 18a constitute the amplifying transistor 18.

[0179] A transistor 42 is formed along the left side of the region 86 in the figure (the side on the base end side of the X-axis). In addition, a plurality of unit transistors 18a are formed on the right side of the transistor 42 in the figure (the side in the X-axis direction). The long dimension direction of the transistor 42 and the plurality of unit transistors 18a are respectively in the Y-axis direction and the short dimension direction is in the X-axis direction. The transistor 42 and the plurality of unit transistors 18a are arranged in the long dimension direction (X-axis direction) of the region 86.

[0180] The emitter of the transistor 42 is electrically connected to the bump BMP21 via the wiring 92 .

[0181] The bases of the plurality of unit transistors 18 a are electrically connected to the inter-stage matching circuit 14 in the inter-stage matching circuit region 84 via a wiring 96 formed in the semiconductor substrate 71 .

[0182] In the upper layer (the layer on the outer side of the paper) of the region 86, a bump BMP13 is formed via an insulating layer. The bump BMP13 overlaps with the region 86 (the transistor 42 and the plurality of unit transistors 18a) in a plan view. Here, the so-called plan view refers to observing the semiconductor substrate 71 from a direction perpendicular to the main surface of the semiconductor substrate 71 (a direction opposite to the Z-axis direction).

[0183] The bump BMP13 may be made of copper (Cu). In addition to copper, the bump BMP13 may be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0184] An under bump metallurgy may be formed between the insulating layer and the bump BMP13 .

[0185] (Effect)

[0186] The wiring 92 electrically connecting the transistor 32 and the bump BMP21 may need to intersect with other wirings. Even in this case, the wiring 92 can intersect with the wiring 95 electrically connected to the bases of the plurality of unit transistors 15a, thereby achieving intersection with a smaller parasitic capacitance.

[0187] Thus, the power amplifier circuit 1B can suppress the deterioration of the output characteristics.

[0188] In addition, the third embodiment and the second embodiment may be combined. That is, the bias circuit 13 may further include a transistor 24 connected in parallel with the transistor 22. The bias circuit 16 may further include a transistor 34 connected in parallel with the transistor 32. Similarly, the bias circuit 19 may further include a transistor connected in parallel with the transistor 42.

[0189] In the third embodiment, the technology of the present disclosure is applied to two stages of the multi-stage amplifier circuit (amplifier transistor 12 and bias circuit 13, amplifier transistors 15 and 18, and bias circuits 16 and 19), but the present disclosure is not limited to this. The technology of the present disclosure may also be applied to at least one stage of the multi-stage amplifier circuit.

[0190] <Fourth Implementation Method>

[0191] (Circuit Structure)

[0192] Figure 8 It is a diagram showing a circuit configuration of a power amplifier circuit according to a fourth embodiment.

[0193] The power amplifier circuit 1C is similar to the power amplifier circuit 1A (refer to Figure 4 ) includes a bias circuit 13C instead of the bias circuit 13A. In addition, the power amplifier circuit 1C includes a bias circuit 16C instead of the bias circuit 16A.

[0194] In the bias circuit 13C, the emitter of the transistor 22 is electrically connected to the bump BMP11 .

[0195] In the bias circuit 16C, the emitter of the transistor 32 is electrically connected to the bump BMP12 .

[0196] (layout)

[0197] Fig. 9 1C is a diagram showing a layout of a power amplifier circuit according to a fourth embodiment. The power amplifier circuit 1C is formed on a semiconductor substrate 71 . Fig. 9 This is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface.

[0198] The power amplifier circuit 1C is similar to the power amplifier circuit 1A (refer to Figure 5 ), the wiring 91 and the wiring 92 are not formed. Moreover, the emitter of the transistor 22 is electrically connected to the bump BMP11. Moreover, the emitter of the transistor 32 is electrically connected to the bump BMP12.

[0199] Fig.10 It is a cross-sectional view of a power amplifier circuit according to a fourth embodiment. Fig.10 yes Fig. 9 Cross-sectional view at line CD in .

[0200] exist Fig.10 , the cross-section of the transistor 32, the plurality of unit transistors 15a, and the bump BMP12 is shown, but the cross-section of the transistor 22, the plurality of unit transistors 12a, and the bump BMP11 is the same, and thus illustration and description thereof are omitted.

[0201] The emitter of the transistor 32 is electrically connected to the bump BMP12 through the via 102 .

[0202] (Effect)

[0203] Reference Fig.10 . The heat generated from the plurality of unit transistors 15a is transferred to the transistor 32 via the semiconductor substrate 71, the insulating layer 72, the bump BMP12, and the via 102. That is, the plurality of unit transistors 15a and the transistor 32 are thermally coupled. If the temperature of the transistor 32 rises due to the heat transferred, the threshold of the base-emitter voltage rises. Therefore, in the amplifier transistor 15, the change in the threshold of the base-emitter voltage caused by the temperature rise is compensated by the increase in the base bias current (current I26).

[0204] Thus, even if the amplifying transistor 15 generates heat, the power amplifier circuit 1C can suppress deterioration in output characteristics.

[0205] In the bias circuit 16C, in addition to the transistor 32 that is thermally coupled to the plurality of unit transistors 15a, a transistor 34 that is not thermally coupled to the plurality of unit transistors 15a is also included. The transistor 32 and the transistor 34 are connected in parallel. The transistor 34 does not bear the heat generated by the plurality of unit transistors 15a, so the emitter current (current I30) of the transistor 34 is not affected by the heat. Therefore, compared with the first embodiment, the variation of the base bias current (current I26) of the amplifier transistor 15 can be suppressed.

[0206] Thus, the bias circuit 16C can suppress the response to the heat generated by the amplifier transistor 15 from becoming too sensitive. That is, the power amplifier circuit 1C can suppress the response to the heat generated by the amplifier transistor 15 from becoming too sensitive.

[0207] Furthermore, the bias circuit 16C can adjust the response to the heat generated by the amplifier transistor 15 by adjusting the size of the transistor 32 and the size of the transistor 34 .

[0208] In the above description, the bias circuit 16C is described, but the bias circuit 13C also operates in the same manner. Thus, even if the amplifying transistor 12 generates heat, the power amplifier circuit 1C can suppress the deterioration of the output characteristics.

[0209] Furthermore, the bias circuit 13C can adjust the response to heat generated by the amplifier transistor 12 by adjusting the size of the transistor 22 and the size of the transistor 24 .

[0210] Furthermore, when the amplifier transistor 15 (a plurality of unit transistors 15 a ) receives stress from the bump BMP12 through the via 101 a , the threshold of the base-emitter voltage rises, the operating point varies, the quiescent current varies, the gain varies, and the linearity deteriorates.

[0211] Reference Fig.10 The transistor 32 is electrically connected to the bump BMP12 through the via 102. Thus, the transistor 32 receives stress from the bump BMP12 through the via 102, which is equivalent to the stress received by the plurality of unit transistors 15a from the bump BMP12 through the via 101a.

[0212] If the base-emitter threshold voltages of the plurality of unit transistors 15a vary due to stress, the base-emitter threshold voltage of the transistor 32 also varies due to stress. Thus, in the amplifier transistor 15, the variation of the threshold of the base-emitter voltage due to stress is compensated by the increase of the base bias current (current I26). Therefore, the variation of the quiescent current of the amplifier transistor 15 can be suppressed, the variation of the gain can be suppressed, and the linearity degradation can be suppressed.

[0213] Thus, even if the amplifying transistor 15 is stressed, the power amplifier circuit 1C can suppress the deterioration of the output characteristics.

[0214] Furthermore, the bias circuit 16C can adjust the response to the stress applied to the amplifier transistor 15 by adjusting the size of the transistor 32 and the size of the transistor 34 .

[0215] In the above description, the transistor 32 and the amplifier transistor 15 are described, but the transistor 22 and the amplifier transistor 12 also operate in the same manner. Therefore, even if the amplifier transistor 12 receives stress from the bump BMP11, the power amplifier circuit 1C can suppress deterioration of output characteristics.

[0216] Furthermore, the bias circuit 13C can adjust the response to the stress applied to the amplifier transistor 12 by adjusting the size of the transistor 22 and the size of the transistor 24 .

[0217] <Fifth Implementation Method>

[0218] (Circuit Structure)

[0219] The circuit configuration of the fifth embodiment is similar to that of the first embodiment (see Figure 1 ) are the same, so the illustration and description are omitted.

[0220] (layout)

[0221] Fig.11 1D is a diagram showing a layout of a power amplifier circuit according to a fifth embodiment. The power amplifier circuit 1D is formed on a semiconductor substrate 71 . Fig.11 This is a plan view of the semiconductor substrate 71 as viewed from a direction perpendicular to the main surface.

[0222] The power amplifier circuit 1D and the power amplifier circuit 1 (refer to Figure 2 ) compared to the embodiment shown in FIG. 1 , when viewed from a direction perpendicular to the main surface of the semiconductor substrate 71, the transistor 32 and the bump BMP12 do not overlap.

[0223] The transistor 31 is formed in the bias circuit region 81. A bump BMP14 is formed via an insulating layer in the upper layer (the layer on the outer side of the paper) of the transistor 31. The bump BMP14 overlaps the transistor 31 when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71.

[0224] (Effect)

[0225] In the power amplifier circuit 1 of the first embodiment, when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71, the transistor 32 overlaps with the bump BMP12, so the response to the heat generated by the plurality of unit transistors 15a may become too sensitive. In other words, the power amplifier circuit 1 may become too sensitive to the heat generated by the amplifier transistor 15.

[0226] On the other hand, in the power amplifier circuit 1D of the fifth embodiment, the transistor 32 does not overlap the bump BMP12 when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71. Therefore, the power amplifier circuit 1D can reduce the thermal coupling between the transistor 32 and the amplification transistor 15 compared to the power amplifier circuit 1.

[0227] Thus, the power amplifier circuit 1D can suppress the response to heat generated by the amplifier transistor 15 from becoming too sensitive.

[0228] Furthermore, in the power amplifier circuit 1D, when the semiconductor substrate 71 is viewed from a direction perpendicular to the main surface of the semiconductor substrate 71 , the transistor 31 overlaps with the bump BMP14 .

[0229] Thus, in the power amplifier circuit 1D, when stress is applied to the semiconductor substrate 71 , stress is also applied to the transistor 31 , and the influence of the stress on the amplifier transistor 15 is reduced, thereby suppressing the deterioration of the output characteristics.

[0230] In the above, the final stage (transistor 31 and transistor 32) of the multi-stage amplifier circuit is described, but the initial stage (transistor 21 and transistor 22) of the multi-stage amplifier circuit may also be set to be the same as the final stage. That is, it is also possible to make it so that when the semiconductor substrate 71 is observed from a direction perpendicular to the main surface of the semiconductor substrate 71, the transistor 22 and the bump BMP11 do not overlap. In addition, it is also possible to make it so that when the semiconductor substrate 71 is observed from a direction perpendicular to the main surface of the semiconductor substrate 71, the transistor 21 and a bump different from the bump BMP11 overlap. It is also possible to apply the technology disclosed in this disclosure to at least one stage of the multi-stage amplifier circuit.

[0231] <Configuration Example of the Present Disclosure>

[0232] The present disclosure can also take the following structures. (1)

[0234] A power amplifier circuit comprising:

[0235] A first transistor is formed on a semiconductor substrate;

[0236] a second transistor formed on the semiconductor substrate, the first current being a part of the control current being supplied to the base of the second transistor, and supplying a bias current based on the first current to the first transistor;

[0237] a third transistor formed on the semiconductor substrate, supplied with the second current as a part of the control current at the collector, and outputting a third current based on the second current from the emitter;

[0238] a first metal member electrically connected to the emitter of the first transistor and arranged to overlap with a first arrangement region where the first transistor is arranged in a plan view of the semiconductor substrate; and

[0239] a second metal member electrically connected to the emitter of the third transistor;

[0240] The third transistor is provided so as to overlap with the first metal member in the plan view. (2)

[0242] The power amplifier circuit according to (1) above, wherein:

[0243] further comprising: a fourth transistor formed on the semiconductor substrate, the second current as a part of the control current being supplied to the collector, connected in parallel with the third transistor, and outputting a fourth current based on the second current from the emitter,

[0244] An emitter of the fourth transistor is electrically connected to the second metal member. (3)

[0246] The power amplifier circuit according to (2) above, wherein:

[0247] The fourth transistor is provided so as to overlap with the second metal member in the plan view. (4)

[0249] The power amplifier circuit according to any one of (1) to (3) above, wherein:

[0250] A first wiring electrically connecting the emitter of the third transistor and the second metal member intersects with a second wiring, and the second wiring is electrically connected to the base of the first transistor. (5)

[0252] The power amplifier circuit according to any one of (2) to (4) above, wherein:

[0253] The third transistor and the fourth transistor have different sizes. (6)

[0255] The power amplifier circuit according to any one of (1) to (5) above, wherein:

[0256] The device further comprises: a fifth transistor formed on the semiconductor substrate, having a collector and a base electrically connected, a fifth current as a part of the control current being supplied to the collector and the base, and outputting the second current from the emitter,

[0257] The collector and the base of the third transistor are electrically connected. (7)

[0259] A power amplifier circuit comprising:

[0260] A first transistor is formed on a semiconductor substrate;

[0261] a second transistor formed on the semiconductor substrate, the first current being a part of the control current being supplied to the base of the second transistor, and supplying a bias current based on the first current to the first transistor;

[0262] a third transistor formed on the semiconductor substrate, supplied with the second current as a part of the control current at the collector, and outputting a third current based on the second current from the emitter;

[0263] a fourth transistor formed on the semiconductor substrate, supplied with the second current at a collector, connected in parallel with the third transistor, and outputting a fourth current based on the second current from an emitter; and

[0264] a first metal member electrically connected to the emitter of the first transistor and arranged to overlap with a first arrangement region where the first transistor is arranged in a plan view of the semiconductor substrate;

[0265] An emitter electrode of the third transistor is electrically connected to the first metal member. (8)

[0267] The power amplifier circuit according to (7) above, wherein:

[0268] The device further comprises: a fifth transistor formed on the semiconductor substrate, having a collector and a base electrically connected, a fifth current as a part of the control current being supplied to the collector and the base, and outputting the second current from the emitter,

[0269] The collector and base of the third transistor are electrically connected,

[0270] The collector and the base of the fourth transistor are electrically connected.

[0271] In addition, the above-mentioned embodiment is for easy understanding of the present invention, and is not intended to limit the present invention. The present invention can be changed / improved without departing from the gist thereof, and the present invention also includes its equivalents.

Claims

1. A power amplifier circuit, comprising: A first transistor is formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, the first current being a part of the control current being supplied to the base of the second transistor, and supplying a bias current based on the first current to the first transistor; a third transistor formed on the semiconductor substrate, supplied with the second current as a part of the control current at the collector, and outputting a third current based on the second current from the emitter; a first metal member electrically connected to the emitter of the first transistor and arranged to overlap with a first arrangement region where the first transistor is arranged in a plan view of the semiconductor substrate; and a second metal member electrically connected to the emitter of the third transistor; The third transistor is provided so as to overlap with the first metal member in the plan view.

2. The power amplifier circuit according to claim 1, wherein: further comprising: a fourth transistor formed on the semiconductor substrate, the second current as a part of the control current being supplied to the collector, connected in parallel with the third transistor, and outputting a fourth current based on the second current from the emitter, An emitter of the fourth transistor is electrically connected to the second metal member.

3. The power amplifier circuit according to claim 2, wherein: The fourth transistor is provided so as to overlap with the second metal member in the plan view.

4. The power amplifier circuit according to any one of claims 1 to 3, wherein: A first wiring electrically connecting the emitter of the third transistor and the second metal member intersects with a second wiring, and the second wiring is electrically connected to the base of the first transistor.

5. The power amplifier circuit according to any one of claims 2 to 4, wherein: The third transistor and the fourth transistor have different sizes.

6. The power amplifier circuit according to any one of claims 1 to 5, wherein: The device further comprises: a fifth transistor formed on the semiconductor substrate, having a collector and a base electrically connected, a fifth current as a part of the control current being supplied to the collector and the base, and outputting the second current from the emitter, The collector and the base of the third transistor are electrically connected.

7. A power amplifier circuit, comprising: A first transistor is formed on a semiconductor substrate; a second transistor formed on the semiconductor substrate, the first current being a part of the control current being supplied to the base of the second transistor, and supplying a bias current based on the first current to the first transistor; a third transistor formed on the semiconductor substrate, supplied with the second current as a part of the control current at the collector, and outputting a third current based on the second current from the emitter; a fourth transistor formed on the semiconductor substrate, supplied with the second current at the collector, connected in parallel with the third transistor, and outputting a fourth current based on the second current from the emitter; as well as a first metal member electrically connected to the emitter of the first transistor and arranged to overlap with a first arrangement region where the first transistor is arranged in a plan view of the semiconductor substrate; An emitter electrode of the third transistor is electrically connected to the first metal member.

8. The power amplifier circuit according to claim 7, wherein: The device further comprises: a fifth transistor formed on the semiconductor substrate, having a collector and a base electrically connected, a fifth current as a part of the control current being supplied to the collector and the base, and outputting the second current from the emitter, The collector and base of the third transistor are electrically connected, The collector and the base of the fourth transistor are electrically connected.

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