Biasing circuit and biasing method of radio frequency amplifier

Abstract

The invention provides a bias circuit and a bias method of a radio frequency amplifier. The bias circuit comprises a reference voltage circuit, a bias voltage circuit and the radio frequency amplifier, the reference voltage circuit comprises a negative feedback system, and the negative feedback system comprises an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor; the reference voltage circuit, the bias voltage circuit and the radio frequency amplifier are connected in sequence; enabling input power supply voltage to pass through a negative feedback system in the reference voltage circuit to obtain first voltage; enabling the first voltage to pass through a resistance voltage division control network of a bias voltage circuit to obtain a second voltage; connecting the second voltage to a grid electrode of an amplifier tube in the radio frequency amplifier, and performing voltage bias on the amplifier tube; the generated second voltage (bias voltage) has small fluctuation along with the power supply voltage, and the second voltage (bias voltage) can be flexibly adjusted through code words, so that the influence of the fluctuation of the power supply voltage on the overall performance of a radio frequency transceiving link is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a bias circuit and a bias method for a radio frequency amplifier. Background Art

[0002] In a common RF amplifier bias circuit, taking a common-source and common-gate amplifier as an example, the common-gate tube of the RF amplifier is biased to the power supply voltage through a resistor, and the common-source tube is biased to a given voltage through a current mirror or the power supply voltage is divided by a resistor to give the tube a bias voltage.

[0003] The bias voltage generated by this common amplifier voltage bias circuit is greatly affected by power supply voltage fluctuations. When the amplifier is actually in use, the power supply voltage will fluctuate by + / -5% to + / -10%. The power supply voltage fluctuation causes the bias voltage to fluctuate greatly, which in turn causes the amplifier tube bias state, such as gate-source voltage and drain-source voltage, to vary greatly. The power consumption and gain of the amplifier also vary greatly with the power supply voltage, causing the overall performance of the RF transceiver link to be greatly affected by power supply voltage fluctuations. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a bias circuit and a bias method for a radio frequency amplifier, wherein the generated second voltage (bias voltage) fluctuates very little with the power supply voltage, and the second voltage (bias voltage) can be flexibly adjusted through codewords, thereby reducing the impact of power supply voltage fluctuations on the overall performance of the radio frequency transceiver link.

[0005] In a first aspect, an embodiment of the present invention provides a bias circuit of a radio frequency amplifier, the circuit comprising: a reference voltage circuit, a bias voltage circuit and the radio frequency amplifier; the reference voltage circuit comprises a negative feedback system, the negative feedback system comprises an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor;

[0006] The reference voltage circuit, the bias voltage circuit and the radio frequency amplifier are connected in sequence;

[0007] The input power supply voltage is passed through the negative feedback system in the reference voltage circuit to obtain a first voltage; the first voltage is passed through the resistor voltage divider control network of the bias voltage circuit to obtain a second voltage; the second voltage is connected to the gate of the amplifier tube in the radio frequency amplifier to perform voltage bias on the amplifier tube.

[0008] Further, the reference voltage circuit includes a first current source, a resistor array and a multiplexer;

[0009] The current in the first current source flows through each resistor in the resistor array to generate a plurality of first output voltages; each of the first output voltages is respectively connected to an input terminal of the multiplexer; and the output terminal of the multiplexer is connected to a negative input terminal of the operational amplifier;

[0010] The positive input terminal of the operational amplifier is respectively connected to one end of the first feedback sampling resistor and one end of the second feedback sampling resistor, the other end of the second feedback sampling resistor is grounded, and the other end of the first feedback sampling resistor is connected to the drain of the first MOS tube;

[0011] The output end of the operational amplifier is connected to the gate of the first MOS tube.

[0012] Further, the multiplexer selects a second output voltage from the plurality of the first output voltages, and sends the second output voltage to the negative input terminal of the operational amplifier;

[0013] The first feedback sampling resistor and the second feedback sampling resistor sample the first voltage and feed it back to the operational amplifier, compare it with the second output voltage generated by the multiplexer, amplify it and input it into the first MOS tube, adjust the first voltage, and keep the first voltage stable.

[0014] Further, the bias voltage circuit includes a decoder, the resistor voltage divider control network and a plurality of switches;

[0015] One end of the resistor voltage-dividing control network is connected to the first voltage, and the other end of the resistor voltage-dividing control network is grounded;

[0016] Each resistor in the resistor voltage divider control network is connected in series in sequence, each resistor in the resistor voltage divider control network generates a corresponding voltage and is connected to one end of a corresponding switch, and the other end of the corresponding switch is connected to the port VB_CAS.

[0017] Furthermore, after the bias voltage control codeword is determined, multiple control codewords are output through the decoder; the on and off of the corresponding switches are controlled respectively by the control codewords; and the corresponding voltages generated by each resistor in the resistor voltage divider control network are selected to obtain the second voltage.

[0018] Furthermore, the RF amplifier includes a second current source, a common source tube, a common gate tube, a second MOS tube, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and an inductor.

[0019] Furthermore, the second voltage biases the common-gate transistor after passing through the third resistor and the third capacitor; the second current source outputs a gate-source voltage after passing through the second MOS transistor;

[0020] The gate-source voltage biases the common source transistor after passing through the first resistor, the first capacitor and the second resistor; the signal passes through the second capacitor and is connected to the gate of the common source transistor;

[0021] When the signal passes through the common source tube and the common gate tube and reaches the output port after passing through the fourth capacitor, the drain of the common gate tube is connected to the inductor to the power supply voltage.

[0022] In a second aspect, an embodiment of the present invention provides a bias method for a radio frequency amplifier, which is applied to the bias circuit of the radio frequency amplifier as described above, wherein the circuit includes a reference voltage circuit, a bias voltage circuit and the radio frequency amplifier; the reference voltage circuit includes a negative feedback system, and the negative feedback system includes an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor; the method includes:

[0023] Passing the input power supply voltage through the negative feedback system in the reference voltage circuit to obtain a first voltage;

[0024] Passing the first voltage through a resistor voltage divider control network of the bias voltage circuit to obtain a second voltage;

[0025] The second voltage is connected to the gate of the amplifier tube in the radio frequency amplifier to apply voltage bias to the amplifier tube.

[0026] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor implements the method described above when executing the computer program.

[0027] In a fourth aspect, an embodiment of the present invention provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute the method as described above.

[0028] The embodiment of the present invention provides a bias circuit and a bias method for a radio frequency amplifier, including: a reference voltage circuit, a bias voltage circuit and the radio frequency amplifier; the reference voltage circuit includes a negative feedback system, the negative feedback system includes an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor; the reference voltage circuit, the bias voltage circuit and the radio frequency amplifier are connected in sequence; the input power supply voltage passes through the negative feedback system in the reference voltage circuit to obtain a first voltage; the first voltage passes through a resistor voltage divider control network of the bias voltage circuit to obtain a second voltage; the second voltage is connected to the gate of an amplifier tube in the radio frequency amplifier to perform voltage bias on the amplifier tube; the generated second voltage (bias voltage) fluctuates very little with the power supply voltage, and the second voltage (bias voltage) can be flexibly adjusted through codewords, thereby reducing the impact of power supply voltage fluctuations on the overall performance of the radio frequency transceiver link.

[0029] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of the bias circuit structure of the radio frequency amplifier provided in Embodiment 1 of the present invention;

[0033] Figure 2 A schematic diagram of the structure of a reference voltage circuit provided in Embodiment 1 of the present invention;

[0034] Figure 3 A schematic diagram of the structure of a bias voltage circuit provided in Embodiment 1 of the present invention;

[0035] Figure 4 A schematic diagram of the structure of a radio frequency amplifier provided in Embodiment 1 of the present invention;

[0036] Figure 5 A schematic diagram showing a curve comparison between the bias circuit provided in the first embodiment of the present invention and a conventional bias circuit;

[0037] Figure 6 This is a flow chart of a biasing method for a radio frequency amplifier provided in Embodiment 2 of the present invention.

[0038] icon:

[0039] 1-reference voltage circuit; 2-bias voltage circuit; 3-RF amplifier. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] To facilitate understanding of this embodiment, the embodiment of the present invention is described in detail below.

[0042] Embodiment 1:

[0043] Figure 1 A schematic diagram of the bias circuit structure of a radio frequency amplifier provided in Embodiment 1 of the present invention.

[0044] Reference Figure 1 , the circuit includes: a reference voltage circuit 1, a bias voltage circuit 2 and a radio frequency amplifier 3; the reference voltage circuit 1 includes a negative feedback system, and the negative feedback system includes an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor;

[0045] The reference voltage circuit 1, the bias voltage circuit 2 and the radio frequency amplifier 3 are connected in sequence;

[0046] The input power supply voltage VDD is passed through the negative feedback system in the reference voltage circuit 1 to obtain the first voltage VREF; the first voltage VREF is passed through the resistor voltage divider control network of the bias voltage circuit 2 to obtain the second voltage VB_CAS; the second voltage VB_CAS is connected to the gate of the amplifier tube in the RF amplifier 3 to perform voltage bias on the amplifier tube.

[0047] Specifically, in the reference voltage circuit 1, the first current source I1_poly flows through the resistors Ra_n~Ra_0 respectively to generate multiple first output voltages (VR_n~VR_0), VR_n~VR_0 are selected by the multiplexer to obtain the second output voltage Vmux, and the second output voltage Vmux is sent to the negative input terminal of the operational amplifier OP. The operational amplifier OP, the first MOS tube M0, the first feedback sampling resistor R4 and the second feedback sampling resistor R5 constitute an LDO that outputs a stable first voltage VREF.

[0048] The first voltage VREF is connected to the resistor Rb_n+1 in the bias voltage circuit 2, the resistors Rb_n+1~Rb_0 are connected in series in sequence, the voltages on the resistors Rb_0~Rb_n are V0~Vn respectively, one port of the switches SW0~SWn is connected to V0~Vn respectively, and the other ports of the switches SW0~SWn are all connected to the port VB_CAS.

[0049] In the RF amplifier 3, the second voltage VB_CAS passes through the series resistor R3 and the third capacitor C3 to bias the common-gate tube M2; the second current source idc passes through the second MOS tube M3 connected in a diode manner, and outputs the gate-source voltage VB_GM. The gate-source voltage VB_GM biases the common-source tube M1 after passing through the first resistor R1, the first capacitor C1 and the second resistor R2. The signal Vin passes through the DC blocking capacitor C2 and is connected to the gate of M1. After the signal flows through M1 and M2, it passes through the DC blocking capacitor C4 and reaches the output port Vout. The drain of M2 is connected to the inductor L1 to the power supply voltage VDD.

[0050] Compared with the prior art, the bias voltage generated by the circuit fluctuates very little with the power supply voltage, and the bias voltage can be flexibly adjusted through codewords, thereby reducing the impact of power supply voltage fluctuations on the overall performance of the RF transceiver link.

[0051] Further, see Figure 2 , the reference voltage circuit (sub-circuit C) includes a first current source I1_poly, a resistor array (Ra_0 to Ra_n) and a multiplexer (sub-circuit A); the negative feedback system includes an operational amplifier OP (abbreviated as operational amplifier), a first MOS tube M0, a first feedback sampling resistor R4 and a second feedback sampling resistor R5;

[0052] The current in the first current source I1_poly flows through each resistor (Ra_n to Ra_0) in the resistor array to generate a plurality of first output voltages (Ra_0 to Ra_n); each first output voltage is respectively connected to an input terminal of the multiplexer; and an output terminal of the multiplexer is connected to a negative input terminal of the operational amplifier;

[0053] The positive input terminal of the operational amplifier is connected to one end of the first feedback sampling resistor and one end of the second feedback sampling resistor respectively, the other end of the second feedback sampling resistor is grounded, and the other end of the first feedback sampling resistor is connected to the drain of the first MOS tube; the output terminal of the operational amplifier is connected to the gate of the first MOS tube.

[0054] Further, the multiplexer selects a second output voltage Vmux from the plurality of first output voltages (VR_0 to VR_n), and sends the second output voltage Vmux to the negative input terminal of the operational amplifier OP;

[0055] The first feedback sampling resistor R4 and the second feedback sampling resistor R5 sample the first voltage and feed it back to the operational amplifier OP, compare it with the second output voltage Vmux generated by the multiplexer, amplify it and input it into the first MOS tube M0, adjust the first voltage VREF, and keep the first voltage VREF stable.

[0056] Further, see Figure 3 , the bias voltage circuit (sub-circuit E) includes a decoder (sub-circuit D), a resistor voltage divider control network (resistors Rb_0 to Rb_n+1) and a plurality of switches (SW0 to SWn); wherein the reference voltage range generated by the resistor voltage divider control network is V0 to Vn;

[0057] One end of the resistor voltage-dividing control network is connected to the first voltage, and the other end of the resistor voltage-dividing control network is grounded;

[0058] Each resistor in the resistor voltage divider control network is connected in series in sequence, each resistor in the resistor voltage divider control network generates a corresponding voltage and is connected to one end of a corresponding switch, and the other end of the corresponding switch is connected to the port VB_CAS.

[0059] Furthermore, after the bias voltage control codeword is determined, multiple control codewords are output through a decoder; the corresponding switches are controlled on and off respectively by the control codewords; and the corresponding voltages generated by each resistor in the resistor voltage divider control network are selected to obtain a second voltage.

[0060] Specifically, when the bias voltage control code word volt_cas <x:0>After confirmation, the control codeword decoder is output after passing through the decoder (sub-circuit D) <n:0>, control codeword decoder <0> ~decoder <n>The switches SW0-SWn are controlled to be on and off respectively, so as to select a second voltage from the voltages V0-Vn to bias the radio frequency amplifier.

[0061] Further, see Figure 4 The RF amplifier (sub-circuit F) includes a second current source IDC, a common source tube M1, a common gate tube M2, a second MOS tube M3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and an inductor L1.

[0062] Furthermore, the second voltage VB_CAS biases the common gate transistor M2 after passing through the third resistor R3 and the third capacitor C3; the second current source idc outputs the gate-source voltage VB_GM after passing through the second MOS transistor M3;

[0063] The gate-source voltage VB_GM biases the common source tube M1 after passing through the first resistor R1, the first capacitor C1 and the second resistor R2; the signal passes through the second capacitor C2 and is connected to the gate of the common source tube M1;

[0064] After the signal passes through the common source tube M1 and the common gate tube M2 and reaches the output port through the fourth capacitor C4, the drain of the common gate tube M2 is connected to the inductor L1 and the power supply voltage VDD.

[0065] Under this bias circuit, even if the power supply voltage fluctuates by + / -5% to + / -10%, the bias voltage VB_CAS fluctuates much less than 5% with the power supply voltage. Therefore, the power consumption and gain of the RF amplifier also fluctuate very little with the power supply voltage, and the overall performance of the RF transceiver link is basically not affected by voltage fluctuations.

[0066] Reference Figure 5 The two curves are the variation curves of the total gain of the RF link with the power supply voltage. The dotted line is the variation of the overall gain of the link with the power supply voltage under the conventional bias circuit, and the solid line is the variation of the overall gain of the link with the power supply voltage under the bias circuit. It can be seen that the bias circuit is not sensitive to the change of the power supply voltage.

[0067] In summary, the bias circuit of the present application outputs a first voltage (reference voltage) with very small voltage fluctuation through a reference voltage circuit, and the second voltage (bias voltage) can be flexibly adjusted through the control codeword, thereby greatly reducing the impact of power supply voltage fluctuations on the overall performance of the RF transceiver link.

[0068] Embodiment 2:

[0069] Figure 6 This is a flow chart of a biasing method for a radio frequency amplifier provided in Embodiment 2 of the present invention.

[0070] Reference Figure 6 , applied to the bias circuit of the radio frequency amplifier as described above, the circuit includes a reference voltage circuit, a bias voltage circuit and a radio frequency amplifier; the reference voltage circuit includes a negative feedback system, the negative feedback system includes an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor; the method includes the following steps:

[0071] Step S101, the input power supply voltage passes through a negative feedback system in a reference voltage circuit to obtain a first voltage;

[0072] Step S102, the first voltage is passed through a resistor voltage divider control network of a bias voltage circuit to obtain a second voltage;

[0073] Step S103, connecting the second voltage to the gate of the amplifier tube in the radio frequency amplifier to apply voltage bias to the amplifier tube.

[0074] An embodiment of the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the bias method of the radio frequency amplifier provided in the above embodiment are implemented.

[0075] An embodiment of the present invention further provides a computer-readable medium having a non-volatile program code executable by a processor, wherein a computer program is stored on the computer-readable medium, and when the computer program is executed by the processor, the steps of the biasing method of the radio frequency amplifier of the above embodiment are executed.

[0076] The computer program product provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0077] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0078] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0079] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0080] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0081] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.< / n>

Claims

1. A bias circuit for a radio frequency amplifier, characterized in that: The circuit comprises: a reference voltage circuit, a bias voltage circuit and the radio frequency amplifier; the reference voltage circuit comprises a negative feedback system, and the negative feedback system comprises an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor; The reference voltage circuit, the bias voltage circuit and the radio frequency amplifier are connected in sequence; The input power supply voltage is passed through the negative feedback system in the reference voltage circuit to obtain a first voltage; the first voltage is passed through the resistor voltage divider control network of the bias voltage circuit to obtain a second voltage; the second voltage is connected to the gate of the amplifier tube in the radio frequency amplifier to perform voltage bias on the amplifier tube.

2. The bias circuit of the radio frequency amplifier according to claim 1, characterized in that: The reference voltage circuit includes a first current source, a resistor array and a multiplexer; The current in the first current source flows through each resistor in the resistor array to generate a plurality of first output voltages; each of the first output voltages is respectively connected to an input terminal of the multiplexer; and the output terminal of the multiplexer is connected to a negative input terminal of the operational amplifier; The positive input terminal of the operational amplifier is respectively connected to one end of the first feedback sampling resistor and one end of the second feedback sampling resistor, the other end of the second feedback sampling resistor is grounded, and the other end of the first feedback sampling resistor is connected to the drain of the first MOS tube; The output end of the operational amplifier is connected to the gate of the first MOS tube.

3. The bias circuit of the radio frequency amplifier according to claim 2, characterized in that: The multiplexer selects a second output voltage from a plurality of the first output voltages, and sends the second output voltage to the negative input terminal of the operational amplifier; The first feedback sampling resistor and the second feedback sampling resistor sample the first voltage and feed it back to the operational amplifier, compare it with the second output voltage generated by the multiplexer, amplify it and input it into the first MOS tube, adjust the first voltage, and keep the first voltage stable.

4. The bias circuit of the radio frequency amplifier according to claim 1, characterized in that: The bias voltage circuit includes a decoder, the resistor voltage divider control network and a plurality of switches; One end of the resistor voltage-dividing control network is connected to the first voltage, and the other end of the resistor voltage-dividing control network is grounded; Each resistor in the resistor voltage divider control network is connected in series in sequence, each resistor in the resistor voltage divider control network generates a corresponding voltage and is connected to one end of a corresponding switch, and the other end of the corresponding switch is connected to the port VB_CAS.

5. The bias circuit of the radio frequency amplifier according to claim 4, characterized in that: When the bias voltage control codeword is determined, multiple control codewords are output after passing through the decoder; the on and off of the corresponding switches are controlled respectively by the control codewords; and the corresponding voltages generated by each resistor in the resistor voltage divider control network are selected to obtain the second voltage.

6. The bias circuit of the radio frequency amplifier according to claim 1, characterized in that: The radio frequency amplifier includes a second current source, a common source tube, a common gate tube, a second MOS tube, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and an inductor.

7. The bias circuit of the radio frequency amplifier according to claim 6, characterized in that: The second voltage biases the common-gate transistor after passing through the third resistor and the third capacitor; the second current source outputs a gate-source voltage after passing through the second MOS transistor; The gate-source voltage biases the common source transistor after passing through the first resistor, the first capacitor and the second resistor; the signal passes through the second capacitor and is connected to the gate of the common source transistor; When the signal passes through the common source tube and the common gate tube and reaches the output port through the fourth capacitor, the drain of the common gate tube is connected to the inductor to the power supply voltage.

8. A biasing method for a radio frequency amplifier, characterized in that: A bias circuit applied to a radio frequency amplifier according to any one of claims 1 to 7, the circuit comprising a reference voltage circuit, a bias voltage circuit and the radio frequency amplifier; The reference voltage circuit includes a negative feedback system, and the negative feedback system includes an operational amplifier, a first MOS tube, a first feedback sampling resistor and a second feedback sampling resistor; the method includes: Passing the input power supply voltage through the negative feedback system in the reference voltage circuit to obtain a first voltage; Passing the first voltage through a resistor voltage divider control network of the bias voltage circuit to obtain a second voltage; The second voltage is connected to the gate of the amplifier tube in the radio frequency amplifier to apply voltage bias to the amplifier tube.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor executes the computer program, the method according to claim 8 is implemented.

10. A computer readable medium having a non-volatile program code executable by a processor, characterized in that: The program code causes the processor to execute the method of claim 8.

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