Circuit module and electronic equipment

Abstract

The invention relates to a circuit module and electronic equipment. The circuit module comprises a printed circuit board and a characteristic matching network, the printed circuit board comprises a top layer, a plurality of middle layers and a bottom layer, and the characteristic matching network is arranged on the printed circuit board; the characteristic matching network comprises a signal transmission line and a POC circuit. The POC circuit comprises a first impedance network, a second impedance network and a POC power supply. One end of the first impedance network is connected with the signal transmission line, the other end of the first impedance network is connected with one end of the second impedance network, and the other end of the second impedance network is connected with the POC power supply; the middle layer is provided with a copper foil hollowed-out area, and the copper foil hollowed-out area is opposite to the first impedance network, the second impedance network and the wiring area between the first impedance network and the second impedance network. According to the invention, the insertion loss of a signal transmission link can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a circuit module and an electronic device. Background Art

[0002] With the rapid development of intelligent assisted driving technology, cameras have become standard sensors for every car. The transmission of video signals between the serializer in the camera module and the deserializer in the autonomous driving domain controller generally adopts a communication protocol based on the GMSL (Gigabit Multimedia Serial Links) architecture. GMSL is a high-speed serial interface launched by Maxim and is widely used in the transmission of in-vehicle video, audio and control signals. At present, the communication protocol based on the GMSL architecture can achieve a maximum single-channel transmission rate of 12Gbps.

[0003] In order to measure the transmission characteristics of the signal in the system, S parameter measurement is introduced, among which the S21 parameter describing the insertion loss is one of the most critical indicators. The insertion loss is used to measure the power attenuation of the signal after passing through the transmission channel. With the continuous upgrading of GMSL technology, the signal transmission rate is getting higher and higher, so the difficulty of passing the S21 parameter test standard is also increasing. In order to achieve the control of the insertion loss indicator, the existing technology mainly controls the characteristic impedance and trace length of the coaxial cable and the printed circuit board trace, and changes the selection and combination of components in the POC (Power Over Coax, a technology that simultaneously transmits power and data through coaxial cable) circuit module, but often ignores the influence of the parasitic capacitance between the circuit components and traces and the reference ground of the printed circuit board, and still faces the risk of test failure. Summary of the invention

[0004] In view of the deficiencies in the prior art, the object of the present invention is to provide a circuit module and an electronic device, which can effectively reduce the insertion loss of the signal transmission link by reducing the parasitic capacitance between the impedance network in the POC circuit and the reference ground of the printed circuit board, and better meet the requirements of the S21 parameter test standard.

[0005] According to a first aspect of the present invention, there is provided a circuit module, comprising: a printed circuit board and a characteristic matching network;

[0006] The printed circuit board comprises a top layer, a plurality of middle layers and a bottom layer, and the characteristic matching network is laid out and wired on the printed circuit board;

[0007] The characteristic matching network includes a signal transmission line and a POC circuit, and the POC circuit includes a first impedance network, a second impedance network and a POC power supply;

[0008] One end of the first impedance network is connected to the signal transmission line, and the other end is connected to one end of the second impedance network, and the other end of the second impedance network is connected to the POC power supply;

[0009] The middle layer is provided with a copper foil hollowed-out area, and the copper foil hollowed-out area is opposite to the first impedance network and the second impedance network and the wiring area therebetween.

[0010] According to one embodiment, the copper foil hollowed-out area is also opposite to a routing area between the first impedance network and the signal transmission line.

[0011] According to one embodiment, the first impedance network includes a first inductor, the second impedance network includes a second inductor, and the inductance of the first inductor is smaller than the inductance of the second inductor;

[0012] According to one embodiment, the characteristic matching network further includes: a DC blocking capacitor;

[0013] The DC blocking capacitor is connected in series to the signal transmission line to isolate the DC power provided by the POC circuit.

[0014] According to one embodiment, the characteristic matching network further includes: an electrostatic protection device;

[0015] One end of the electrostatic protection device is connected to the signal transmission line, and the other end is grounded.

[0016] According to an embodiment, the inductance of the first inductor is between 0.33uH and 2.2uH.

[0017] According to one embodiment, the second impedance network further comprises: a resistance device connected in parallel with the second inductance device;

[0018] The resistance value of the resistor device is between 1 kΩ and 10 kΩ;

[0019] The inductance of the second inductor is between 47uH and 100uH.

[0020] According to a second aspect of the present invention, there is provided an electronic device, comprising the circuit module according to the first aspect of the present invention.

[0021] Technical features and beneficial effects of the present invention:

[0022] The circuit module provided by the present invention utilizes the POC circuit in the characteristic matching network to provide a DC power supply and filter out noise, and effectively ensures the high impedance characteristics of the POC circuit in the full test frequency band of the S parameter by reducing the parasitic capacitance between the impedance network in the POC circuit and the reference ground of the printed circuit board, effectively reduces the insertion loss of the signal transmission link, ensures the transmission performance of the signal transmission link, and better meets the requirements of the S parameter test standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a principle block diagram of the circuit module provided in the embodiment of the present application.

[0024] Figure 2 It is a schematic diagram of the structure of the circuit module provided in the embodiment of the present application.

[0025] Figure 3 This is a schematic diagram of the S parameter insertion loss test provided in an embodiment of the present application.

[0026] Figure 4 It is the inductance frequency impedance characteristic curve of the POC circuit.

[0027] Figure 5 It is the inductance-frequency-impedance characteristic curve of the POC circuit after actual PCB wiring.

[0028] Figure 6 It is the influence of parasitic capacitance C1 on the insertion loss test results.

[0029] Figure 7 It is the influence of parasitic capacitance C2 on the insertion loss test results.

[0030] Figure 8 It is a schematic diagram of the top-level Layout of the circuit module PCB provided in this embodiment.

[0031] Fig. 9 It is a schematic diagram of the bottom layer Layout of the circuit module PCB provided in this embodiment.

[0032] Fig.10 It is the insertion loss test comparison result before and after using the embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with specific implementation methods.

[0034] Embodiment 1:

[0035] like Figure 2The circuit module shown includes a characteristic matching network, which is laid out and wired on a multi-layer printed circuit board. One end of the characteristic matching network is connected to the vehicle camera module through a coaxial transmission line, and the other end is connected to the video signal input end of the deserializer module. The coaxial transmission line is used to transmit video signals, such as GMSL signals. The characteristic matching network consists of two branches, one branch includes a POC circuit, and the other branch runs along the signal transmission line to the input end of the deserializer module, including a signal transmission line, a DC blocking capacitor, and an electrostatic protection device. The POC circuit includes a first impedance network composed of L1, a second impedance network composed of L2 and R1 in parallel, a filter capacitor, and a POC power supply.

[0036] L1 is a small inductor with an inductance value between 0.33uH and 2.2uH. The first impedance network is used to filter the high-frequency band noise. L2 is a large inductor with an inductance value between 47uH and 100uH. R1 is a resistor with a resistance value between 1kΩ and 10kΩ. The second impedance network is used to filter the low-frequency band noise. The low-frequency band refers to 2MHz to 100MHz, and the high-frequency band refers to 100MHz to 3.5GHz.

[0037] The DC blocking capacitor is connected in series to the signal transmission line between the POC circuit and the deserializer module to isolate the DC power provided by the POC circuit from the signal input end of the deserializer module. One end of the electrostatic protection device is connected to the signal transmission line between the DC blocking capacitor and the deserializer module, and the other end is grounded to prevent static electricity from damaging the deserializer module. The electrostatic protection device uses a TVS (Transient Voltage Suppression) device.

[0038] In the signal transmission link, the insertion of cables or components will introduce signal power loss, namely insertion loss (IL). In the S parameter test, it can be represented by the transmission coefficient S21. For a two-port network, its mathematical definition is as follows:

[0039]

[0040] Among them, V1 represents the signal voltage sent by port 1, and V2 represents the signal voltage received at port 2. If it is an ideal lossless transmission channel, the insertion loss is numerically equal to 0dB. The insertion loss measures the energy loss during the transmission process from port 1 to port 2.

[0041] like Figure 3As shown in the figure, when performing the insertion loss test, the vector network analyzer transmits energy from port 1 and injects it into the signal transmission link and the PCB (Printed Circuit Board) through the coaxial probe 1. Board, printed circuit board) board connector, and then transmitted on the signal transmission line of the PCB board, through the POC circuit, DC blocking capacitor and TVS, and finally picked up by the coaxial probe 2 at the input end of the deserializer module, and the measured insertion loss value is determined by importing the corresponding test template limit to determine whether it meets the test requirements. In order to reduce the insertion loss, it is necessary to strictly control the routing of the signal transmission link on the PCB board, control its impedance to 50Ω, and reduce the energy reflected back to the source end due to the impedance mutation in the transmission link. Due to the insertion of the POC circuit, when the routing of the signal transmission line on the PCB board passes through node 1, there will be a parallel impedance of branch one and branch two, where branch one is the impedance of the POC circuit, and branch two is the impedance along the signal transmission line to the input end of the deserializer module. The impedance of branch two has been strictly controlled at 50Ω, so the impedance of branch one is large enough to ensure that the signal energy will not pass through the POC circuit branch, so that the injected signal can be transmitted to the input end of the deserializer module through branch two, thereby reducing the insertion loss and ensuring the transmission performance.

[0042] A typical two-stage inductor POC circuit frequency impedance characteristics, such as Figure 4 As shown, curve 1 is the frequency impedance characteristic of a large inductor alone, curve 2 is the frequency impedance characteristic of a small inductor alone, and curve 3 is the total frequency impedance characteristic of the two inductors after cascading. It can be seen that the cascaded inductor impedance will form a low impedance resonance point m1. The impedance at this point is low, which will provide a low impedance path for the signal on the transmission line, thereby reducing the energy transmitted to the deserializer. After the actual PCB Layout (printed circuit board layout and routing) is completed, this low impedance resonance point will be further deteriorated due to the parasitic capacitance between the inductor and the routing (the routing includes the line and the end point of the line, that is, the pad of the device) and the adjacent copper layer. After the actual PCB Layout is completed, the total frequency impedance characteristic of the two inductors after cascading is as follows Figure 5 As shown in the middle curve 4, the impedance of the low-impedance resonance point will be significantly reduced after wiring, and the resonance point will shift to a lower frequency band, which provides a low-impedance path for the signal at this frequency point to be transmitted to the POC circuit branch, thereby worsening the insertion loss of the signal transmission link.

[0043] The circuit module after the actual PCB layout has parasitic capacitors C1 and C2, and its equivalent circuit is shown as follows Figure 2As shown in . C1 represents the parasitic capacitance of the line between the first impedance network of the POC circuit and the signal transmission line to the ground. According to one embodiment, even if the length of the line between the first impedance network and the signal transmission line is zero, and the small inductor in the first impedance network adopts a smaller 0402 package, the capacitance of C1 is not less than 0.3pF. C2 represents the parasitic capacitance of the line between the first impedance network and the second impedance network of the POC circuit to the ground. According to one embodiment, even if the length of the line between the first impedance network and the second impedance network is zero, since the second impedance network adopts a large inductor, its package size will increase. Only the influence of the package pad, the capacitance of C2 is not less than 2pF. The influence of the capacitance of C1 on the parameter test results of the signal transmission link S21 is shown in the figure. Figure 6 As shown in the figure, C1 mainly affects the high-frequency characteristics. As the capacitance of C1 gradually increases from 0.1pF to 1.3pF, it can be seen that the energy loss in the high-frequency part increases significantly. The influence of the capacitance of C2 on the test results of the signal transmission link S21 parameters is shown in the figure. Figure 7 As shown in the figure, when the capacitance of C2 gradually increases from 0.3pF to 3pF, it can be seen that the resonance point of the S21 parameter begins to shift to a lower frequency band, and the energy loss also increases sharply. When the capacitance of C2 exceeds 2pF, it cannot pass the test requirements of the S21 parameter. It can be seen that reducing the capacitance of C1 and C2 is conducive to improving the impedance of the POC circuit in the S21 parameter test frequency band and reducing the transmission energy loss.

[0044] The circuit module adopts a multi-layer PCB Layout solution. To ensure the impedance of the signal transmission line of 50Ω, the adjacent layer of the routing must have a complete copper clad layer as a reference layer, which is generally the working ground layer or power layer of the circuit board. By optimizing the multi-layer PCB Layout solution, a copper foil hollowing area is set on the copper clad layer relative to the routing area between the first impedance network and the signal transmission line, which can reduce the capacitance of the parasitic capacitor C1. According to one embodiment, the capacitance of C1 can be controlled to 0.1pF. A copper foil hollowing area is set on the copper clad layer relative to the routing area between the first impedance network and the second impedance network, which can reduce the capacitance of the parasitic capacitor C2. According to one embodiment, the capacitance of C2 can be controlled to 0.3pF. Figure 8 and Fig. 9 The schematic diagram of the layout of the top and bottom layers of a multilayer PCB in an embodiment is shown. In this embodiment, the signal transmission line is routed on the top layer, and the components of the first impedance network and the second impedance network of the POC circuit are placed on the bottom layer. The copper foils of the first impedance network and the second impedance network and the routing area between them, as well as the corresponding areas of all intermediate layers in the vertical direction of the routing area between the first impedance network and the signal transmission line are hollowed out. The beneficial effects of adopting this embodiment are as follows: Fig.10As shown, curve 5 is the S parameter insertion loss test result before using this embodiment, and curve 6 is the test result after using this embodiment. When the curve is above the test limit, it means the test is passed, otherwise the test fails. It can be seen that the embodiment of the present application can significantly improve the test result of the S parameter insertion loss of the signal transmission link and greatly improve the pass rate of the test.

[0045] The circuit module of the present invention reduces the parasitic capacitance between the impedance network of the POC circuit and the reference ground layer of the PCB board by optimizing the multi-layer PCB Layout solution, effectively ensures the high impedance characteristics of the POC circuit in the full S parameter test frequency band (2MHz~3.5GHz), effectively reduces the insertion loss of the signal transmission link, and ensures the transmission performance of the signal transmission link. In addition, in automotive electronics projects, changing the device selection on the POC circuit often requires a new round of reliability verification. Therefore, compared with the prior art, the technical solution of the present invention also has the advantages of high efficiency and saving manpower and time costs.

[0046] Embodiment 2:

[0047] An electronic device comprises the circuit module of embodiment 1.

[0048] It should be understood that the above is only an exemplary embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Those skilled in the art can easily conceive of modifications, replacements or adaptive changes without departing from the principle and essence of the present invention, which should all be covered within the protection scope of the present invention.

Claims

1. A circuit module, characterized in that: include: Printed circuit boards and characteristic matching networks; The printed circuit board comprises a top layer, a plurality of middle layers and a bottom layer, and the characteristic matching network is laid out and wired on the printed circuit board; The characteristic matching network includes a signal transmission line and a POC circuit, and the POC circuit includes a first impedance network, a second impedance network and a POC power supply; One end of the first impedance network is connected to the signal transmission line, and the other end is connected to one end of the second impedance network, and the other end of the second impedance network is connected to the POC power supply; The middle layer is provided with a copper foil hollowed-out area, and the copper foil hollowed-out area is opposite to the first impedance network and the second impedance network and the wiring area therebetween.

2. The circuit module according to claim 1, characterized in that: The copper foil hollowed-out area is also opposite to the routing area between the first impedance network and the signal transmission line.

3. The circuit module according to claim 1, characterized in that: The first impedance network includes a first inductor, the second impedance network includes a second inductor, and the inductance of the first inductor is smaller than the inductance of the second inductor.

4. The circuit module according to claim 1, wherein: The characteristic matching network also includes: a DC blocking capacitor; The DC blocking capacitor is connected in series to the signal transmission line to isolate the DC power provided by the POC circuit.

5. The circuit module according to claim 1, characterized in that: The characteristic matching network also includes: an electrostatic protection device; One end of the electrostatic protection device is connected to the signal transmission line, and the other end is grounded.

6. The circuit module according to claim 1, wherein: The inductance of the first inductor is between 0.33uH and 2.2uH.

7. The circuit module according to claim 1, characterized in that: The second impedance network further includes: a resistance device connected in parallel with the second inductance device; The resistance value of the resistor device is between 1 kΩ and 10 kΩ; The inductance of the second inductor is between 47uH and 100uH.

8. An electronic device, characterized in that: The invention comprises the circuit module according to any one of claims 1 to 7.

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