Delay calibration circuit and delay calibration method thereof

Abstract

The invention discloses a delay calibration circuit and a delay calibration method thereof, and the delay calibration circuit comprises a first delay chain, a second delay chain and a calibration circuit. The first delay chain includes a plurality of first delay units, and delays the clock signal for a first delay time to generate a first delay signal. The supply current of each first delay unit is a first current. The second delay chain comprises a plurality of second delay units and third delay units. The second delay unit delays the first signal for a second delay time to generate a second delay signal. The third delay unit delays the second delay signal to generate a third delay signal. The supply current of the second delay unit and the third delay unit is a second current. The calibration circuit adjusts the current ratio of the second current to the first current according to the second delay signal and the third delay signal, so that the second delay time is equal to the first delay time.

Description

Technical Field

[0001] The present invention relates to a delay calibration circuit and a delay calibration method thereof, and in particular to a delay calibration circuit and a delay calibration method thereof for copying the delay time of a delay locked loop to an open delay chain. Background Art

[0002] In today's digital controlled pulse width modulation (PWM) applications, more sophisticated pulse width control capabilities and accuracy are required. However, due to the fact that the system's base frequency is not high enough, the pulse width adjustment of pulse width modulation can only be fine-tuned to the base duty cycle (i.e., the inverse of the frequency). Therefore, a method of using a delay-locked loop (DLL) to provide a delay time that is less than the length of the base duty cycle (the inverse of the base frequency) has been developed. By copying the control signal in the delay-locked loop to control an open-loop delay chain, and using the signal waveforms before and after the input to the delay chain for logical operations, the pulse width of the pulse width modulation signal can be finely controlled.

[0003] However, the characteristics of the delay time of the open-loop delay chain still vary with the inconsistency of temperature, voltage and manufacturing process, and thus have some differences from the delay time of the delay chain controlled by the delay-locked loop. Therefore, it is necessary to optimize the method of how to copy the delay time of the delay chain controlled by the delay-locked loop to another open-loop delay chain. Summary of the invention

[0004] The present invention proposes a delay calibration circuit and a delay calibration method, which adjusts the current ratio of the supply current by comparing the delay time of the last two stages of the open second delay chain with the delay time of the first delay chain of the delay locked loop, so that the delay time of the first delay chain is copied to the second delay chain. Regardless of the delay difference caused by voltage, temperature and manufacturing process, it can be calibrated by the delay calibration circuit and the delay calibration method proposed by the present invention.

[0005] In view of this, a delay calibration circuit includes a delay lock loop, a first delay chain, a second delay chain and a calibration circuit. The delay lock loop generates a first current and a second current according to a clock signal, a first delay signal and a current ratio. The first delay chain includes a plurality of first delay units, and delays the clock signal by a first delay time to generate the first delay signal, wherein the supply current of each first delay unit is the first current. The second delay chain includes a plurality of second delay units and a third delay unit. The second delay unit delays a first signal by a second delay time to generate a second delay signal. The third delay unit delays the second delay signal to generate a third delay signal. The supply current of the second delay unit and the third delay unit is the second current. The first delay unit, the second delay unit and the third delay unit are the same, and the number of the first delay units and the number of the second delay units are the same. The calibration circuit adjusts the current ratio of the second current to the first current according to the second delay signal and the third delay signal, so that the second delay time is equal to the first delay time.

[0006] According to an embodiment of the present invention, the clock signal has a cycle time, and the first delay time is equal to the cycle time.

[0007] According to an embodiment of the present invention, the calibration circuit includes a first D-type flip-flop, a second D-type flip-flop and an adjustment circuit. The first D-type flip-flop samples the second delayed signal using an edge of a second signal to generate a first sampling signal. The second D-type flip-flop samples the third delayed signal using an edge of the second signal to generate a second sampling signal. The adjustment circuit adjusts the current ratio according to the first sampling signal and the second sampling signal.

[0008] According to an embodiment of the present invention, the second signal is the first signal delayed by the first delay time.

[0009] According to an embodiment of the present invention, the calibration circuit further comprises a third D-type flip-flop. The third D-type flip-flop samples the first signal using the edge of the clock signal to generate the second signal.

[0010] According to an embodiment of the present invention, when the first sampling signal and the second sampling signal are both at a first logic level, the adjustment circuit increases the current ratio. When the first sampling signal and the second sampling signal are both at a second logic level, the adjustment circuit reduces the current ratio. When the first sampling signal is at the first logic level and the second sampling signal is at the second logic level, the adjustment circuit maintains the current ratio.

[0011] According to one embodiment of the present invention, the delay calibration circuit further includes a first multiplexer and a register. The first multiplexer selects one of the clock signal and the first signal to provide to the second delay chain. The register is used to store the current ratio. When the first multiplexer selects the clock signal to provide to the second delay chain, the adjustment circuit determines the current ratio according to the first sampling signal and the second sampling signal, and stores the current ratio in the register. When the first multiplexer selects the first signal to provide to the second delay chain, the delay locking loop generates the first current and the second current according to the current ratio stored in the register.

[0012] According to one embodiment of the present invention, the delay locked loop includes a phase detector, a charge pump and a current source. The phase detector compares the phases of the clock signal and the first delay signal to generate a control signal. The charge pump generates a control voltage according to the control signal. The current source generates the first current and the second current according to the control voltage.

[0013] According to one embodiment of the present invention, the current source includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a resistor and a first N-type transistor. The first P-type transistor is coupled between a supply voltage and a first node and is controlled by the first node, wherein a reference current flows through the first node. The second P-type transistor and the first P-type transistor form a first current mirror to generate the first current, wherein the first current mirror has a first mapping ratio, so that the ratio of the first current to the reference current is the first mapping ratio. The third P-type transistor and the first P-type transistor form a second current mirror to generate the second current, wherein the second current mirror has a second mapping ratio, so that the ratio of the second current to the reference current is the second mapping ratio. The resistor is coupled to a ground terminal. The first N-type transistor is coupled between the first node and the resistor, and controls the reference current according to the control voltage.

[0014] According to an embodiment of the present invention, when the calibration circuit generates a first calibration signal to control the second mapping ratio of the second current mirror, when the calibration circuit increases the current ratio, the calibration circuit increases the second mapping ratio using the first calibration signal, and when the calibration circuit decreases the current ratio, the calibration circuit decreases the second mapping ratio using the first calibration signal.

[0015] According to an embodiment of the present invention, the calibration circuit further generates a second calibration signal to control the first mapping ratio of the first current mirror. When the calibration circuit increases the current ratio, the calibration circuit increases the second mapping ratio using the first calibration signal, and decreases the first mapping ratio using the second calibration signal. When the calibration circuit decreases the current ratio, the calibration circuit decreases the second mapping ratio using the first calibration signal, and increases the first mapping ratio using the second calibration signal.

[0016] The present invention further proposes a delay calibration method, comprising: generating the first current and the second current according to a clock signal, a first delay signal, and a current ratio of a first current to a second current; providing a first delay chain, wherein the first delay chain includes a plurality of first delay units, wherein the supply current of each first delay unit is the first current; using the first delay chain to delay the clock signal by a first delay time to generate the first delay signal; providing a second delay chain, wherein the second delay chain includes a plurality of second delay units and a third delay unit, wherein the supply current of each second delay unit and the third delay unit is the second current; using the second delay unit to delay a first signal by a second delay time to generate a second delay signal; using the third delay unit to delay the second delay signal to generate a third delay signal; adjusting the current ratio according to the second delay signal and the third delay signal so that the second delay time is equal to the first delay time; wherein the number of the second delay units is the same as the number of the first delay units; wherein the first delay unit, the second delay unit, and the third delay unit are all the same.

[0017] According to an embodiment of the present invention, the clock signal has a cycle time, and the first delay time is equal to the cycle time.

[0018] According to an embodiment of the present invention, the step of adjusting the current ratio according to the second delayed signal and the third delayed signal includes: sampling the second delayed signal using an edge of a second signal to generate a first sampling signal; sampling the third delayed signal using an edge of the second signal to generate a second sampling signal; and adjusting the current ratio according to the first sampling signal and the second sampling signal.

[0019] According to an embodiment of the present invention, the second signal is the first signal delayed by the first delay time.

[0020] According to an embodiment of the present invention, the step of adjusting the current ratio according to the second delay signal and the third delay signal further includes: sampling the first signal using the edge of the clock signal to generate the second signal.

[0021] According to an embodiment of the present invention, the step of adjusting the current ratio according to the second delay signal and the third delay signal further includes: when the first sampling signal and the second sampling signal are both at a first logic level, increasing the current ratio; when the first sampling signal and the second sampling signal are both at a second logic level, reducing the current ratio; and when the first sampling signal is at the first logic level and the second sampling signal is at the second logic level, maintaining the current ratio.

[0022] According to an embodiment of the present invention, the delay calibration method further includes: selecting one of the clock signal and the first signal to be provided to the second delay chain; when the clock signal is provided to the second delay chain, determining the current ratio according to the first sampling signal and the second sampling signal; storing the current ratio in a register; and when the first signal is provided to the second delay chain, generating the first current and the second current according to the current ratio stored in the register.

[0023] According to one embodiment of the present invention, the step of generating the first current and the second current according to the clock signal, the first delay signal and the current ratio includes: generating a control signal by comparing the phases of the clock signal and the first delay signal; generating a control voltage according to the control signal; and generating the first current and the second current according to the control voltage.

[0024] According to an embodiment of the present invention, the step of generating the first current and the second current according to the control voltage further comprises: generating a reference current by using the control voltage; mapping the reference current to a first mapping ratio by using a first current mirror to generate the first current; and mapping the reference current to a second mapping ratio by using a second current mirror to generate the second current. The current ratio is adjusted by adjusting the first mapping ratio and / or the second mapping ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A circuit diagram showing a delay calibration circuit according to an embodiment of the present invention;

[0026] Figure 2 A waveform diagram showing a calibration circuit according to an embodiment of the present invention;

[0027] Figure 3 A circuit diagram showing a delay calibration circuit according to another embodiment of the present invention;

[0028] Figure 4 A circuit diagram showing a delay calibration circuit according to another embodiment of the present invention; and

[0029] Figure 5 A flowchart of a delay calibration method according to an embodiment of the present invention is shown.

[0030] Figure Number:

[0031] 100,300,400: Delay calibration circuit

[0032] 110: Delay Lock Loop

[0033] 111: Phase detector

[0034] 112: Charge Pump

[0035] 113: Current Source

[0036] 120: First delay chain

[0037] 130: Second delay chain

[0038] 131: First Multiplexer

[0039] 140: Calibration circuit

[0040] 141: The first D-type flip-flop

[0041] 142: Second D-type flip-flop

[0042] 143: Adjustment circuit

[0043] 144: The third D-type flip-flop

[0044] 432: Second multiplexer

[0045] 450: register

[0046] 500: Delay calibration method

[0047] CLK: Clock signal

[0048] SDLY1: First delayed signal

[0049] CC1: First current control signal

[0050] CC2: Second current control signal

[0051] I1: First current

[0052] I2: Second current

[0053] IREF: Reference current

[0054] CLK: Clock signal

[0055] SUP: Upward signal

[0056] SDWN: Downward signal

[0057] VCT: Control voltage

[0058] PM1: The first P-type transistor

[0059] PM2: Second P-type transistor

[0060] PM3: The third P-type transistor

[0061] NM1: The first N-type transistor

[0062] R: Resistance

[0063] VDD: supply voltage

[0064] N1: First Node

[0065] X: First mapping scale

[0066] Y: Second mapping scale

[0067] GND: Ground terminal

[0068] D1(1): The first delay unit

[0069] D1(2): The second first delay unit

[0070] D1(K): Kth first delay unit

[0071] DLY1: First delay time

[0072] D2(1): First and second delay units

[0073] D2(2): The second delay unit

[0074] D2(K-1): (K-1)th second delay unit

[0075] D2(K): Kth second delay unit

[0076] D3: The third delay unit

[0077] DLY2: Second delay time

[0078] SDLY2(1): first and second delay signals

[0079] SDLY2(2): Second delayed signal

[0080] SDLY2(K-1): (K-1)th second delayed signal

[0081] SDLY2(K): Kth second delayed signal

[0082] SDLY3: The third delayed signal

[0083] SOUT: output signal

[0084] SP1: First sampling signal

[0085] SP2: Second sampling signal

[0086] PM1X: First Trimming Circuit

[0087] PM2X: Second trimming circuit

[0088] S1: First signal

[0089] S2: Second signal

[0090] PD: Cycle time

[0091] T1: First time

[0092] SEL1: First selection signal

[0093] SEL2: Second selection signal

[0094] S510~S570: Step Flow DETAILED DESCRIPTION

[0095] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as limiting the present invention. The scope of the present invention should be based on the claims.

[0096] It is worth noting that the following invention may provide multiple embodiments or examples for practicing different features of the present invention. The specific device examples and arrangements described below are only used to briefly and concisely explain the spirit of the present invention and are not used to limit the scope of the present invention. In addition, the following description may reuse the same device symbols or words in multiple examples. However, the purpose of reusing is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0097] In addition, the description of a feature being connected to, coupled to and / or formed on another feature described in the following specification may actually include multiple different embodiments, including that the features are directly in contact, or that other additional features are formed between the features, etc., so that the features are not in direct contact.

[0098] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one device to another device in the figure. It is understood that if the device in the figure is turned upside down, the device described on the "lower" side will become the device on the "upper" side.

[0099] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various devices, components, regions, layers, and / or parts, these devices, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different devices, components, regions, layers, and / or parts. Therefore, a first device, component, region, layer, and / or part discussed below may be referred to as a second device, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0100] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0101] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0102] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art of this invention. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0103] In some embodiments of the present invention, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0104] In the drawings, similar devices and / or features may have the same device symbol. Various devices of the same type may be distinguished by adding a letter or number after the device symbol to distinguish similar devices and / or similar features.

[0105] Figure 1 A circuit diagram of a delay calibration circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the delay calibration circuit 100 includes a delay locked loop 110, a first delay chain 120, a second delay chain 130 and a calibration circuit 140. The delay locked loop 110 generates a first current I1 and a second current I2 according to a clock signal CLK, a first delay signal SDLY1 and a first current control signal CC1.

[0106] like Figure 1 As shown, the delay locked loop 110 includes a phase detector 111, a charge pump 112 and a current source 113. The phase detector 111 compares the phases of the clock signal CLK and the first delay signal SDLY1 to generate an up signal SUP and a down signal SDWN. According to an embodiment of the present invention, the up signal SUP and the down signal SDWN are combined to form a control signal.

[0107] The charge pump 112 generates a control voltage VCT according to a control signal formed by combining the rising signal SUP and the falling signal SDWN. The current source 113 generates a first current I1 and a second current I2 according to the control voltage VCT. Figure 1 As shown, the current source 113 includes a first P-type transistor PM1, a second P-type transistor PM2, a third P-type transistor PM3, a resistor R, and a first N-type transistor NM1.

[0108] The first P-type transistor PM1 is a diode-type transistor and is coupled between the supply voltage VDD and the first node N1, and the reference current IREF flows through the first node N1. The second P-type transistor PM2 and the first P-type transistor PM1 form a first current mirror to generate a first current I1. According to an embodiment of the present invention, the first current mirror has a first mapping ratio X, so that the first current I1 is the reference current IREF multiplied by the first mapping ratio X.

[0109] The third P-type transistor PM3 and the first P-type transistor PM1 form a second current mirror to generate a second current I2. According to an embodiment of the present invention, the second current mirror has a second mapping ratio Y, so that the second current I2 is the reference current IREF multiplied by the second mapping ratio Y. The resistor R is coupled to the ground terminal GND. The first N-type transistor NM1 is coupled between the first node N1 and the resistor R, and controls the magnitude of the reference current IREF according to the control voltage VCT.

[0110] The first delay chain 120 includes a plurality of first delay units D1 and is used to delay the clock signal CLK by a first delay time DLY1 to generate a first delay signal SDLY1. Figure 1 In the embodiment of the present invention, the first delay chain 120 includes a first first delay unit D1(1), a second first delay unit D1(2), ..., and a Kth first delay unit D1(K) which are connected in series in sequence. In addition, a supply current of each of the first first delay unit D1(1), the second first delay unit D1(2), ..., and the Kth first delay unit D1(K) is the first current I1.

[0111] According to an embodiment of the present invention, the delay locked loop 110 is used to adjust the reference current IREF to lock the first delay signal SDLY1 to a period of the clock signal CLK delayed by the clock signal CLK. In other words, the first delay time DLY1 is the period of the clock signal CLK.

[0112] The second delay chain 130 includes a plurality of second delay units D2 and a third delay unit D3, and delays the first signal S1 by a second delay time DLY2 to generate a Kth second delayed signal SDLY2 (K). Figure 1In an embodiment of the present invention, the second delay chain 130 includes a first second delay unit D2(1), a second second delay unit D2(2), ..., a (K-1)th second delay unit D2(K-1), a Kth second delay unit D2(K), and a third delay unit D3 which are sequentially connected in series. In other words, the number of the second delay units D2 is the same as the number of the first delay units D1. According to an embodiment of the present invention, the structures of the first delay unit D1, the second delay unit D2, and the third delay unit D3 are the same.

[0113] In addition, the supply current of each of the first second delay unit D2(1), the second second delay unit D2(2), . . . , the Kth second delay unit D2(K) and the third delay unit D3 is the second current I2. Figure 1 As shown, the output signals of the first second delay unit D2(1), the second second delay unit D2(2), ..., and the Kth second delay unit D2(K) are respectively the first second delay signal SDLY2(1), the second second delay signal SDLY2(2), ..., the (K-1)th second delay signal SDLY2(K-1) and the Kth second delay signal SDLY2(K), and the output signal of the third delay unit D3 is the third delay signal SDLY3.

[0114] According to an embodiment of the present invention, the delay calibration circuit 100 further includes a first multiplexer 131, wherein the first multiplexer 131 outputs one of the first second delay signal SDLY2(1), the second second delay signal SDLY2(2), ..., the (K-1)th second delay signal SDLY2(K-1) and the Kth second delay signal SDLY2(K) as the output signal SOUT according to the first selection signal SEL1. Since the first second delay unit D2(1), the second second delay unit D2(2), ..., the Kth second delay unit D2(K) are all the same, the delay time of the first second delay signal SDLY2(1), the second second delay signal SDLY2(2), ..., the (K-1)th second delay signal SDLY2(K-1) and the Kth second delay signal SDLY2(K) with the first signal S1 is as shown in Formula 1:

[0115]

[0116] The calibration circuit 140 includes a first D-type flip-flop 141, a second D-type flip-flop 142, and an adjustment circuit 143. The first D-type flip-flop 141 samples the K-th second delay signal SDLY2(K) using the edge of the second signal S2 to generate a first sampling signal SP1. The second D-type flip-flop 142 samples the third delay signal SDLY3 using the edge of the second signal S2 to generate a second sampling signal SP2. The adjustment circuit 143 adjusts the ratio of the second mapping ratio Y to the first mapping ratio X according to the first sampling signal SP1 and the second sampling signal SP2.

[0117] According to other embodiments of the present invention, the first D-type flip-flop 141 can utilize the edge of the second signal S2 to sample the (K-1)th second delayed signal SDLY2(K-1), and the second D-type flip-flop 142 can utilize the edge of the second signal S2 to sample the Kth second delayed signal SDLY2(K), so that the adjustment circuit 143 adjusts the ratio of the second mapping ratio Y to the first mapping ratio X according to the first sampling signal SP1 and the second sampling signal SP2.

[0118] According to an embodiment of the present invention, the current source 113 further includes a first trimming circuit PM1X, wherein the first trimming circuit PM1X and the third P-type transistor PM3 are connected in parallel to each other, and adjust the second current I2 according to the first current control signal CC1. The adjustment circuit 143 generates a first current control signal CC1 according to the first sampling signal SP1 and the second sampling signal SP2, and is used to control the first trimming circuit PM1X to adjust the second current I2, thereby adjusting the ratio of the second mapping ratio Y to the first mapping ratio X. In other words, the adjustment circuit 143 affects the current ratio of the second current I2 to the first current I1 by adjusting the second mapping ratio Y, so that the second delay time DLY2 is close to the first delay time DLY1.

[0119] According to some embodiments of the present invention, the second signal S2 is the first signal S1 delayed by the first delay time DLY1. According to some embodiments of the present invention, since the first delay time DLY1 is the cycle time of the clock signal CLK, the second signal S2 can also be regarded as the result of the first signal S1 delaying the cycle time of the clock signal CLK. When the second signal S2 is used to sample the K-th second delay signal SDLY2 (K) and the third delay signal SDLY3, the adjustment circuit 143 can obtain the relationship between the second delay time DLY2 and the first delay time DLY1 according to the first sampling signal SP1 and the second sampling signal SP2, and then adjust the current ratio of the second current I2 to the first current I1 by adjusting the second mapping ratio Y.

[0120] According to an embodiment of the present invention, the calibration circuit 140 further includes a third D-type flip-flop 144. The third D-type flip-flop 144 samples the first signal S1 using the edge of the clock signal CLK to generate the second signal S2. In other words, the third D-type flip-flop 144 is used to delay the first signal S1 by the cycle time of the clock signal CLK to generate the second signal S2.

[0121] Figure 2 The waveform diagram of the calibration circuit according to one embodiment of the present invention is shown. Figure 2 As shown, the third D-type flip-flop 144 samples the first signal S1 using the clock signal CLK at the first time T1, and the generated second signal S2 is the first signal S1 delayed by the cycle time PD of the clock signal CLK. In addition, the first D-type flip-flop 141 and the second D-type flip-flop 142 also sample the Kth second delayed signal SDLY2(K) and the third delayed signal SDLY3 using the second signal S2 at the first time T1.

[0122] According to one embodiment of the present invention, when the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3 sampled by the first D-type flip-flop 141 and the second D-type flip-flop 142 at the first time T1 are both at a low logic level, it represents that the second delay time DLY2 is greater than the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 utilizes the first current control signal CC1 to increase the second mapping ratio Y, so that the second current I2 increases and the second delay time DLY2 is reduced.

[0123] According to another embodiment of the present invention, when the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3 sampled by the first D-type flip-flop 141 and the second D-type flip-flop 142 at the first time T1 are both at a high logic level, it represents that the second delay time DLY2 is less than the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 utilizes the first current control signal CC1 to reduce the second mapping ratio Y, so that the second current I2 is reduced and the second delay time DLY2 is increased.

[0124] According to another embodiment of the present invention, when the Kth second delay signal SDLY2 (K) sampled by the first D-type flip-flop 141 is at a high logic level and the second D-type flip-flop 142 and the third delay signal SDLY3 are at a low logic level, it represents that the second delay time DLY2 is approximately equal to the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 maintains the second mapping ratio Y without adjusting the current ratio of the second current I2 and the first current I1.

[0125] According to an embodiment of the present invention, when the number of second delay units D2 (that is, the number of first delay units D1) is greater, the difference between the first delay time DLY1 and the second delay time DLY2 is smaller after calibration by the calibration circuit 140. In other words, the greater the number of second delay units D2 connected in series, the closer the second delay time DLY2 will be to the cycle time PD of the clock signal CLK after calibration by the calibration circuit 140.

[0126] Figure 3 A circuit diagram of a delay calibration circuit according to another embodiment of the present invention is shown. Figure 3 The delay calibration circuit 300 is Figure 1 Compared to the delay calibration circuit 100, the delay calibration circuit 300 further includes a second trimming circuit PM2X, wherein the second trimming circuit PM2X and the second P-type transistor PM2 are connected in parallel to each other and adjust the first current I1 according to the second current control signal CC2.

[0127] According to some embodiments of the present invention, when the adjustment circuit 143 determines that the current ratio of the second current I2 to the first current I1 needs to be adjusted based on the first sampling signal SP1 and the second sampling signal SP2, the adjustment circuit 143 can not only use the first current control signal CC1 to adjust the second mapping ratio Y, but can also use the second current control signal CC2 to adjust the first mapping ratio X, thereby adjusting the current ratio of the second current I2 to the first current I1 to a greater extent.

[0128] According to one embodiment of the present invention, when the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3 sampled by the first D-type flip-flop 141 and the second D-type flip-flop 142 at the first time T1 are both at a low logic level, it represents that the second delay time DLY2 is greater than the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 utilizes the first current control signal CC1 to increase the second mapping ratio Y and utilizes the second current control signal CC2 to reduce the first mapping ratio X to reduce the second delay time DLY2.

[0129] According to another embodiment of the present invention, when the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3 sampled by the first D-type flip-flop 141 and the second D-type flip-flop 142 at the first time T1 are both at a high logic level, it represents that the second delay time DLY2 is less than the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 utilizes the first current control signal CC1 to reduce the second mapping ratio Y and utilizes the second current control signal CC2 to increase the first mapping ratio X, so as to increase the second delay time DLY2.

[0130] According to another embodiment of the present invention, when the Kth second delay signal SDLY2(K) sampled by the first D-type flip-flop 141 is at a high logic level and the second D-type flip-flop 142 and the third delay signal SDLY3 are at a low logic level, it represents that the second delay time DLY2 is approximately equal to the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 maintains the first mapping ratio X and the second mapping ratio Y, thereby maintaining the current ratio of the second current I2 and the first current I1.

[0131] Figure 4 A circuit diagram of a delay calibration circuit according to another embodiment of the present invention is shown. Figure 4 The delay calibration circuit 400 is Figure 1 Compared with the delay calibration circuit 100 , the delay calibration circuit 400 further includes a second multiplexer 432 and a register 450 .

[0132] The second multiplexer 432 selects one of the clock signal CLK and the first signal S1 according to the second selection signal SEL2 and provides it to the second delay chain 130. The register 450 is used to store the first current control signal CC1 and the second current control signal CC2 generated by the adjustment circuit 143. In other words, the register 450 is used to store the current ratio of the second current I2 and the first current I1.

[0133] According to an embodiment of the present invention, when the second multiplexer 432 provides the clock signal CLK to the second delay chain 130 according to the second selection signal SEL2, the adjustment circuit 143 adjusts the current ratio of the second current I2 and the first current I1 through the first current control signal CC1 and the second current control signal CC2, so that the second delay time DLY2 is similar to the first delay time DLY1 (that is, the cycle time PD of the clock signal CLK). Subsequently, the first current control signal CC1 and the second current control signal CC2 that make the second delay time DLY2 similar to the first delay time DLY1 are stored in the register 450.

[0134] According to another embodiment of the present invention, when the second multiplexer 432 provides the second signal S2 to the second delay chain 130 according to the second selection signal SEL2, the calibration circuit 140 stops operating, and the first trimming circuit PM1X and the second trimming circuit PM2X respectively operate according to the first current control signal CC1 and the second current control signal CC2 stored in the register 450, so that the second delay time DLY2 is approximately equal to the first delay time DLY1.

[0135] In other words, with the second multiplexer 432 and the register 450, the delay calibration circuit 400 can perform calibration in the idle time before receiving the first signal S1, and store the calibrated first current control signal CC1 and the second current control signal CC2 in the register 450. When the second delay chain 130 receives the first signal S1, the first current control signal CC1 and the second current control signal CC2 stored in the register 450 can be directly used to control the first trimming circuit PM1X and the second trimming circuit PM2X.

[0136] In addition, with the second multiplexer 432 and the register 450 , the operating frequency of the calibration circuit 140 can be reduced, thereby reducing power consumption and shortening the waiting time required for other circuits when the calibration circuit 140 is calibrating.

[0137] Figure 5 The following is a flowchart of a delay calibration method according to an embodiment of the present invention. Figure 1 The delay calibration device 100 is described in detail by taking an example.

[0138] First, the delay locked loop 110 generates the first current I1 and the second current I2 according to the clock signal CLK, the first delay signal SDLY1 and the current ratio of the first current I1 and the second current I2 (step S510). Figure 1 In the embodiment of the present invention, the current ratio of the first current I1 and the second current I2 is determined by the first current control signal CC1. Figure 3 In the embodiment of the present invention, the current ratio between the first current I1 and the second current I2 is determined by the first current control signal CC1 and the second current control signal CC2.

[0139] Next, a first delay chain 120 is provided (step S520). According to one embodiment of the present invention, the first delay chain 120 includes a plurality of first delay units D1, wherein the supply current of each first delay unit D1 is a first current I1. The first delay chain 120 is used to delay the clock signal CLK by a first delay time DLY1 to generate a first delay signal SDLY1 (step S530). According to one embodiment of the present invention, the first delay time DLY1 is controlled by the delay locked loop 110 to be the cycle time PD of the clock signal CLK.

[0140] A second delay chain 130 is provided (step S540 ). According to an embodiment of the present invention, the second delay chain 130 includes a plurality of second delay units D2 and third delay units D3 , wherein a supply current of each of the second delay unit D2 and the third delay unit D3 is a second current I2 .

[0141] The first signal S1 is delayed by a second delay time DLY2 by a plurality of second delay units D2 to generate a second delayed signal SDLY2 (step S550). Figure 1 In an embodiment of the present invention, the first signal S1 is delayed by the second delay time DLY2 to generate the second delay signal SDLY2 by using the first second delay unit D2(1), the second second delay unit D2(2), ... the (K-1)th second delay unit D2(K-1), and the Kth second delay unit D2(K) connected in series. According to an embodiment of the present invention, the number of the second delay units D2 is equal to the number of the first delay units D1.

[0142] The third delay unit D3 delays the second delay signal SDLY2 to generate a third delay signal SDLY3 (step S560). Figure 1 In the embodiment of the present invention, the third delay unit D3 delays the K-th second delay signal SDLY2(K) to generate the third delay signal SDLY3.

[0143] The calibration circuit 140 adjusts the current ratio of the second current I2 to the first current I1 according to the second delay signal SDLY2 and the third delay signal SDLY3 (step S570), so that the second delay time DLY2 is equal to the first delay time DLY1. Figure 1 In the embodiment of FIG. 1 , the calibration circuit 140 adjusts the second mapping ratio Y according to the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3, thereby adjusting the current ratio of the second current I2 to the first current I1. Figure 3 In the embodiment of FIG. 1 , the calibration circuit 140 can adjust the first mapping ratio X and the second mapping ratio Y, thereby adjusting the current ratio of the second current I2 to the first current I1 .

[0144] According to other embodiments of the present invention, the calibration circuit 140 may also adjust the current ratio of the second current I2 to the first current I1 according to the (K-1)th second delay signal SDLY2(K-1) and the Kth second delay signal SDLY2(K), and the second delay time DLY2 may be slightly smaller than the first delay time DLY1. On the other hand, when the calibration circuit 140 adjusts the current ratio according to the second delay signal SDLY2 and the third delay signal SDLY3, the second delay time DLY2 may be slightly larger than the first delay time DLY1.

[0145] According to one embodiment of the present invention, Figure 3As shown, when the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3 sampled by the first D-type flip-flop 141 and the second D-type flip-flop 142 at the first time T1 are both at a low logic level, it means that the second delay time DLY2 is greater than the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 increases the current ratio of the second current I2 to the first current I1 to reduce the second delay time DLY2.

[0146] According to another embodiment of the present invention, Figure 3 As shown, when the Kth second delay signal SDLY2 (K) and the third delay signal SDLY3 sampled by the first D-type flip-flop 141 and the second D-type flip-flop 142 at the first time T1 are both at a high logic level, it represents that the second delay time DLY2 is less than the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 reduces the current ratio of the second current I2 to the first current I1 to increase the second delay time DLY2.

[0147] According to another embodiment of the present invention, Figure 3 As shown, when the Kth second delay signal SDLY2 (K) sampled by the first D-type trigger 141 is at a high logic level and the second D-type trigger 142 and the third delay signal SDLY3 are at a low logic level, it represents that the second delay time DLY2 is approximately equal to the first delay time DLY1 (i.e., the cycle time PD of the clock signal CLK), and therefore the adjustment circuit 143 maintains the current ratio of the second current I2 and the first current I1.

[0148] The present invention proposes a delay calibration circuit and a delay calibration method, which adjusts the current ratio of the supply current by comparing the delay time of the last two stages of the open second delay chain with the delay time of the first delay chain of the delay locked loop, so that the delay time of the first delay chain is copied to the second delay chain. Regardless of the delay difference caused by voltage, temperature and manufacturing process, it can be calibrated by the delay calibration circuit and the delay calibration method proposed by the present invention.

[0149] Although the embodiments of the present invention and its advantages have been described above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the manufacturing process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed manufacturing process, machine, manufacture, material composition, device, method and steps from the disclosure of some embodiments of the present invention. As long as the same functions can be implemented or the same results can be obtained in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned manufacturing process, machine, manufacture, material composition, device, method and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A delay calibration circuit, characterized in that: include: A delay locked loop generates a first current and a second current according to a clock signal, a first delay signal and a current ratio; a first delay chain, comprising a plurality of first delay units, and delaying the clock signal by a first delay time to generate the first delay signal, wherein the supply current of each first delay unit is the first current; a second delay chain, comprising: A plurality of second delay units delay a first signal by a second delay time to generate a second delayed signal; as well as a third delay unit, delaying the second delay signal to generate a third delay signal; wherein the supply current of the second delay unit and the third delay unit is the second current; wherein the first delay unit, the second delay unit and the third delay unit are the same, and the number of the first delay units and the number of the second delay units are the same; and A calibration circuit adjusts the current ratio of the second current to the first current according to the second delay signal and the third delay signal, so that the second delay time is equal to the first delay time.

2. The delay calibration circuit according to claim 1, characterized in that: The above-mentioned clock signal has a cycle time; The first delay time is equal to the cycle time.

3. The delay calibration circuit according to claim 1, wherein: The above calibration circuit includes: a first D-type flip-flop, sampling the second delayed signal using an edge of a second signal to generate a first sampling signal; a second D-type flip-flop, sampling the third delayed signal using the edge of the second signal to generate a second sampling signal; and An adjustment circuit adjusts the current ratio according to the first sampling signal and the second sampling signal.

4. The delay calibration circuit according to claim 3, characterized in that: The second signal is the first signal delayed by the first delay time.

5. The delay calibration circuit according to claim 3, characterized in that: The calibration circuit further comprises: A third D-type flip-flop samples the first signal using the edge of the clock signal to generate the second signal.

6. The delay calibration circuit according to claim 3, characterized in that: When the first sampling signal and the second sampling signal are both at a first logic level, the adjustment circuit increases the current ratio; When the first sampling signal and the second sampling signal are both at a second logic level, the adjustment circuit reduces the current ratio; When the first sampling signal is at the first logic level and the second sampling signal is at the second logic level, the adjustment circuit maintains the current ratio.

7. The delay calibration circuit according to claim 3, characterized in that: Also includes: a first multiplexer, selecting one of the clock signal and the first signal and providing it to the second delay chain; and A register for storing the current ratio; When the first multiplexer selects the clock signal to provide to the second delay chain, the adjustment circuit determines the current ratio according to the first sampling signal and the second sampling signal, and stores the current ratio in the register; When the first multiplexer selects the first signal to provide to the second delay chain, the delay locked loop generates the first current and the second current according to the current ratio stored in the register.

8. The delay calibration circuit according to claim 1, wherein: The delay locked loop comprises: a phase detector, comparing the phases of the clock signal and the first delay signal to generate a control signal; a charge pump, generating a control voltage according to the control signal; and A current source generates the first current and the second current according to the control voltage.

9. The delay calibration circuit according to claim 8, characterized in that: The above current sources include: a first P-type transistor coupled between a supply voltage and a first node and controlled by the first node, wherein a reference current flows through the first node; a second P-type transistor, forming a first current mirror with the first P-type transistor to generate the first current, wherein the first current mirror has a first mapping ratio, so that the ratio of the first current to the reference current is the first mapping ratio; a third P-type transistor, forming a second current mirror with the first P-type transistor to generate the second current, wherein the second current mirror has a second mapping ratio, so that the ratio of the second current to the reference current is the second mapping ratio; a resistor coupled to a ground terminal; and A first N-type transistor is coupled between the first node and the resistor and controls the reference current according to the control voltage.

10. The delay calibration circuit according to claim 9, characterized in that: When the calibration circuit generates a first calibration signal to control the second mapping ratio of the second current mirror; When the calibration circuit increases the current ratio, the calibration circuit increases the second mapping ratio using the first calibration signal; When the calibration circuit reduces the current ratio, the calibration circuit reduces the second mapping ratio using the first calibration signal.

11. The delay calibration circuit according to claim 10, wherein: The calibration circuit further generates a second calibration signal to control the first mapping ratio of the first current mirror; When the calibration circuit increases the current ratio, the calibration circuit increases the second mapping ratio using the first calibration signal and decreases the first mapping ratio using the second calibration signal; When the calibration circuit reduces the current ratio, the calibration circuit reduces the second mapping ratio using the first calibration signal and increases the first mapping ratio using the second calibration signal.

12. A delay calibration method, characterized in that: include: Generate the first current and the second current according to a clock signal, a first delay signal, and a current ratio of a first current to a second current; Providing a first delay chain, wherein the first delay chain comprises a plurality of first delay units, wherein a supply current of each first delay unit is the first current; Delaying the clock signal by a first delay time using the first delay chain to generate the first delayed signal; Providing a second delay chain, wherein the second delay chain comprises a plurality of second delay units and a third delay unit, wherein a supply current of each of the second delay units and the third delay unit is the second current; Using the second delay unit, a first signal is delayed by a second delay time to generate a second delayed signal; Using the third delay unit, delaying the second delay signal to generate a third delay signal; According to the second delay signal and the third delay signal, adjusting the current ratio so that the second delay time is equal to the first delay time; wherein the number of the second delay units is the same as the number of the first delay units; The first delay unit, the second delay unit and the third delay unit are all the same.

13. The delay calibration method according to claim 12, characterized in that: The above-mentioned clock signal has a cycle time; The first delay time is equal to the cycle time.

14. The delay calibration method according to claim 12, wherein: The step of adjusting the current ratio according to the second delay signal and the third delay signal includes: Using an edge of a second signal to sample the second delayed signal to generate a first sampled signal; Using the edge of the second signal to sample the third delayed signal to generate a second sampled signal; and The current ratio is adjusted according to the first sampling signal and the second sampling signal.

15. The delay calibration method according to claim 14, characterized in that: The second signal is the first signal delayed by the first delay time.

16. The delay calibration method according to claim 14, wherein: The step of adjusting the current ratio according to the second delay signal and the third delay signal further includes: The first signal is sampled by using the edge of the clock signal to generate the second signal.

17. The delay calibration method according to claim 14, wherein: The step of adjusting the current ratio according to the second delay signal and the third delay signal further includes: When the first sampling signal and the second sampling signal are both at a first logic level, increasing the current ratio; When the first sampling signal and the second sampling signal are both at a second logic level, reducing the current ratio; and When the first sampling signal is at the first logic level and the second sampling signal is at the second logic level, the current ratio is maintained.

18. The delay calibration method according to claim 14, wherein: include: Selecting one of the clock signal and the first signal to provide to the second delay chain; When the clock signal is provided to the second delay chain, the current ratio is determined according to the first sampling signal and the second sampling signal; storing the current ratio in a register; and When the first signal is provided to the second delay chain, the first current and the second current are generated according to the current ratio stored in the register.

19. The delay calibration method according to claim 12, wherein: The step of generating the first current and the second current according to the clock signal, the first delay signal and the current ratio comprises: Comparing the phases of the clock signal and the first delay signal to generate a control signal; Generate a control voltage according to the control signal; and The first current and the second current are generated according to the control voltage.

20. The delay calibration method according to claim 19, wherein: The step of generating the first current and the second current according to the control voltage further includes: Using the control voltage, a reference current is generated; Using a first current mirror to map the reference current to a first mapping ratio to generate the first current; and Using a second current mirror to map the reference current to a second mapping ratio to generate the second current; The current ratio is adjusted by adjusting the first mapping ratio and / or the second mapping ratio.

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