LDO control device and control system

Abstract

The invention provides an LDO (Low Dropout Regulator) control device and system. The LDO control device comprises an asynchronous clock generation circuit, a counter and a controller, the asynchronous clock generation circuit is used for generating a clock signal, and the signal output end of the asynchronous clock generation circuit is connected with the input end of the counter; the controller is used for reading the count value of the counter, controlling to reduce the output voltage of the LDO when the count value is larger than a preset value and controlling to increase the output voltage of the LDO when the count value is smaller than the preset value, and the signal input end of the controller is connected with the signal output end of the counter. According to the invention, the output voltage of the LDO can be adaptively adjusted.

Description

Technical Field

[0001] The present application relates to the field of digital circuits, and in particular to an LDO control device and a control system. Background Art

[0002] Currently, under the process technology below 22nm, the transistor speeds of chips on the same wafer in the foundry vary greatly at different locations. The speed difference between the chip in the middle of the wafer and the chip at the edge of the wafer is often more than 20%. Therefore, under the same power supply voltage for different chips, while ensuring that the slowest chip can work normally, this voltage is too high for the fastest chip. This will cause the chip with the highest speed and the lowest transistor threshold to have larger leakage and higher dynamic power consumption.

[0003] The most common countermeasure in the industry is to measure the output voltage of the LDO on the machine and perform calibration. However, this measure requires the digital power LDO of the chip to be led out. Under the premise that there are multiple LDOs in the digital power domain, it will greatly increase the packaging and testing costs. In addition, a single calibration of the machine cannot track the aging of the chip. As the chip ages, the speed of its transistors will change, and its requirements for power supply voltage will change. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a LDO control device and a control system, which can adaptively adjust the LDO output voltage.

[0005] The technical solution of the embodiment of the present application is implemented as follows: In a first aspect, an embodiment of the present application provides an LDO control device, the device comprising: Asynchronous clock generation circuits, counters, and controllers; The asynchronous clock generating circuit is used to generate a clock signal, and the signal output end of the asynchronous clock generating circuit is connected to the input end of the counter; The controller is used to read the count value of the counter, and control to reduce the output voltage of the LDO when the count value is greater than a preset value, and control to increase the output voltage of the LDO when the count value is less than the preset value. The signal input end of the controller is connected to the signal output end of the counter.

[0006] In a possible implementation, the asynchronous clock generating circuit includes a first circuit and a second circuit; The first circuit is used to periodically generate the clock signal, and the signal output end of the first circuit is connected to the signal input end of the counter; The second circuit is used to control the length of the cycle of the clock signal generated by the first circuit, and the control end of the second circuit is connected to the first circuit.

[0007] In a possible implementation manner, the first circuit includes a comparator and an AND gate, the input end of the comparator is clamped to a high level and a low level respectively, the output end of the comparator is connected to the input end of the AND gate, the output end of the AND gate is connected to the input end of the counter, and when the output of the AND gate changes from a zero level to a high level, the counter counts by one; When the comparator is working, the output end of the comparator outputs a high level and a low level; when the comparator is not working, the output end of the comparator outputs two high levels.

[0008] In a possible implementation manner, the second circuit is used to control whether the comparator works, and a control end of the second circuit is connected to the comparator.

[0009] In a possible implementation manner, the second circuit includes a delay circuit and a NAND gate, one input end of the NAND gate is connected to the output end of the AND gate, and the other input end of the NAND gate is connected to the output end of the AND gate through the delay circuit; The delay circuit is a copy of the longest path in the digital circuit pipeline that supplies power to the LDO, and the delay time of the delay circuit is greater than the sum of the delays of the comparator, the AND gate, and the NAND gate; The output end of the NAND gate is connected to the comparator, and the output end of the NAND gate is used to control whether the comparator works. When the NAND gate outputs a low level, the comparator does not work; when the NAND gate outputs a high level, the comparator works.

[0010] In a possible implementation manner, the delay time of the delay circuit is greater than ten times the sum of the delays of the comparator, the AND gate, and the NAND gate.

[0011] In a possible implementation, the LDO includes at least one PMOS power tube, and when the count value is less than a preset value, the controller controls to increase the number of PMOS power tubes that are turned on; when the count value is greater than the preset value, the controller controls to reduce the number of PMOS power tubes that are turned on.

[0012] In one possible implementation, whether to increase or decrease the number of open PMOS power tubes is based on whether the count value is less than or greater than a preset value, the count value is an integer, and whenever the count value is less than or greater than the preset value, the controller controls to increase or decrease the number of open PMOS power tubes by 1 until the count value reaches the preset value range.

[0013] In a possible implementation, the preset value is a preset interval, and the preset interval is [N+M1, N+M2], wherein the counter counts through a crystal clock, N is the output N of the counter in each crystal oscillation cycle, and the values ​​of M1 and M2 are determined based on component delays and noise of the asynchronous clock generating circuit.

[0014] In a second aspect, an embodiment of the present application further provides an LDO control system, wherein the LDO control system comprises the LDO control device described in any one of the first aspects.

[0015] The embodiments of the present application have the following beneficial effects: (1) Improved stability and reliability: By combining the asynchronous clock generation circuit with the counter, the device can control the output voltage of the LDO more stably. The generation of the asynchronous clock signal does not rely on the external synchronous clock, which reduces the system's dependence on the external clock source and improves the overall reliability and stability.

[0016] (2) Flexible voltage regulation: The controller adjusts the output voltage of the LDO in real time according to the count value of the counter, making the voltage regulation more flexible and precise. Whether increasing or decreasing the voltage, it can be achieved by changing the count value of the counter without the need for complex control logic.

[0017] (3) Adaptive adjustment capability: The second circuit controls the cycle length of the clock signal generated by the first circuit, so that the device has adaptive adjustment capability. In the case of large load changes, it can quickly respond and adjust the output voltage of the LDO to meet the system's requirements for voltage stability.

[0018] (4) Efficient energy management: By controlling the number of PMOS power tubes turned on to adjust the output voltage of the LDO, the device can achieve efficient energy management. When needed, the number of power tubes is increased to improve the voltage output capability, and when not needed, the number of power tubes is reduced to reduce power consumption, thereby improving the overall energy efficiency of the system.

[0019] (5) Reduce noise interference: Since the generation of asynchronous clock signals does not rely on external synchronous clocks, the noise interference introduced by the clock signals is reduced. At the same time, through precise delay circuit design, the noise generated by the internal logic gate can be further reduced, and the purity of the LDO output voltage can be improved.

[0020] (6) Improve system response speed: The delay time of the delay circuit is greater than the sum of the delays of the comparator, AND gate, NAND gate and other components, ensuring the stability and accuracy of the control signal.

[0021] (7) Enhanced scalability: The design of the device has strong scalability. The counting range, preset value, number of PMOS power tubes and other parameters of the counter can be adjusted according to actual needs to meet the needs of different application scenarios.

[0022] In summary, the LDO control device realizes precise control and adaptive adjustment of the LDO output voltage through the combination of an asynchronous clock generation circuit, a counter and a controller, improves the stability, reliability and energy efficiency of the system, reduces noise interference, and enhances the scalability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a circuit schematic diagram of an LDO control device provided in an embodiment of the present application; Figure 2 is a schematic diagram of a comparator provided in an embodiment of the present application; Figure 3 is an asynchronous counting timing diagram provided by an embodiment of the present application; Figure 4 is a schematic diagram of an LDO provided in an embodiment of the present application; Figure 5 This is a schematic diagram of the LDO control logic provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0026] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0028] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0029] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0031] See also Figure 1 , Figure 1 is a circuit schematic diagram of the LDO control device provided in the embodiment of the present application, which will be combined with Figure 1 The embodiments of the present application are described.

[0032] like Figure 1 As shown, an embodiment of the present application provides an LDO control device, the device comprising: Asynchronous clock generation circuit, counter (COUNTER) and controller (DIG LDO CONTROL LOGIC); The asynchronous clock generating circuit is used to generate a clock signal, and the signal output end of the asynchronous clock generating circuit is connected to the input end of the counter; The controller is used to read the count value of the counter, and control to reduce the output voltage of the LDO when the count value is greater than a preset value, and control to increase the output voltage of the LDO when the count value is less than the preset value. The signal input end of the controller is connected to the signal output end of the counter.

[0033] The asynchronous clock generation circuit is responsible for generating a clock signal. This clock signal is asynchronous, which means that it does not rely on the system master clock or any other external synchronization signal. The advantage of the asynchronous clock is its independence and flexibility, which can ensure that the clock signal can still work stably even when other parts of the system are disturbed or fail. Its output is directly connected to the input of the counter to provide a stable clock source for the counter to drive the counting operation of the counter.

[0034] The counter receives the clock signal from the asynchronous clock generation circuit and counts according to the frequency of the clock signal. The output of the counter is connected to the signal input of the controller, and the current count value is fed back to the controller in real time so that the controller can make corresponding control decisions based on the count value.

[0035] The controller is the core of the whole device. It is responsible for reading the count value of the counter and controlling the output voltage of the LDO according to the comparison result between the count value and the preset value. Specifically, when the count value is greater than the preset value, the controller will issue an instruction to reduce the output voltage of the LDO; on the contrary, when the count value is less than the preset value, the controller will issue an instruction to increase the output voltage of the LDO. This dynamic adjustment mechanism helps to maintain the stability of the LDO output voltage and optimize energy efficiency. The signal input end of the controller is connected to the signal output end of the counter to obtain the real-time count value; at the same time, the controller is also connected to the LDO in some way (such as directly controlling the adjustment pin of the LDO or through the driving circuit) to achieve control of the LDO output voltage.

[0036] In some embodiments, the asynchronous clock generation circuit includes a first circuit and a second circuit; The first circuit is used to periodically generate the clock signal, and the signal output end of the first circuit is connected to the signal input end of the counter; The second circuit is used to control the length of the cycle of the clock signal generated by the first circuit, and the control end of the second circuit is connected to the first circuit.

[0037] Here, the main function of the first circuit is to periodically generate a clock signal. This means that the circuit will output a pulse signal at a certain fixed time interval (or called a period), and this signal is the clock signal required by the subsequent counter. The period of the clock signal determines the counting speed of the counter, which in turn affects the reaction speed and adjustment accuracy of the entire control device. The signal output end of the first circuit is directly connected to the signal input end of the counter, providing a stable, periodic clock signal for the counter.

[0038] In some embodiments, the first circuit includes a comparator (COPM) and an AND gate (AND), the input terminal of the comparator is clamped to a high level (TIEH) and a low level (TIEL) respectively, the output terminal of the comparator is connected to the input terminal of the AND gate, the output terminal of the AND gate is connected to the input terminal of the counter, and when the output of the AND gate changes from a zero level to a high level, the counter counts by one; When the comparator is working, the output end of the comparator outputs a high level and a low level; when the comparator is not working, the output end of the comparator outputs two high levels.

[0039] Please continue to see Figure 1 , the inputs of the comparator are "clamped" to high and low levels, which means that the two inputs are fixedly connected to the high and low potentials of the power supply. The AND gate has two inputs and one output. The output of the AND gate will output a high level only when all inputs are high; otherwise, the output is a low level.

[0040] When the comparator "works" ("work" here refers to the internal state or the trigger of an external signal), the output terminal will output high and low levels accordingly. When the comparator "does not work", its output terminal will output two high levels. The input of the AND gate is connected to the output of the comparator. When the comparator outputs a high level, if the other input of the AND gate (if any) is also high, the AND gate output changes from zero level to high level. This high level signal is then sent to the input of the counter, triggering the counter to count up by one.

[0041] If the comparator output is low, or the other input of the AND gate is low, the AND gate output is low and the counter does not count. Figure 2 , Figure 2 is a schematic diagram of a comparator provided in an embodiment of the present application, such as Figure 2 As shown, in the initial state, the comparator is reset, and the comparator does not work at this time. The positive and negative ends of the comparator output are pulled high by the PMOS tubes controlled by two reset inverted signals, so two high levels are output to the AND gate. After the AND gate logic judgment, a high level is still output to the counter. This high level will also be input to the second circuit.

[0042] In some embodiments, the second circuit is used to control whether the comparator is working, and a control terminal of the second circuit is connected to the comparator.

[0043] Specifically, the second circuit includes a delay circuit and a NAND gate, one input end of the NAND gate is connected to the output end of the AND gate, and the other input end of the NAND gate is connected to the output end of the AND gate through the delay circuit; The delay circuit is used to prolong the time it takes for the input signal to reach the NAND gate, and the delay time of the delay circuit is greater than the sum of the delays of the comparator, the AND gate, and the NAND gate; The output end of the NAND gate is connected to the comparator, and the output end of the NAND gate is used to control whether the comparator works. When the NAND gate outputs a low level, the comparator does not work; when the NAND gate outputs a high level, the comparator works.

[0044] Please continue to see Figure 1 The embodiment of the present application realizes precise control of the working state of the comparator by combining a delay circuit and a NAND gate. This design utilizes the time delay of signal propagation and the logic function of the logic gate to generate a signal that can control the working state of the comparator.

[0045] The delay circuit is a copy of the longest path in the LDO-powered digital circuit pipeline, which is also the critical path. This delay is necessary. When the control system is stable, the delay of the asynchronous circuit is approximately equal to the target cycle, and the speed of the copied digital circuit reaches the design target, that is, the copied digital pipeline is powered by a suitable power supply voltage and can reach the target frequency, thereby generating an output signal to control the working state of the comparator. The delay time of the delay circuit is designed to be greater than the sum of the delays of the comparator, AND gate, NAND gate and other components themselves to ensure the accuracy and reliability of the entire control logic. This condition is easy to achieve in general digital circuits. The delay of the critical path of general digital circuits is much greater than the sum of the delays of a comparator, AND gate and NAND gate.

[0046] The NAND gate is a logic gate with two or more inputs, and its output state is the result of the AND operation after all inputs are logically negated. In this circuit, one input of the NAND gate is directly connected to the output of the AND gate, and the other input is connected to the output of the AND gate through a delay circuit. In this way, the NAND gate can receive two signals with a slight difference in time and generate output according to the logical states of the two signals.

[0047] When the AND gate outputs a high level, this high level signal will be transmitted to the two input terminals of the NAND gate at the same time. However, due to the existence of the delay circuit, the signal transmitted to the NAND gate through the delay circuit will arrive a period of time later than the signal directly transmitted to the NAND gate.

[0048] At a certain moment, the NAND gate will receive two input signals: one is a direct signal without delay, and the other is a signal after the delay circuit. When both inputs of the NAND gate are high, the reset signal is low. At this time, the reset of the comparator is low, the reset is released, and the comparator starts to compare.

[0049] Afterwards, the comparator outputs high and low levels, and after passing through the AND gate, it outputs a low level to the subsequent counter. At the same time, this low level will continue to be given to the NAND gate, passing through the delay circuit one way and not passing through the delay circuit the other way. Since only one input of the NAND gate is low, the output is high. Therefore, the low level of the other way does not need to pass through the delay circuit to make the NAND gate output a high level, reset the comparator, and complete a cycle.

[0050] See also Figure 3 , Figure 3 is an asynchronous counting timing diagram provided by an embodiment of the present application, such as Figure 3 As shown, this graph shows the input of the counter. Each cycle is mainly composed of two parts, one is a low pulse, and the other is a critical path logic (ie, delay circuit) delay. As mentioned earlier, since the low level does not need to go through the critical path delay, it can generate a high level reset comparator through the NAND gate. The high level needs to go through the critical path delay to make the NAND gate produce a low level and release the reset. Therefore, in one cycle, only the high level lasts for a long time. If the output level of the digital LDO is required to be basically determined by the critical path logic delay, it is necessary to ensure that the sum of the logic delays of the comparator comparison time, the AND gate, and the NAND gate is much less than the critical path logic delay, so that each cycle can be ensured to be approximately equal to the critical path logic delay. In an embodiment of the present application, the sum of the logic delays of the comparator comparison time, the AND gate, and the NAND gate must be less than ten times the critical path logic delay.

[0051] In some embodiments, the LDO includes at least one PMOS power tube. When the count value is less than a preset value, the controller controls to increase the number of PMOS power tubes that are turned on; when the count value is greater than the preset value, the controller controls to reduce the number of PMOS power tubes that are turned on.

[0052] In some embodiments, whether to increase or decrease the number of open PMOS power tubes is based on whether the count value is less than or greater than a preset value, and the count value is an integer. Whenever the count value is less than or greater than the preset value, the controller controls to increase or decrease the number of open PMOS power tubes by 1 until the count value reaches the preset value range.

[0053] In some embodiments, the preset value is a preset interval, and the preset interval is [N+M1, N+M2], wherein the counter counts through a crystal clock, N is the output N of the counter in each crystal oscillation cycle, and the values ​​of M1 and M2 are determined based on component delays and noise of the asynchronous clock generating circuit.

[0054] In conjunction with the above embodiments, please refer to Figure 4 , Figure 4 is a schematic diagram of an LDO provided in an embodiment of the present application, such as Figure 4 As shown in the figure, the LDO is composed of a series of PMOS power tubes of equal size. The more PMOS tubes are turned on, the stronger the load capacity of the digital LDO is. Under the same load condition, the higher the output voltage is. The speed and leakage of digital logic are both positively correlated with the supply voltage, that is, the higher the supply voltage, the faster the digital logic is. The higher the supply voltage, the greater the leakage of digital logic. Therefore, in order to ensure the minimum power consumption, it is necessary to provide a suitable power supply voltage for the digital load. The power supply voltage should not be too high, resulting in excessive leakage and power consumption; nor should it be too low, resulting in insufficient digital logic speed, which will cause errors in the digital logic and the entire chip will become a bad chip.

[0055] To achieve a balance between speed and leakage for digital LDO, see Figure 5 , Figure 5 : is a schematic diagram of the LDO control logic provided in the embodiment of the present application, such as Figure 5As shown, a crystal clock is used for counting, the frequency of the crystal is Fc, and the digital target clock frequency is N times the crystal frequency, that is, N×Fc. Therefore, the target period of the digital circuit is T, and the crystal oscillation period is N×T. Ideally, the output voltage of the digital LDO is appropriate, and the period of the digital circuit is determined by the logic delay of the critical path. Therefore, ignoring the comparator delay, the AND gate and the NAND gate delay, ideally, the output of the counter in each crystal oscillation period is N. At this time, the output voltage of the digital LDO makes the digital logic delay just meet the requirements of the period. However, considering that there are comparator delays, AND gates, and NAND gate delays in the asynchronous control circuit period, it is necessary to ensure a certain margin, and select the counter output as N+M, where M is an integer greater than zero, to ensure that there is a certain margin in the digital circuit logic. In addition, due to the presence of noise, the counting result of the comparator will have certain fluctuations. In order to prevent the digital LDO from frequently adjusting the number of PMOS power units, a certain range can be set for the margin M. That is, when the counter output is between N+M1 and N+M2, the digital LDO does not adjust the number of PMOS power units. When the counter output is less than N+M1, the number of PMOS power units turned on is increased, the output voltage of the digital LDO is increased, the speed of the digital critical path delay is increased, and the speed of the entire digital load is increased to ensure that the speed of the digital circuit meets the cycle requirements. When the counter output is greater than N+M2, the number of PMOS power units turned on is reduced. At this time, the counter output result is too large, indicating that the digital logic speed is too fast and the digital leakage is too large, so it is necessary to reduce the voltage and reduce the leakage. In the specific implementation process, the count value is an integer. Whenever the count value is less than or greater than a unit of the preset value, the controller controls to increase or decrease the number of PMOS power tubes turned on, and gradually controls the output voltage of the LDO. It should be noted that the digital critical path delay circuit is a copy of a section of the logic circuit with the largest delay in the digital load, which ensures that the minimum cycle requirement of the digital load can be tracked.

[0056] An embodiment of the present application further provides an LDO control system, which includes the LDO control device described in any one of the embodiments of the present application.

[0057] In summary, the embodiments of the present application have the following beneficial effects: (1) Improved stability and reliability: By combining the asynchronous clock generation circuit with the counter, the device can control the output voltage of the LDO more stably. The generation of the asynchronous clock signal does not rely on the external synchronous clock, which reduces the system's dependence on the external clock source and improves the overall reliability and stability.

[0058] (2) Flexible voltage regulation: The controller adjusts the output voltage of the LDO in real time according to the count value of the counter, making the voltage regulation more flexible and precise. Whether increasing or decreasing the voltage, it can be achieved by changing the count value of the counter without the need for complex control logic.

[0059] (3) Adaptive adjustment capability: The second circuit controls the cycle length of the clock signal generated by the first circuit, so that the device has adaptive adjustment capability. In the case of large load changes, it can quickly respond and adjust the output voltage of the LDO to meet the system's requirements for voltage stability.

[0060] (4) Efficient energy management: By controlling the number of PMOS power tubes turned on to adjust the output voltage of the LDO, the device can achieve efficient energy management. When needed, the number of power tubes is increased to improve the voltage output capability, and when not needed, the number of power tubes is reduced to reduce power consumption, thereby improving the overall energy efficiency of the system.

[0061] (5) Reduce noise interference: Since the generation of asynchronous clock signals does not rely on external synchronous clocks, the noise interference introduced by the clock signals is reduced. At the same time, through precise delay circuit design, the noise generated by the internal logic gate can be further reduced, and the purity of the LDO output voltage can be improved.

[0062] (6) Improve system response speed: The delay time of the delay circuit is greater than the sum of the delays of the comparator, AND gate, NAND gate and other components, ensuring the stability and accuracy of the control signal.

[0063] (7) Enhanced scalability: The design of the device has strong scalability. The counting range, preset value, number of PMOS power tubes and other parameters of the counter can be adjusted according to actual needs to meet the needs of different application scenarios.

[0064] In summary, the LDO control device realizes precise control and adaptive adjustment of the LDO output voltage through the combination of an asynchronous clock generation circuit, a counter and a controller, improves the stability, reliability and energy efficiency of the system, reduces noise interference, and enhances the scalability of the system.

[0065] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0066] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0067] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0068] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An LDO control device, characterized in that: The device comprises: Asynchronous clock generation circuits, counters, and controllers; The asynchronous clock generating circuit is used to generate a clock signal, and the signal output end of the asynchronous clock generating circuit is connected to the input end of the counter; The controller is used to read the count value of the counter, and control to reduce the output voltage of the LDO when the count value is greater than a preset value, and control to increase the output voltage of the LDO when the count value is less than the preset value. The signal input end of the controller is connected to the signal output end of the counter.

2. The device according to claim 1, characterized in that The asynchronous clock generating circuit comprises a first circuit and a second circuit; The first circuit is used to periodically generate the clock signal, and the signal output end of the first circuit is connected to the signal input end of the counter; The second circuit is used to control the length of the cycle of the clock signal generated by the first circuit, and the control end of the second circuit is connected to the first circuit.

3. The device according to claim 2, characterized in that The first circuit includes a comparator and an AND gate, the input end of the comparator is clamped to a high level and a low level respectively, the output end of the comparator is connected to the input end of the AND gate, the output end of the AND gate is connected to the input end of the counter, and when the output of the AND gate changes from a zero level to a high level, the counter counts by one; When the comparator is working, the output end of the comparator outputs a high level and a low level; when the comparator is not working, the output end of the comparator outputs two high levels.

4. The device according to claim 3, characterized in that The second circuit is used to control whether the comparator works, and a control end of the second circuit is connected to the comparator.

5. The device according to claim 4, characterized in that The second circuit includes a delay circuit and a NAND gate, one input end of the NAND gate is connected to the output end of the AND gate, and the other input end of the NAND gate is connected to the output end of the AND gate through the delay circuit; The delay circuit is a copy of the longest path in the digital circuit pipeline that supplies power to the LDO, and the delay time of the delay circuit is greater than the sum of the delays of the comparator, the AND gate, and the NAND gate; The output end of the NAND gate is connected to the comparator, and the output end of the NAND gate is used to control whether the comparator works. When the NAND gate outputs a low level, the comparator does not work; when the NAND gate outputs a high level, the comparator works.

6. The device according to claim 5, characterized in that The delay time of the delay circuit is greater than ten times the sum of the delays of the comparator, the AND gate, and the NAND gate.

7. The device according to claim 1, characterized in that The LDO includes at least one PMOS power tube. When the count value is less than a preset value, the controller controls to increase the number of PMOS power tubes that are turned on; when the count value is greater than the preset value, the controller controls to reduce the number of PMOS power tubes that are turned on.

8. The device according to claim 7, characterized in that Whether to increase or decrease the number of PMOS power tubes to be opened is based on whether the count value is less than or greater than a preset value. The count value is an integer. Whenever the count value is less than or greater than the preset value, the controller controls to increase or decrease the number of PMOS power tubes to be opened by 1 until the count value reaches the preset value range.

9. The device according to claim 1, characterized in that The preset value is a preset interval, and the preset interval is [N+M1, N+M2], wherein the counter counts through the crystal clock, N is the output N of the counter in each crystal oscillation cycle, and the values ​​of M1 and M2 are determined based on the component delay and noise of the asynchronous clock generating circuit.

10. An LDO control system, characterized in that: The LDO control system comprises the LDO control device according to any one of claims 1 to 9.

Images