Hysteresis comparator

Abstract

The application provides a hysteresis comparator, comprising a bias voltage providing module, a switch control module, a hysteresis amount adjusting module and a hysteresis comparison module. The application outputs a plurality of intermediate switch signals to the hysteresis amount adjusting module through the switch control module to control the on-off of the current of a plurality of branches in the hysteresis amount adjusting module, thereby providing a current signal with adjustable value to the hysteresis comparison module. The greater the value of the current signal, the greater the hysteresis voltage interval of the hysteresis comparator, thereby enabling flexible adjustment of the hysteresis voltage interval of the hysteresis comparator.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of comparator integrated circuits, in particular to a hysteresis comparator. BACKGROUND

[0002] Hysteresis comparators, also known as hysteresis comparators or Schmidt triggers, belong to the field of electronic technology, and play an important role in the design of analog circuits and digital circuits.

[0003] The core feature of the hysteresis comparator is the hysteresis characteristic, and the hysteresis comparator has a hysteresis region, that is, the output signal will change state only when the input signal reaches two different threshold values (a high threshold value and a low threshold value), and the hysteresis characteristic makes the hysteresis comparator have higher stability and reliability when processing noise and fluctuating signals. Further, the hysteresis comparator has a comparison function, which can compare the input signal with the reference level to determine whether the input signal is higher or lower than the reference level, and generate a corresponding output signal accordingly, and the comparison function of the hysteresis comparator is particularly important in signal detection, signal synchronization and other applications. In addition, the hysteresis comparator also has the ability to convert continuous analog signals into binary digital signals (digital signal conversion function), which is widely used in digital signal processing circuits such as analog-to-digital converters (ADC) and digital-to-analog converters (DAC).

[0004] The current traditional hysteresis comparator mainly realizes its hysteresis characteristic through positive feedback, which makes the output state of the comparator flip after the input signal reaches a certain threshold value, and maintains the current output state until the input signal returns to another threshold value, thereby forming a hysteresis interval (also known as a hysteresis window), but the traditional hysteresis comparator cannot adjust the hysteresis interval when the feedback network is fixed. In addition, the power supply of the digital logic circuit and the analog logic circuit in most traditional hysteresis comparators is not separated, which causes mutual interference between the digital logic circuit and the analog logic circuit, affecting the accuracy of the output. SUMMARY

[0005] The present application provides a hysteresis comparator, which can solve at least one of the problems of the traditional hysteresis comparator, such as the unadjustable hysteresis interval (hysteresis voltage interval), the mutual interference between the digital logic circuit and the analog logic circuit in the hysteresis comparator, and the influence on the accuracy of the output.

[0006] The present application provides a hysteresis comparator, which comprises a bias voltage providing module, a switch control module, a hysteresis amount adjusting module and a hysteresis comparison module, wherein,

[0007] The bias voltage providing module is configured to provide bias voltage to the multiple branches in the hysteresis amount adjusting module and to the multiple branches in the hysteresis comparing module.

[0008] The switch control module is configured to receive multiple control signals inputted from outside, to perform internal logic processing according to the multiple control signals, and to output multiple intermediate switch signals to the hysteresis amount adjusting module to control the on-off of the current of the multiple branches in the hysteresis amount adjusting module.

[0009] The hysteresis amount adjusting module is configured to provide a current signal with adjustable value to the hysteresis comparing module according to the intermediate switch signals.

[0010] The hysteresis comparing module is configured to receive a differential signal inputted from outside, to perform signal amplification and comparison processing according to the differential signal and the current signal, and to output a first voltage signal and a second voltage signal to the next stage circuit.

[0011] Optionally, in the hysteresis comparator, the hysteresis comparator further comprises a first power supply module and a second power supply module, wherein the first power supply module is connected to the hysteresis amount adjusting module to supply power to the hysteresis amount adjusting module, and the second power supply module is connected to the hysteresis comparing module to supply power to the hysteresis comparing module.

[0012] Optionally, in the hysteresis comparator, the bias voltage providing module comprises a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q23, a transistor Q24, a transistor Q27, a resistor R1, a resistor R2, a resistor R3, a resistor R6, a resistor R7 and a resistor R8, wherein,

[0013] One end of the resistor R6 is connected to the positive pole of the second power module, the other end of the resistor R6 is connected to the collector of the transistor Q23, the base of the transistor Q23 is connected to the collector of the transistor Q23, the emitter of the transistor Q23 is connected to the collector of the transistor Q24, the base of the transistor Q24 is connected to the collector of the transistor Q24, the emitter of the transistor Q24 is connected to the collector of the transistor Q27, the base of the transistor Q27 is connected to the collector of the transistor Q27, the emitter of the transistor Q27 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector of the transistor Q1, one end of the resistor R2 is connected to the emitter of the transistor Q1, the other end of the resistor R2 is connected to the negative pole of the second power module, the base of the transistor Q1 is also connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the emitter of the transistor Q5, one end of the resistor R8 is connected to the collector of the transistor Q5, the other end of the resistor R8 is connected to the positive pole of the first power module, the emitter of the transistor Q2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the negative pole of the second power module, the base of the transistor Q2 is also connected to the hysteresis comparison module to provide bias voltage for multiple branches in the hysteresis comparison module.

[0014] The resistor R7 is connected between the base of the transistor Q5 and the base of the transistor Q3, one end of the resistor R3 is connected to the collector of the transistor Q3, the other end of the resistor R3 is connected to the positive pole of the first power module, the emitter of the transistor Q3 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is also connected to the collector of the transistor Q4, the emitter of the transistor Q4 is connected to the negative pole of the first power module, the base of the transistor Q4 is connected to the node in series between the transistor Q5 and the transistor Q2, the base of the transistor Q3 is also connected to the hysteresis amount adjustment module to provide bias voltage for multiple branches in the hysteresis amount adjustment module.

[0015] Optionally, in the hysteresis comparator, the hysteresis amount adjustment module comprises: first to fifth branches, wherein,

[0016] The first branch comprises a resistor R4, a transistor Q6, a transistor Q7 and a first switch unit M5, wherein one end of the resistor R4 is connected to the positive pole of the first power module, the other end of the resistor R4 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is connected to the collector of the transistor Q7, the collector of the transistor Q7 is further connected to the first end of the first switch unit M5, the second end of the first switch unit M5 is connected to the negative pole of the first power module, and the third end of the first switch unit M5 is connected to the first output end of the switch control module to receive the first intermediate switch signal of the switch control module;

[0017] The second branch comprises a resistor R5, a transistor Q8, a transistor Q9 and a second switch unit M4, wherein one end of the resistor R5 is connected to the positive pole of the first power module, the other end of the resistor R5 is connected to the collector of the transistor Q8, the emitter of the transistor Q8 is connected to the collector of the transistor Q9, the collector of the transistor Q9 is further connected to the first end of the second switch unit M4, the second end of the second switch unit M4 is connected to the negative pole of the first power module, and the third end of the second switch unit M4 is connected to the second output end of the switch control module to receive the second intermediate switch signal of the switch control module;

[0018] The third branch comprises a resistor R9, a transistor Q10, a transistor Q11 and a third switch unit M3, wherein one end of the resistor R9 is connected to the positive pole of the first power module, the other end of the resistor R9 is connected to the collector of the transistor Q10, the emitter of the transistor Q10 is connected to the collector of the transistor Q11, the collector of the transistor Q11 is further connected to the first end of the third switch unit M3, the second end of the third switch unit M3 is connected to the negative pole of the first power module, and the third end of the third switch unit M3 is connected to the third output end of the switch control module to receive the third intermediate switch signal of the switch control module;

[0019] The fourth branch comprises a resistor R10, a transistor Q12, a transistor Q13 and a fourth switch unit M2, wherein one end of the resistor R10 is connected to the positive pole of the first power module, the other end of the resistor R10 is connected to the collector of the transistor Q12, the emitter of the transistor Q12 is connected to the collector of the transistor Q13, the collector of the transistor Q13 is further connected to the first end of the fourth switch unit M2, the second end of the fourth switch unit M2 is connected to the negative pole of the first power module, and the third end of the fourth switch unit M2 is connected to the fourth output end of the switch control module to receive the fourth intermediate switch signal of the switch control module;

[0020] The fifth branch comprises a resistor R11, a triode Q14, a triode Q15 and a fifth switch unit M1, wherein one end of the resistor R11 is connected to the positive pole of the first power module, the other end of the resistor R11 is connected to the collector of the triode Q14, the emitter of the triode Q14 is connected to the collector of the triode Q15, the collector of the triode Q15 is further connected to the first end of the fifth switch unit M1, the second end of the fifth switch unit M1 is connected to the negative pole of the first power module, and the third end of the fifth switch unit M1 is connected to the fifth output end of the switch control module to receive the fifth intermediate switch signal of the switch control module.

[0021] The base of the triode Q15, the base of the triode Q13, the base of the triode Q11, the base of the triode Q9 and the base of the triode Q7 are all connected to the negative pole of the first power module; the emitter of the triode Q15, the emitter of the triode Q13, the emitter of the triode Q11, the emitter of the triode Q9 and the emitter of the triode Q7 are connected and then connected to the hysteresis comparison module to provide a value-adjustable current signal to the hysteresis comparison module.

[0022] Optionally, in the hysteresis comparator, the first switch unit M5, the second switch unit M4, the third switch unit M3, the fourth switch unit M2 and the fifth switch unit M1 are all NMOS tubes, wherein the first end of the first switch unit M5 is the drain end of the NMOS tube, the second end of the first switch unit M5 is the source end of the NMOS tube, and the third end of the first switch unit M5 is the gate end of the NMOS tube; the first end of the second switch unit M4 is the drain end of the NMOS tube, the second end of the second switch unit M4 is the source end of the NMOS tube, and the third end of the second switch unit M4 is the gate end of the NMOS tube; the first end of the third switch unit M3 is the drain end of the NMOS tube, the second end of the third switch unit M3 is the source end of the NMOS tube, and the third end of the third switch unit M3 is the gate end of the NMOS tube; the first end of the fourth switch unit M2 is the drain end of the NMOS tube, the second end of the fourth switch unit M2 is the source end of the NMOS tube, and the third end of the fourth switch unit M2 is the gate end of the NMOS tube; the first end of the fifth switch unit M1 is the drain end of the NMOS tube, the second end of the fifth switch unit M1 is the source end of the NMOS tube, and the third end of the fifth switch unit M1 is the gate end of the NMOS tube.

[0023] Optionally, in the hysteresis comparator, the hysteresis comparison module includes: a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a transistor Q18, a transistor Q19, a transistor Q20, a transistor Q21, a transistor Q25, a transistor Q26, a transistor Q28, a transistor Q29, a transistor Q30, a transistor Q31, a transistor Q32, a transistor Q33, a transistor Q34, a transistor Q35, a transistor Q36, a transistor Q37 and a transistor Q38, wherein

[0024] The collector of the transistor Q18 is connected to the emitter of the transistor Q15, the base of the transistor Q18 is connected to the collector of the transistor Q18, the emitter of the transistor Q18 is connected to the collector of the transistor Q20, the emitter of the transistor Q20 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the negative electrode of the second power module, the base of the transistor Q18 is also connected to the base of the transistor Q19, the emitter of the transistor Q19 is connected to the collector of the transistor Q21, the base of the transistor Q21 is respectively connected to the base of the transistor Q20 and the collector of the transistor Q21, the emitter of the transistor Q21 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the negative electrode of the second power module, and the collector of the transistor Q19 is connected to the emitter of the transistor Q25;

[0025] The base of the transistor Q25 is connected to the emitter of the transistor Q25, the collector of the transistor Q25 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the positive electrode of the second power module, the base of the transistor Q25 is also connected to the base of the transistor Q26, the collector of the transistor Q26 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to the positive electrode of the second power module, and the emitter of the transistor Q26 is connected to the transistor The collector of the transistor Q28, the emitter of the transistor Q28 is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the negative electrode of the second power module, the resistor R18 is connected between the base of the transistor Q28 and the base of the transistor Q29, the collector of the transistor Q28 is connected to the base of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module;

[0026] The emitter of the transistor Q30 and the emitter of the transistor Q31 are connected to the collector of the transistor Q32, the emitter of the transistor Q32 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to the negative pole of the second power supply module, the collector of the transistor Q30 is connected to one end of the resistor R22, the other end of the resistor R22 is connected to the positive pole of the second power supply module, the collector of the transistor Q31 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to the positive pole of the second power supply module, and the base of the transistor Q30 and the base of the transistor Q31 receive an external input pair of differential signals;

[0027] The collector of the transistor Q30 is also connected to the base of the transistor Q38, the collector of the transistor Q38 is connected to the positive pole of the second power supply module, the emitter of the transistor Q38 is connected to the collector of the transistor Q34, the emitter of the transistor Q34 is connected to one end of the resistor R25, and the other end of the resistor R25 is connected to the negative pole of the second power supply module;

[0028] The collector of the transistor Q37 is connected to the positive pole of the second power supply module, the emitter of the transistor Q37 is connected to the collector of the transistor Q33, the emitter of the transistor Q33 is connected to one end of the resistor R24, and the other end of the resistor R24 is connected to the negative pole of the second power supply module;

[0029] The emitter of the transistor Q35 and the emitter of the transistor Q36 are connected to the collector of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the negative pole of the second power supply module, the collector of the transistor Q35 is connected to the collector of the transistor Q30, the collector of the transistor Q36 is connected to the collector of the transistor Q31, the base of the transistor Q35 is connected to the emitter of the transistor Q37, and the base of the transistor Q36 is connected to the emitter of the transistor Q38;

[0030] The base of the transistor Q32, the base of the transistor Q33, and the base of the transistor Q34 are all connected to the base of the transistor Q2 to receive the bias voltage provided by the bias voltage providing module;

[0031] Among them, the transistors Q18-Q21, the resistor R13, and the resistor R14 constitute a first current mirror; the transistors Q25, Q26, Q28, Q29, the resistor R19, and the resistor R20 constitute a second current mirror; the transistors Q30 and Q31 constitute a first differential pair transistor; and the transistors Q35 and Q36 constitute a second differential pair transistor.

[0032] Optionally, in the hysteresis comparator, the switch control module comprises: first to third control signal input terminals, first to fifth switch signal output terminals, first to third inverters, first to seventh NAND gates, a first NOR gate and a second NOR gate, the first control signal input terminal is connected with the first end of the first NAND gate, the input terminal of the second inverter and the first input terminal of the second NOR gate respectively, the second control signal input terminal is connected with the input terminal of the first inverter, the second input terminal of the second NAND gate, the first input terminal of the first NOR gate and the second input terminal of the second NOR gate respectively, the third control signal input terminal is connected with the input terminal of the third inverter, the second input terminal of the seventh NAND gate, the second input terminal of the first NOR gate and the third input terminal of the second NOR gate respectively, the output terminal of the first inverter is connected with the second input terminal of the first NAND gate and the second input terminal of the fourth NAND gate respectively, the output terminal of the second inverter is connected with the first input terminal of the second NAND gate, the first input terminal of the third NAND gate and the first input terminal of the fourth NAND gate respectively, the output terminal of the third inverter is connected with the second input terminal of the third NAND gate, the output terminal of the first NAND gate is connected with the first end of the fifth NAND gate and the first input terminal of the sixth NAND gate respectively, the output terminal of the second NAND gate is connected with the second input terminal of the fifth NAND gate, the output terminal of the third NAND gate is connected with the second input terminal of the sixth NAND gate, the output terminal of the fourth NAND gate is connected with the first input terminal of the seventh NAND gate, the output terminal of the fifth NAND gate is connected with the first switch signal output terminal, the output terminal of the sixth NAND gate is connected with the second switch signal output terminal, the output terminal of the seventh NAND gate is connected with the fourth switch signal output terminal, the output terminal of the first NOR gate is connected with the third switch signal output terminal, and the output terminal of the second NOR gate is connected with the fifth switch signal output terminal.

[0033] The technical scheme of the present application has at least the following advantages:

[0034] The present application provides a hysteresis comparator, comprising: a bias voltage providing module, a switch control module, a hysteresis amount adjusting module and a hysteresis comparison module. The switch control module outputs multiple intermediate switch signals to the hysteresis amount adjusting module to control the on-off of the currents of multiple branches in the hysteresis amount adjusting module, thereby providing a current signal with adjustable value to the hysteresis comparison module. The positive feedback is realized by the current, and the greater the value of the current signal is, the greater the hysteresis voltage interval of the hysteresis comparator is, so that the hysteresis voltage interval of the hysteresis comparator can be flexibly adjusted.

[0035] Further, the application supplies power to the hysteresis amount adjusting module (digital logic circuit) by using a first power module and supplies power to the hysteresis comparison module (analog logic circuit) by using a second power module, wherein the power supply of the hysteresis comparison module (analog logic circuit) can be adjusted according to the input common mode range without affecting the power supply of the hysteresis amount adjusting module (digital logic circuit), the application separates the power supply of the digital logic circuit and the analog logic circuit, effectively reduces the interference between the two, and improves the accuracy of the device output result. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0037] Figure 1 is a circuit structure schematic diagram of the hysteresis comparator of the embodiment of the present application;

[0038] Figure 2 is a circuit structure schematic diagram of the switch control module of the embodiment of the present application;

[0039] In the drawings, the reference signs are explained as follows:

[0040] 10-bias voltage providing module, 20-switch control module, 30-hysteresis amount adjusting module, 40-hysteresis comparison module. DETAILED DESCRIPTION

[0041] The technical solutions in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0042] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0043] In the description of the present application, it is necessary to point out that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements, it can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0045] The embodiment of the present application provides a hysteresis comparator, which refers to Figure 1 , Figure 1 It is a schematic diagram of the circuit structure of the hysteresis comparator of the embodiment of the present application, which comprises a bias voltage providing module 10, a switch control module 20, a hysteresis amount adjusting module 30 and a hysteresis comparison module 40, wherein

[0046] The bias voltage providing module 10 is used to provide bias voltage for a plurality of branches in the hysteresis amount adjusting module 30, and provide bias voltage for a plurality of branches in the hysteresis comparison module 40;

[0047] The switch control module 20 is used to receive a plurality of control signals inputted from outside, and output a plurality of intermediate switch signals to the hysteresis amount adjusting module 30 according to the internal logic processing of a plurality of control signals, so as to control the on-off of the current of a plurality of branches in the hysteresis amount adjusting module 30;

[0048] The hysteresis amount adjusting module 30 is used to provide a value-adjustable current signal to the hysteresis comparison module 40 according to the intermediate switch signal;

[0049] The hysteresis comparison module 40 is used to receive a differential signal inputted from outside, and perform signal amplification and comparison processing according to the differential signal and the current signal, and output a first voltage signal and a second voltage signal to the subsequent circuit.

[0050] Further, the hysteresis comparator can further comprise a first power supply module and a second power supply module, wherein the first power supply module is connected with the hysteresis amount adjusting module 30 to supply power to the hysteresis amount adjusting module 30; the second power supply module is connected with the hysteresis comparison module 40 to supply power to the hysteresis comparison module 40.

[0051] In the embodiment, the positive pole of the first power module is VDD, and the negative pole is DGND; the positive pole of the second power module is VCC, and the negative pole is VEE.

[0052] In the application, the hysteresis adjustment module (digital logic circuit) is powered by the first power module, and the hysteresis comparison module (analog logic circuit) is powered by the second power module, wherein the power supply of the hysteresis comparison module (analog logic circuit) can be adjusted according to the input common mode range, without affecting the power supply of the hysteresis adjustment module (digital logic circuit). The application separates the power supply of the digital logic circuit and the analog logic circuit, effectively reduces the interference between them, and improves the accuracy of the device output result.

[0053] Preferably, the bias voltage providing module 10 comprises a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q23, a transistor Q24, a transistor Q27, a resistor R1, a resistor R2, a resistor R3, a resistor R6, a resistor R7 and a resistor R8.

[0054] One end of the resistor R6 is connected to the positive pole VCC of the second power module, the other end of the resistor R6 is connected to the collector of the transistor Q23, the base of the transistor Q23 is connected to the collector of the transistor Q23, the emitter of the transistor Q23 is connected to the collector of the transistor Q24, the base of the transistor Q24 is connected to the collector of the transistor Q24, the emitter of the transistor Q24 is connected to the collector of the transistor Q27, the base of the transistor Q27 is connected to the collector of the transistor Q27, the emitter of the transistor Q27 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector of the transistor Q1, the emitter of the transistor Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the negative pole VEE of the second power module, the base of the transistor Q1 is also connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the emitter of the transistor Q5, the collector of the transistor Q5 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the positive pole VDD of the first power module, the emitter of the transistor Q2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the negative pole VEE of the second power module, and the base of the transistor Q2 is also connected to the hysteresis comparison module 40 to provide bias voltage for multiple branches in the hysteresis comparison module 40.

[0055] The resistor R7 is connected between the base of the transistor Q5 and the base of the transistor Q3, the collector of the transistor Q3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the positive pole VDD of the first power module, the emitter of the transistor Q3 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is also connected to the collector of the transistor Q4, the emitter of the transistor Q4 is connected to the negative pole DGND of the first power module, the base of the transistor Q4 is connected to the series connection node between the transistor Q5 and the transistor Q2, and the base of the transistor Q3 is also connected to the hysteresis amount adjusting module 30 to provide bias voltage for multiple branches in the hysteresis amount adjusting module 30.

[0056] In the embodiment, the transistors Q1, Q2, Q23, Q24 and Q27 are NPN transistors, and the transistors Q3, Q4 and Q5 are PNP transistors.

[0057] Further, referring to Figure 2 , Figure 2: is a circuit structure diagram of a switch control module according to an embodiment of the present invention. The switch control module 20 includes: first to third control signal input terminals HYST0-HYST2, first to fifth switch signal output terminals U5-U1, first to third inverters X1-X3, first to seventh NAND gates D1-D3, first NOR gate N1 and second NOR gate N2. The first control signal input terminal HYST0 is respectively connected to the first terminal of the first NAND gate D1, the input terminal of the second inverter X2 and the first input terminal of the second NOR gate N2; the second control signal input terminal HYST1 is respectively connected to the input terminal of the first inverter X1, the second input terminal of the second NAND gate D2, the first input terminal of the first NOR gate N1 and the second input terminal of the second NOR gate N2; the third control signal input terminal HYST2 is respectively connected to the input terminal of the third inverter X3, the second input terminal of the seventh NAND gate D7, the second input terminal of the first NOR gate N1 and the third input terminal of the second NOR gate N2; the output terminal of the first inverter X1 is respectively connected to the second input terminal of the first NAND gate D1. the first input terminal of the fifth NAND gate D5 and the first input terminal of the sixth NAND gate D6; the output terminal of the fourth NAND gate D4 is connected to the first input terminal of the seventh NAND gate D7; the output terminal of the fifth NAND gate D5 is connected to the first switch signal output terminal U5, the output terminal of the sixth NAND gate D6 is connected to the second switch signal output terminal U4, and the output terminal of the seventh NAND gate D7 is connected to the fourth switch signal output terminal U2; the output terminal of the first NOR gate N1 is connected to the third switch signal output terminal U3, and the output terminal of the second NOR gate N2 is connected to the fifth switch signal output terminal U1.

[0058] Preferably, the hysteresis adjustment module 30 includes: first to fifth branches, wherein:

[0059] The first branch comprises a resistor R4, a transistor Q6, a transistor Q7 and a first switch unit M5, wherein one end of the resistor R4 is connected to the positive pole VDD of the first power module, the other end of the resistor R4 is connected to the collector of the transistor Q6, the emitter of the transistor Q6 is connected to the collector of the transistor Q7, the collector of the transistor Q7 is further connected to the first end of the first switch unit M5, the second end of the first switch unit M5 is connected to the negative pole DGND of the first power module, and the third end of the first switch unit M5 is connected to the first output end U5 of the switch control module to receive the first intermediate switch signal of the switch control module.

[0060] The second branch comprises a resistor R5, a transistor Q8, a transistor Q9 and a second switch unit M4, wherein one end of the resistor R5 is connected to the positive pole VDD of the first power module, the other end of the resistor R5 is connected to the collector of the transistor Q8, the emitter of the transistor Q8 is connected to the collector of the transistor Q9, the collector of the transistor Q9 is further connected to the first end of the second switch unit M4, the second end of the second switch unit M4 is connected to the negative pole DGND of the first power module, and the third end of the second switch unit M4 is connected to the second output end U4 of the switch control module to receive the second intermediate switch signal of the switch control module.

[0061] The third branch comprises a resistor R9, a transistor Q10, a transistor Q11 and a third switch unit M3, wherein one end of the resistor R9 is connected to the positive pole VDD of the first power module, the other end of the resistor R9 is connected to the collector of the transistor Q10, the emitter of the transistor Q10 is connected to the collector of the transistor Q11, the collector of the transistor Q11 is further connected to the first end of the third switch unit M3, the second end of the third switch unit M3 is connected to the negative pole DGND of the first power module, and the third end of the third switch unit M3 is connected to the third output end U3 of the switch control module to receive the third intermediate switch signal of the switch control module.

[0062] The fourth branch comprises a resistor R10, a transistor Q12, a transistor Q13 and a fourth switch unit M2, wherein one end of the resistor R10 is connected to the positive pole VDD of the first power module, the other end of the resistor R10 is connected to the collector of the transistor Q12, the emitter of the transistor Q12 is connected to the collector of the transistor Q13, the collector of the transistor Q13 is further connected to the first end of the fourth switch unit M2, the second end of the fourth switch unit M2 is connected to the negative pole DGND of the first power module, and the third end of the fourth switch unit M2 is connected to the fourth output end U2 of the switch control module to receive the fourth intermediate switch signal of the switch control module.

[0063] The fifth branch includes a resistor R11, a transistor Q14, a transistor Q15 and a fifth switch unit M1, wherein one end of the resistor R11 is connected to the positive pole VDD of the first power module, the other end of the resistor R11 is connected to the collector of the transistor Q14, the emitter of the transistor Q14 is connected to the collector of the transistor Q15, the collector of the transistor Q15 is further connected to the first end of the fifth switch unit M1, the second end of the fifth switch unit M1 is connected to the negative pole DGND of the first power module, and the third end of the fifth switch unit M1 is connected to the fifth output end U1 of the switch control module to receive the fifth intermediate switch signal of the switch control module;

[0064] The base of the transistor Q15, the base of the transistor Q13, the base of the transistor Q11, the base of the transistor Q9 and the base of the transistor Q7 are all connected to the negative pole DGND of the first power module; the emitter of the transistor Q15, the emitter of the transistor Q13, the emitter of the transistor Q11, the emitter of the transistor Q9 and the emitter of the transistor Q7 are connected to the hysteresis comparison module 40 to provide a value-adjustable current signal I6 for the hysteresis comparison module 40.

[0065] In the embodiment, the transistors Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14 and Q15 are all PNP transistors.

[0066] Further, the first switch unit M5, the second switch unit M4, the third switch unit M3, the fourth switch unit M2 and the fifth switch unit M1 are all NMOS tubes, wherein the first end of the first switch unit M5 is the drain end of the NMOS tube, the second end of the first switch unit M5 is the source end of the NMOS tube, and the third end of the first switch unit M5 is the gate end of the NMOS tube; the first end of the second switch unit M4 is the drain end of the NMOS tube, the second end of the second switch unit M4 is the source end of the NMOS tube, and the third end of the second switch unit M4 is the gate end of the NMOS tube; the first end of the third switch unit M3 is the drain end of the NMOS tube, the second end of the third switch unit M3 is the source end of the NMOS tube, and the third end of the third switch unit M3 is the gate end of the NMOS tube; the first end of the fourth switch unit M2 is the drain end of the NMOS tube, the second end of the fourth switch unit M2 is the source end of the NMOS tube, and the third end of the fourth switch unit M2 is the gate end of the NMOS tube; and the first end of the fifth switch unit M1 is the drain end of the NMOS tube, the second end of the fifth switch unit M1 is the source end of the NMOS tube, and the third end of the fifth switch unit M1 is the gate end of the NMOS tube.

[0067] In the embodiment, HYST0, HYST1 and HYST2 are three control signals inputted from outside of the switch control module 20, and five intermediate switch signals U5-U1 for controlling the first switch unit to the fifth switch unit (M5-M1) to be turned on or turned off are generated through internal logic processing of the switch control module 20, wherein according to Figure 2 According to the circuit structure of the switch control module 20 in the embodiment, the truth table of the switch control module 20 is shown in Table 1, and the switch control module 20 outputs U1-U5, wherein U1-U5=low level "0" or high level "1", and the low level "0" represents controlling the corresponding connected switch unit (one of M1-M5) to be turned off, and the high level "1" represents controlling the corresponding connected switch unit (one of M1-M5) to be turned on.

[0068] Table 1

[0069]

[0070]

[0071] Further, the hysteresis comparison module 40 comprises: a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a transistor Q18, a transistor Q19, a transistor Q20, a transistor Q21, a transistor Q25, a transistor Q26, a transistor Q28, a transistor Q29, a transistor Q30, a transistor Q31, a transistor Q32, a transistor Q33, a transistor Q34, a transistor Q35, a transistor Q36, a transistor Q37 and a transistor Q38.

[0072] The collector of the transistor Q18 is connected to the emitter of the transistor Q15, the base of the transistor Q18 is connected to the collector of the transistor Q18, the emitter of the transistor Q18 is connected to the collector of the transistor Q20, the emitter of the transistor Q20 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the negative pole VEE of the second power module, the base of the transistor Q18 is also connected to the base of the transistor Q19, the emitter of the transistor Q19 is connected to the collector of the transistor Q21, the base of the transistor Q21 is connected to the base of the transistor Q20 and the collector of the transistor Q21 respectively, the emitter of the transistor Q21 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the negative pole VEE of the second power module, the collector of the transistor Q19 is connected to the emitter of the transistor Q25;

[0073] The base of the transistor Q25 is connected to the emitter of the transistor Q25, the collector of the transistor Q25 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the positive pole of the second power module, the base of the transistor Q25 is also connected to the base of the transistor Q26, the collector of the transistor Q26 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to the positive pole VCC of the second power module, the emitter of the transistor Q26 is connected to the collector of the transistor Q28, the emitter of the transistor Q28 is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the negative pole VEE of the second power module, the resistor R18 is connected between the base of the transistor Q28 and the base of the transistor Q29, the collector of the transistor Q28 is connected to the base of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the negative pole VEE of the second power module;

[0074] The emitter of the transistor Q30 and the emitter of the transistor Q31 are connected to the collector of the transistor Q32, the emitter of the transistor Q32 is connected to one end of the resistor R21, the other end of the resistor R21 is connected to the negative pole VEE of the second power module, the collector of the transistor Q30 is connected to one end of the resistor R22, the other end of the resistor R22 is connected to the positive pole VCC of the second power module, the collector of the transistor Q31 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to the positive pole VCC of the second power module, the base of the transistor Q30 and the base of the transistor Q31 receive an external input pair of differential signals VP and VN;

[0075] The collector of the transistor Q30 is also connected to the base of the transistor Q38, the collector of the transistor Q38 is connected to the positive pole VCC of the second power module, the emitter of the transistor Q38 is connected to the collector of the transistor Q34, the emitter of the transistor Q34 is connected to one end of the resistor R25, the other end of the resistor R25 is connected to the negative pole VEE of the second power module;

[0076] The collector of the transistor Q37 is connected to the positive pole VCC of the second power module, the emitter of the transistor Q37 is connected to the collector of the transistor Q33, the emitter of the transistor Q33 is connected to one end of the resistor R24, the other end of the resistor R24 is connected to the negative pole VEE of the second power module;

[0077] The emitter of the transistor Q35 and the emitter of the transistor Q36 are connected to the collector of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the negative pole VEE of the second power module, the collector of the transistor Q35 is connected to the collector of the transistor Q30, the collector of the transistor Q36 is connected to the collector of the transistor Q31, the base of the transistor Q35 is connected to the emitter of the transistor Q37, and the base of the transistor Q36 is connected to the emitter of the transistor Q38;

[0078] The base of the transistor Q32, the base of the transistor Q33, and the base of the transistor Q34 are all connected to the base of the transistor Q2 to receive the bias voltage provided by the bias voltage providing module 10;

[0079] Wherein, the triode Q18, the triode Q19, the triode Q20, the triode Q21, the resistance R13 and the resistance R14 constitute the first current mirror; the triode Q25, the triode Q26, the triode Q28, the triode Q29, the resistance R19, the resistance R20 constitute the second current mirror; the triode Q30 and the triode Q31 constitute the first differential pair; the triode Q35 and the triode Q36 constitute the second differential pair;

[0080] The potential V of the collector position of the triode Q34 OUT1 The potential V of the collector position of the triode Q33 is output as a first voltage signal to the rear stage circuit, OUT2 As a second voltage signal to the rear stage circuit.

[0081] In the embodiment, the triode Q18, the triode Q19, the triode Q20, the triode Q21, the triode Q28, the triode Q29, the triode Q30, the triode Q31, the triode Q32, the triode Q33, the triode Q34, the triode Q35, the triode Q36, the triode Q37 and the triode Q38 are all NPN triodes; the triode Q25, the triode Q26 are all PNP triodes.

[0082] In the embodiment, taking the negative pole DGND of the first power module as the ground end (0V) and the negative pole VEE of the second power module as the ground end (0V) as an example, the working principle of the fifth branch of the switch control module 20, i.e. the resistance R11, the triode Q14, the triode Q15 and the fifth switch unit M1, is described, and the working principles of the remaining first to fourth branches are the same. U5, U4, U3, U2 and U1 are five intermediate switch signals output by the first to fifth output ends of the switch control module 20. Assuming that U2-U5=“1”, I2-I5 pass through M2-M5 to the ground, if U1=“1”, the NMOS tube M1 is turned on, the current I1 flowing through the fifth branch flows to the negative pole DGND (ground end) of the first power module through the NMOS tube M1, the triode Q15 has no current, and the current of the triode Q18-Q21 remains unchanged, which will not affect the subsequent analog logic; if U1=“0”, the NMOS tube M1 is turned off, the current I1 flowing through the fifth branch flows through the triode Q15 to the first current mirror Q18-Q21, and then through the second current mirror Q25, Q26, Q28 and Q29 to affect the analog logic.

[0083] The working principle of the hysteresis comparison module 40 (analog logic) is as follows:

[0084] Since transistors Q18, Q19, Q20, Q21, resistors R13, and R14 form a first current mirror (an improved Wilson current mirror), and transistors Q25, Q26, Q28, Q29, resistors R19, and R20 form a second current mirror, I6=I7=I8=I9.

[0085] The external input differential signal pair VP and VN are the input signals of the first differential pair transistors Q30 and Q31. When VP-VN>0, the differential logic is high level "1", and when VP-VN<0, the differential logic is low level "0";

[0086] Assume that the physical characteristics of transistor Q30 and transistor Q31 are exactly the same;

[0087] Assume that the differential mode signal of the differential pair is Vdiff = VP - VN, and the common mode signal is Vcm = (VP + VN) / 2;

[0088] 1. When M1~M5 are all turned on and I9=0,

[0089] 1.1) Differential mode signal Vdiff < 0, IC1<IC2,V1=VCC-IC1*R22,V2=VCC-IC2*R23,所以V1> V2, V OUT1 >V OUT2 ;

[0090] 1.2) Differential mode signal Vdiff = 0, IC1 = IC2, V1 = V2, V OUT1 =V OUT2 ;

[0091] 1.3) Differential mode signal Vdiff>0, IC1>IC2, V1 <V2,V OUT1 <V OUT2 .

[0092] 2. When at least one of M1 to M5 is turned off and I9>0,

[0093] 2.1) Differential mode signal Vdiff < 0, IC1<IC2,V1> V2, V OUT1 >V OUT2 , making transistor Q36 conductive, V2 = VCC - (I9 + IC2) * R23, V1 is equivalent to the value when I9 = 0, V1 is VCC - IC1 * R22;

[0094] 2.2) When Vdiff gradually increases to Vdiff = 0, IC1 = IC2. From 1), we know that V1>V2, V OUT1 >V OUT2 , the output result remains unchanged;

[0095] 2.3) when Vdiff continues to increase, let V OUT1 OUT2 , V1 = V2, IC1 = I9 + IC2, according to the transistor transmission characteristic formula, VP = VCOM + VT * ln ((IC2 + I9) / IS) at this time, VN = VCOM + VT * ln (IC2 / IS), Vdiff = VP - VN = VT * ln (1 + I9 / IC2), Vdiff at this time can be called Vtrip+, only when Vdiff > Vtrip+, V1 < V2, V OUT1 < V OUT2 , the output result is inverted;

[0096] 2.4) Similarly, Vtrip- can be obtained in the process of Vdiff from large to small. In a completely symmetrical structure, ideally Vtrip+ = |Vtrip-| = Vtrip, the hysteresis interval is (Vtrip+) - (Vtrip-), that is, the hysteresis interval is 2Vtrip.

[0097] 3. Obviously, by changing the size of I9, Vtrip can be changed. The hysteresis comparator structure provided by the application corresponds to different hysteresis intervals with different logic choices (control signals HYST0, HYST1, HYST2 are different). Since the resistor R3, the transistor Q3, the resistor R4 and the transistor Q6 constitute a current source; the resistor R3, the transistor Q3, the resistor R5 and the transistor Q8 constitute a current source; the resistor R3, the transistor Q3, the resistor R9 and the transistor Q10 constitute a current source; the resistor R3, the transistor Q3, the resistor R10 and the transistor Q12 constitute a current source; the resistor R3, the transistor Q3, the resistor R11 and the transistor Q14 constitute a current source, so the application can adjust the resistance values of the resistors R4, R5, R9, R10 and R11, so that I5, I4, I3, I2 and I1 are proportional, wherein the specific values (proportional values) of R4: R5: R9: R10: R11 need to be combined with the IC1 current of the transistor Q30 and the IC2 current of the transistor Q31, and the specific proportional values of R4: R5: R9: R10: R11 can be set according to actual circuit debugging. It can be seen that the application can adjust the resistance values of the resistors R4, R5, R9, R10 and R11 to realize linear increase and decrease of the hysteresis interval;

[0098] ​Wherein, I1 is the current flowing through the triode Q14; I2 is the current flowing through the triode Q12; I3 is the current flowing through the triode Q10; I4 is the current flowing through the triode Q8; I5 is the current flowing through the triode Q6; I6 is the current flowing through the triode Q18; I7 is the current flowing through the triode Q19; I8 is the current flowing through the triode Q28; I9 is the current flowing through the triode Q29; IC1 is the current flowing through the triode Q30; IC2 is the current flowing through the triode Q31; IS is the transistor transmission characteristic constant; V1 is the potential of the node between the resistance R22 and the collector of the triode Q30; V2 is the potential of the node between the resistance R23 and the collector of the triode Q31; VCOM is the potential of the collector position of the triode Q32; VCC is the power supply voltage of the second power module; R22 is the resistance value of the resistance R22; R23 is the resistance value of the resistance R23; V OUT1 is the voltage value of the first voltage signal; V OUT2 is the voltage value of the second voltage signal.

[0099] In this embodiment, according to actual conditions, the specific values (proportional values) of R4: R5: R9: R10: R11 are adjusted in combination with the IC1 current of the triode Q30 and the IC2 current of the triode Q31, so that the hysteresis interval of the hysteresis comparison module 40 can be adjusted to be linearly increasing. The hysteresis interval of the hysteresis comparison module 40 changes according to the three control signals HYST0, HYST1, HYST2 externally input by the switch control module 20, and the case is as shown in Table 2. It is worth noting that, in Table 2, the value of the comparator hysteresis interval linearly increases with the change of the current signal value I6, which is only an example.

[0100] Table 2

[0101]

[0102] In this application, the switch control module outputs multiple intermediate switch signals to the hysteresis amount adjusting module to control the on-off of the currents of multiple branches in the hysteresis amount adjusting module, so as to provide a current signal I6 with adjustable value to the hysteresis comparison module. The greater the value of the current signal I6, the greater the hysteresis voltage interval of the hysteresis comparator, so that the hysteresis voltage interval of the hysteresis comparator can be flexibly adjusted. Further, by adjusting the resistance values of the resistances R4, R5, R9, R10 and R11, the hysteresis interval can be linearly increased or decreased.

[0103] The hysteresis comparator provided in the application is an important electronic element in the field of electronic technology, and plays a key role in signal processing, waveform generation, digital signal conversion and other aspects due to its unique hysteresis characteristic and powerful comparison function, and has been widely used in many fields, including but not limited to: power management field, data conversion field, sensor interface field, communication system field and medical electronic field.

[0104] Obviously, the above embodiments are only examples for clearly illustrating, but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments need not and cannot be exhausted. The obvious changes or variations derived therefrom are still within the protection scope of the application.

Claims

1. A hysteresis comparator, characterized in that: include: Bias voltage providing module, switch control module, hysteresis adjustment module and hysteresis comparison module, wherein, The bias voltage providing module is used to provide bias voltages to multiple branches in the hysteresis adjustment module and to provide bias voltages to multiple branches in the hysteresis comparison module; The switch control module is used to receive multiple control signals input from the outside, and perform internal logic processing according to the multiple control signals to output multiple intermediate switch signals to the hysteresis adjustment module to control the on and off of currents in multiple branches in the hysteresis adjustment module; The hysteresis adjustment module is used to provide a current signal with an adjustable value to the hysteresis comparison module according to the intermediate switch signal; The hysteresis comparison module is used to receive a differential signal input from an external source, perform signal amplification and comparison processing based on the differential signal and the current signal, and output a first voltage signal and a second voltage signal to a subsequent circuit; Wherein, the switch control module includes: first to third control signal input terminals, first to fifth switch signal output terminals, first to third inverters, first to seventh NAND gates, first NOR gates and second NOR gates, the first control signal input terminal is respectively connected to the first terminal of the first NAND gate, the input terminal of the second inverter and the first input terminal of the second NOR gate; the second control signal input terminal is respectively connected to the input terminal of the first inverter, the second input terminal of the second NAND gate, the first input terminal of the first NOR gate and the second input terminal of the second NOR gate; the third control signal input terminal is respectively connected to the input terminal of the third inverter, the second input terminal of the seventh NAND gate, the second input terminal of the first NOR gate and the third input terminal of the second NOR gate; the output terminal of the first inverter is respectively connected to the second input terminal of the first NAND gate and the second input terminal of the fourth NAND gate; the second inverter The output end of the first inverter is connected to the second input end of the third NAND gate; the output end of the first NAND gate is connected to the first end of the fifth NAND gate and the first input end of the sixth NAND gate; the output end of the second NAND gate is connected to the second input end of the fifth NAND gate; the output end of the third NAND gate is connected to the second input end of the sixth NAND gate; the output end of the fourth NAND gate is connected to the first input end of the seventh NAND gate; the output end of the fifth NAND gate is connected to the first switch signal output end, the output end of the sixth NAND gate is connected to the second switch signal output end, the output end of the seventh NAND gate is connected to the fourth switch signal output end, the output end of the first NOR gate is connected to the third switch signal output end, and the output end of the second NOR gate is connected to the fifth switch signal output end.

2. The hysteresis comparator according to claim 1, wherein: The hysteresis comparator also includes: a first power supply module and a second power supply module, wherein the first power supply module is connected to the hysteresis adjustment module to supply power to the hysteresis adjustment module; the second power supply module is connected to the hysteresis comparison module to supply power to the hysteresis comparison module.

3. The hysteresis comparator according to claim 2, wherein: The bias voltage providing module includes: transistor Q1, transistor Q2, transistor Q3, transistor Q4, transistor Q5, transistor Q23, transistor Q24, transistor Q27, resistor R1, resistor R2, resistor R3, resistor R6, resistor R7 and resistor R8, wherein, One end of the resistor R6 is connected to the positive electrode of the second power supply module, and the other end of the resistor R6 is connected to the collector of the transistor Q23, the base of the transistor Q23 is connected to the collector of the transistor Q23, the emitter of the transistor Q23 is connected to the collector of the transistor Q24, the base of the transistor Q24 is connected to the collector of the transistor Q24, the emitter of the transistor Q24 is connected to the collector of the transistor Q27, the base of the transistor Q27 is connected to the collector of the transistor Q27, the emitter of the transistor Q27 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the collector of the transistor Q1, and the The emitter of the transistor Q1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the negative electrode of the second power module, the base of the transistor Q1 is also connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to the collector of the transistor Q5, the emitter of the transistor Q5 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the positive electrode of the first power module, the emitter of the transistor Q2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the negative electrode of the second power module, and the base of the transistor Q2 is also connected to the hysteresis comparator module to provide bias voltage to multiple branches in the hysteresis comparator module; The resistor R7 is connected between the base of the transistor Q5 and the base of the transistor Q3, the emitter of the transistor Q3 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the positive electrode of the first power module, the collector of the transistor Q3 is connected to the base of the transistor Q3, the collector of the transistor Q3 is also connected to the emitter of the transistor Q4, the collector of the transistor Q4 is connected to the negative electrode of the first power module, the base of the transistor Q4 is connected to the series node between the transistor Q5 and the transistor Q2, and the base of the transistor Q3 is also connected to the hysteresis adjustment module to provide bias voltage to multiple branches in the hysteresis adjustment module.

4. The hysteresis comparator according to claim 2, wherein: The hysteresis adjustment module includes: first to fifth branches, wherein: The first branch includes: a resistor R4, a transistor Q6, a transistor Q7, and a first switch unit M5, wherein one end of the resistor R4 is connected to the positive electrode of the first power module, the other end of the resistor R4 is connected to the emitter of the transistor Q6, the collector of the transistor Q6 is connected to the emitter of the transistor Q7, the emitter of the transistor Q7 is also connected to the first end of the first switch unit M5, the second end of the first switch unit M5 is connected to the negative electrode of the first power module, and the third end of the first switch unit M5 is connected to the first output end of the switch control module to receive the first intermediate switch signal of the switch control module; The second branch includes: a resistor R5, a transistor Q8, a transistor Q9, and a second switch unit M4, wherein one end of the resistor R5 is connected to the positive electrode of the first power module, the other end of the resistor R5 is connected to the emitter of the transistor Q8, the collector of the transistor Q8 is connected to the emitter of the transistor Q9, the emitter of the transistor Q9 is further connected to the first end of the second switch unit M4, the second end of the second switch unit M4 is connected to the negative electrode of the first power module, and the third end of the second switch unit M4 is connected to the second output end of the switch control module to receive the second intermediate switch signal of the switch control module; The third branch includes: a resistor R9, a transistor Q10, a transistor Q11, and a third switch unit M3, wherein one end of the resistor R9 is connected to the positive electrode of the first power module, the other end of the resistor R9 is connected to the emitter of the transistor Q10, the collector of the transistor Q10 is connected to the emitter of the transistor Q11, the emitter of the transistor Q11 is also connected to the first end of the third switch unit M3, the second end of the third switch unit M3 is connected to the negative electrode of the first power module, and the third end of the third switch unit M3 is connected to the third output end of the switch control module to receive the third intermediate switch signal of the switch control module; The fourth branch includes: a resistor R10, a transistor Q12, a transistor Q13, and a fourth switch unit M2, wherein one end of the resistor R10 is connected to the positive electrode of the first power module, the other end of the resistor R10 is connected to the emitter of the transistor Q12, the collector of the transistor Q12 is connected to the emitter of the transistor Q13, the emitter of the transistor Q13 is also connected to the first end of the fourth switch unit M2, the second end of the fourth switch unit M2 is connected to the negative electrode of the first power module, and the third end of the fourth switch unit M2 is connected to the fourth output end of the switch control module to receive the fourth intermediate switch signal of the switch control module; The fifth branch includes: a resistor R11, a transistor Q14, a transistor Q15, and a fifth switch unit M1, wherein one end of the resistor R11 is connected to the positive electrode of the first power module, the other end of the resistor R11 is connected to the emitter of the transistor Q14, the collector of the transistor Q14 is connected to the emitter of the transistor Q15, the emitter of the transistor Q15 is also connected to the first end of the fifth switch unit M1, the second end of the fifth switch unit M1 is connected to the negative electrode of the first power module, and the third end of the fifth switch unit M1 is connected to the fifth output end of the switch control module to receive the fifth intermediate switch signal of the switch control module; Among them, the base of the transistor Q15, the base of the transistor Q13, the base of the transistor Q11, the base of the transistor Q9 and the base of the transistor Q7 are all connected to the negative electrode of the first power supply module; the collector of the transistor Q15, the collector of the transistor Q13, the collector of the transistor Q11, the collector of the transistor Q9 and the collector of the transistor Q7 are connected and then connected to the hysteresis comparison module to provide the hysteresis comparison module with a current signal with an adjustable value.

5. The hysteresis comparator according to claim 4, wherein: The first switch unit M5, the second switch unit M4, the third switch unit M3, the fourth switch unit M2 and the fifth switch unit M1 are all NMOS transistors, wherein the first end of the first switch unit M5 is the drain end of the NMOS transistor, the second end of the first switch unit M5 is the source end of the NMOS transistor, and the third end of the first switch unit M5 is the gate end of the NMOS transistor; the first end of the second switch unit M4 is the drain end of the NMOS transistor, the second end of the second switch unit M4 is the source end of the NMOS transistor, and the third end of the second switch unit M4 is the gate end of the NMOS transistor; The first end of the third switch unit M3 is the drain end of the NMOS transistor, the second end of the third switch unit M3 is the source end of the NMOS transistor, and the third end of the third switch unit M3 is the gate end of the NMOS transistor; the first end of the fourth switch unit M2 is the drain end of the NMOS transistor, the second end of the fourth switch unit M2 is the source end of the NMOS transistor, and the third end of the fourth switch unit M2 is the gate end of the NMOS transistor; the first end of the fifth switch unit M1 is the drain end of the NMOS transistor, the second end of the fifth switch unit M1 is the source end of the NMOS transistor, and the third end of the fifth switch unit M1 is the gate end of the NMOS transistor.

6. The hysteresis comparator according to claim 4, wherein: The hysteresis comparison module includes: a resistor R13, a resistor R14, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a transistor Q18, a transistor Q19, a transistor Q20, a transistor Q21, a transistor Q25, a transistor Q26, a transistor Q28, a transistor Q29, a transistor Q30, a transistor Q31, a transistor Q32, a transistor Q33, a transistor Q34, a transistor Q35, a transistor Q36, a transistor Q37 and a transistor Q38, wherein The collector of the transistor Q18 is connected to the collector of the transistor Q15, the base of the transistor Q18 is connected to the collector of the transistor Q18, the emitter of the transistor Q18 is connected to the collector of the transistor Q20, the emitter of the transistor Q20 is connected to one end of the resistor R13, the other end of the resistor R13 is connected to the negative electrode of the second power module, the base of the transistor Q18 is also connected to the base of the transistor Q19, the emitter of the transistor Q19 is connected to the collector of the transistor Q21, the base of the transistor Q21 is respectively connected to the base of the transistor Q20 and the collector of the transistor Q21, the emitter of the transistor Q21 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to the negative electrode of the second power module, and the collector of the transistor Q19 is connected to the collector of the transistor Q25; The base of the transistor Q25 is connected to the collector of the transistor Q25, the emitter of the transistor Q25 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to the positive electrode of the second power module, the base of the transistor Q25 is also connected to the base of the transistor Q26, the emitter of the transistor Q26 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to the positive electrode of the second power module, and the collector of the transistor Q26 is connected to the transistor The collector of the transistor Q28, the emitter of the transistor Q28 is connected to one end of the resistor R19, the other end of the resistor R19 is connected to the negative electrode of the second power module, the resistor R18 is connected between the base of the transistor Q28 and the base of the transistor Q29, the collector of the transistor Q28 is connected to the base of the transistor Q29, the emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module; The emitter of the transistor Q30 is connected to the emitter of the transistor Q31 and then connected to the collector of the transistor Q32. The emitter of the transistor Q32 is connected to one end of the resistor R21, and the other end of the resistor R21 is connected to the negative electrode of the second power module. The collector of the transistor Q30 is connected to one end of the resistor R22, and the other end of the resistor R22 is connected to the positive electrode of the second power module. The collector of the transistor Q31 is connected to one end of the resistor R23, and the other end of the resistor R23 is connected to the positive electrode of the second power module. The base of the transistor Q30 and the base of the transistor Q31 receive a pair of differential signals input from the outside. The collector of the transistor Q30 is also connected to the base of the transistor Q38, the collector of the transistor Q38 is connected to the positive electrode of the second power module, the emitter of the transistor Q38 is connected to the collector of the transistor Q34, the emitter of the transistor Q34 is connected to one end of the resistor R25, and the other end of the resistor R25 is connected to the negative electrode of the second power module; The collector of the transistor Q37 is connected to the positive electrode of the second power module, the emitter of the transistor Q37 is connected to the collector of the transistor Q33, the emitter of the transistor Q33 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the negative electrode of the second power module; The emitter of the transistor Q35 is connected to the emitter of the transistor Q36 and then connected to the collector of the transistor Q29. The emitter of the transistor Q29 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the negative electrode of the second power module. The collector of the transistor Q35 is connected to the collector of the transistor Q30, and the collector of the transistor Q36 is connected to the collector of the transistor Q31. The base of the transistor Q35 is connected to the emitter of the transistor Q37, and the base of the transistor Q36 is connected to the emitter of the transistor Q38. The base of the transistor Q32, the base of the transistor Q33 and the base of the transistor Q34 are all connected to the base of the transistor Q2 to receive the bias voltage provided by the bias voltage providing module; Among them, transistors Q18 to Q21, resistor R13 and resistor R14 constitute a first current mirror; transistors Q25, Q26, Q28, Q29, resistor R19 and resistor R20 constitute a second current mirror; the transistors Q30 and Q31 constitute a first differential pair; and the transistors Q35 and Q36 constitute a second differential pair.

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