Circuit for realizing long-distance transmission based on single-line communication

Abstract

The invention belongs to the field of communication of oil drilling while-drilling instruments, and particularly relates to a circuit for achieving long-distance transmission based on single-line communication. The invention aims to solve the problem that the single-line communication cannot realize long distance, reliable communication and simple circuit when the data transmission mode is adopted between circuits. The circuit comprises a second circuit connected with a first circuit, wherein the first circuit comprises a first differential driving chip, a first buffer module, a first gate module, a first NMOS module and a first PMOS module; the second circuit comprises a second differential driving chip, a second buffer module, a second gate module, a second NMOS module and a second PMOS module. On one hand, the system is excellent in anti-interference performance, suitable for long-distance communication and stable in system performance; and on the other hand, the circuit is simplified, the connection reliability and convenience are high, and great practical significance is achieved.

Description

Technical Field

[0001] The invention belongs to the field of communication of oil drilling while-drilling instruments, and in particular relates to a circuit for realizing long-distance transmission based on single-line communication. Background Art

[0002] The long-distance communication, data reading and testing of the downhole system of the while drilling instrument are composed of a variety of parameter measurement circuits (also known as parameter measurement modules) and a ground data processing system.

[0003] A single-line communication system based on UART can achieve one-to-many connections between the main control circuit of the downhole system and multiple parameter measurement circuits while drilling, but problems such as signal attenuation and noise will occur during long-distance transmission, affecting the accuracy and reliability of data transmission. The data transmission method of differential transmission communication has strong anti-interference ability and long transmission distance, but it cannot achieve single-line transmission because it occupies many lines.

[0004] What kind of data transmission method should be used between the ground data processing system of the downhole system of the drilling instrument and the various parameter measurement circuits to enable single-line communication to achieve long distances while ensuring reliable communication and simple circuits has become one of the technical problems that need to be urgently solved in the existing technology.

[0005] Based on this, the present invention provides a circuit for realizing long-distance transmission based on single-line communication. Summary of the invention

[0006] In order to solve the above-mentioned problem in the prior art, that is, no matter what data transmission method is adopted between the ground data processing system of the downhole system of the drilling instrument and the various parameter measurement circuits, single-line communication cannot achieve long-distance transmission while ensuring reliable communication and simple circuits, the present invention provides a circuit based on single-line communication to achieve long-distance transmission.

[0007] The present invention provides a circuit for realizing long-distance transmission based on single-line communication, comprising a first circuit and a second circuit, wherein a first port of the first circuit is connected to a first device, the first device is a downhole system of a while-drilling measurement instrument, a second port of the first circuit is connected to a first port of the second circuit, and a second port of the second circuit is connected to a second device, the second device is a ground data processing system;

[0008] The first circuit includes a first differential driver chip, a first buffer module, a first gate module, a first NMOS module and a first PMOS module;

[0009] The first end of the first differential driver chip is connected to the first end of the first gate module, the second end of the first gate module is connected to the first end of the first buffer module, the second end of the first buffer module is connected to the first end of the first NMOS module and the first end of the first PMOS module, and the second end of the first NMOS module is connected to the second end of the first PMOS module and then connected to the first port of the first circuit;

[0010] The second circuit includes a second differential driver chip, a second buffer module, a second gate module, a second NMOS module and a second PMOS module;

[0011] The first end of the second differential driving chip is connected to the first end of the second gate module, the second end of the second differential driving chip is connected to the second end of the first differential driving chip, the second end of the second gate module is connected to the first end of the second buffer module, the second end of the second buffer module is connected to the first end of the second NMOS module and the first end of the second PMOS module, and the second end of the second NMOS module is connected to the second end of the first PMOS module and then connected to the second port of the second circuit.

[0012] In some preferred embodiments, the first differential driver chip and the second differential driver chip both include an RO pin, a RE# pin, a DE pin, a DI pin, a GND1 pin, an A1 pin, a B1 pin, and a VCC1 pin;

[0013] The RO pin and the DI pin of the first differential driver chip are respectively connected to the first gate module; the B1 pin of the first differential driver chip is connected to the B1 pin of the second differential driver chip, and the A1 pin of the first differential driver chip is connected to the A1 pin of the second differential driver chip; the GND1 pin of the first differential driver chip is connected to the ground wire; the VCC1 pin of the first differential driver chip is connected to the power supply;

[0014] The RO pin and the DI pin of the second differential driver chip are respectively connected to the second gate module; the RE# pin of the first differential driver chip and the second differential driver chip are connected to the ground wire; the DE pin is connected to the power supply; the GND1 pin of the second differential driver chip is connected to the ground wire; and the VCC1 pin of the second differential driver chip is connected to the power supply.

[0015] In some preferred embodiments, the first gate module includes a first gate circuit, a second gate circuit, a first resistor, and a third resistor; the second gate module includes a third gate circuit, a fifth resistor, a fourth gate circuit, and a second resistor;

[0016] The first gate circuit, the second gate circuit, the third gate circuit, and the fourth gate circuit all include an A2 pin, a B2 pin, a GND2 pin, a Y pin, and a VCC2 pin;

[0017] The A2 pin of the first gate circuit and the B2 pin of the first gate circuit are both connected to the RO pin of the first differential driving chip, the GND2 pin of the first gate circuit is connected to the ground line, the Y pin of the first gate circuit is connected to one end of the third resistor, the other end of the third resistor is connected to the power supply, and the VCC2 pin of the first gate circuit is connected to the power supply;

[0018] The A2 pin of the second gate circuit and the B2 pin of the second gate circuit are both connected to one end of the first resistor, the other end of the first resistor is connected to a power supply, the GND2 pin of the second gate circuit is connected to a ground line, the Y pin of the second gate circuit is connected to the DI pin of the first differential driver chip, and the VCC2 pin of the second gate circuit is connected to a power supply;

[0019] The A2 pin of the third gate circuit and the B2 pin of the third gate circuit are both connected to the RO pin of the second differential driving chip, the GND2 pin of the third gate circuit is connected to the ground wire, the Y pin of the third gate circuit is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the power supply, and the VCC2 pin of the third gate circuit is connected to the power supply;

[0020] The A2 pin of the fourth gate circuit and the B2 pin of the fourth gate circuit are both connected to one end of the second resistor, the other end of the second resistor is connected to the power supply, the GND2 pin of the fourth gate circuit is connected to the ground wire, the Y pin of the fourth gate circuit is connected to the DI pin of the second differential drive chip, and the VCC2 pin of the fourth gate circuit is connected to the power supply.

[0021] In some preferred embodiments, the first buffer module includes a first buffer and a fourth resistor; the second buffer module includes a second buffer and a sixth resistor;

[0022] The first buffer and the second buffer each include a 1OE# pin, a 1A pin, a 2Y pin, a GND3 pin, a 2A pin, a 1Y pin, a 2OE# pin, and a VCC3 pin;

[0023] The 1OE# pin of the first buffer is connected to the Y pin of the first gate circuit and one end of the third resistor respectively, and the other end of the third resistor is connected to the other end of the first resistor and the VCC3 pin of the first buffer respectively; the 1A pin of the first buffer is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground line; the 2Y pin of the first buffer is connected to one end of the first resistor, the GND3 pin of the first buffer is connected to the other end of the fourth resistor, and the 2OE# pin of the first buffer is connected to the ground line; the 1Y pin of the first buffer is connected to the first NMOS module, and the 2A pin of the first buffer is connected to the first PMOS module;

[0024] The 1OE# pin of the second buffer is respectively connected to the Y pin of the third gate circuit and one end of the fifth resistor, the other end of the fifth resistor is respectively connected to the other end of the second resistor and the VCC3 pin of the second buffer, the 1A pin of the second buffer is connected through one end of the sixth resistor, and the other end of the sixth resistor is connected to the ground line; the 2Y pin of the second buffer is connected to one end of the second resistor; the GND3 pin of the second buffer is connected to the other end of the sixth resistor; the 2OE# pin of the second buffer is connected to the ground line; the 1Y pin of the second buffer is connected to the second NMOS module, and the 2A pin of the second buffer is connected to the second PMOS module.

[0025] In some preferred embodiments, the first NMOS module includes a seventh resistor and a first NMOS tube; the second NMOS module includes an eighth resistor and a second NMOS tube;

[0026] The 1Y pin of the first buffer is connected to the seventh resistor, the seventh resistor is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to the power supply, and the source of the first NMOS tube is connected to the first port;

[0027] The 1Y pin of the second buffer is connected to the eighth resistor, the eighth resistor is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is connected to the power supply, and the source of the second NMOS tube is connected to the second port.

[0028] In some preferred embodiments, the first PMOS module includes a ninth resistor, a tenth resistor, an eleventh resistor, a first capacitor, and a first PMOS tube;

[0029] The second PMOS module includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second capacitor, and a second PMOS tube;

[0030] The 2A pin of the first buffer is connected in series with the ninth resistor and the tenth resistor and then connected in parallel with the first capacitor, the first capacitor is connected to the ground line, the ninth resistor and the tenth resistor are connected in series with the drain of the first PMOS tube, the source of the first PMOS tube is connected in series with one end of the eleventh resistor, the other end of the eleventh resistor is connected to the gate of the first PMOS tube, and the other end of the eleventh resistor is connected to the ground line;

[0031] The 2A pin of the second buffer is connected in series with the twelfth resistor and the thirteenth resistor and then connected in parallel with the second capacitor, the second capacitor is connected to the ground line, the twelfth resistor and the thirteenth resistor are connected in series with the drain of the second PMOS tube, the source of the second PMOS tube is connected in series with one end of the fourteenth resistor, the other end of the fourteenth resistor is connected to the gate of the second PMOS tube, and the other end of the fourteenth resistor is connected to the ground line.

[0032] Beneficial effects of the present invention:

[0033] This design is applied to the communication end of the downhole system of the measurement while drilling instrument and the ground data processing system. On the one hand, it has excellent anti-interference performance, is suitable for long-distance communication, and has stable system performance; on the other hand, it streamlines the lines, has high connection reliability and convenience, and has great practical significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0035] Figure 1 It is a schematic diagram of the connection between the circuit and the device of the present invention;

[0036] Figure 2 is a schematic diagram of a first differential driving chip of the present invention;

[0037] Figure 3 is a schematic diagram of a first door module of the present invention;

[0038] Figure 4 is a schematic diagram of a first buffer module of the present invention;

[0039] Figure 5 is a schematic diagram of a first NMOS module of the present invention;

[0040] Figure 6 is a schematic diagram of a first PMOS module of the present invention;

[0041] Figure 7 is a schematic diagram of the overall connection of the first circuit of the present invention;

[0042] Figure 8 is a schematic diagram of a second differential driving chip of the present invention;

[0043] Fig. 9 is a schematic diagram of a second door module of the present invention;

[0044] Fig.10 is a schematic diagram of a second buffer module of the present invention;

[0045] Fig.11 is a schematic diagram of a second NMOS module of the present invention;

[0046] Fig.12 is a schematic diagram of a second PMOS module of the present invention;

[0047] Fig.13 It is a schematic diagram of the overall connection of the second circuit of the present invention. DETAILED DESCRIPTION

[0048] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0049] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] like Figure 1-13 As shown, see Figure 1 , Figure 7 , Fig.13 The present invention provides a circuit for realizing long-distance transmission based on single-line communication, comprising a first circuit and a second circuit, wherein a first port of the first circuit is connected to a first device, the first device is a downhole system of a measurement while drilling instrument, a second port of the first circuit is connected to a first port of the second circuit, and a second port of the second circuit is connected to a second device, the second device is a ground data processing system;

[0051] The first circuit includes a first differential driving chip U8, a first buffer module, a first gate module, a first NMOS module and a first PMOS module;

[0052] The first end of the first differential driving chip U8 is connected to the first end of the first gate module, the second end of the first gate module is connected to the first end of the first buffer module, the second end of the first buffer module is connected to the first end of the first NMOS module and the first end of the first PMOS module, and the second end of the first NMOS module is connected to the second end of the first PMOS module and then connected to the first port of the first circuit;

[0053] The second circuit includes a second differential driving chip U13, a second buffer module, a second gate module, a second NMOS module and a second PMOS module;

[0054] The first end of the second differential driver chip U13 is connected to the first end of the second gate module, the second end of the second differential driver chip U13 is connected to the second end of the first differential driver chip U8, the second end of the second gate module is connected to the first end of the second buffer module, the second end of the second buffer module is connected to the first end of the second NMOS module and the first end of the second PMOS module, and the second end of the second NMOS module is connected to the second end of the first PMOS module and then connected to the second port of the second circuit.

[0055] In this embodiment, the first device is a master device, and the second device is a slave device. The master device may be a downhole system of a measurement while drilling instrument, such as Figure 7 In the LWD shown in , the slave device is a ground data processing system, such as Fig.13 In the INTERFACEBOX shown in the figure, each device is set with a unique address. The master device sends a data request command, and the first circuit uses a differential drive transmission method to improve the signal's anti-interference ability. After transmission through a long-distance transmission line, the second circuit reliably sends the data request command to the slave device. After receiving the command, the slave device returns the corresponding data to the master device in the same way as required.

[0056] Preferably, see Figure 2 , Figure 8 , the first differential driver chip U8 and the second differential driver chip U13 both include a RO pin, a RE# pin, a DE pin, a DI pin, a GND1 pin, an A1 pin, a B1 pin, and a VCC1 pin;

[0057] The RO pin and the DI pin of the first differential driver chip U8 are respectively connected to the first gate module; the B1 pin of the first differential driver chip U8 is connected to the B1 pin of the second differential driver chip U13, and the A1 pin of the first differential driver chip U8 is connected to the A1 pin of the second differential driver chip U13; the GND1 pin of the first differential driver chip U8 is connected to the ground wire; the VCC1 pin of the first differential driver chip U8 is connected to the power supply;

[0058] The RO pin and the DI pin of the second differential driver chip U13 are respectively connected to the third gate circuit U11; the RE# pin of the first differential driver chip U8 and the second differential driver chip U13 are connected to the ground line; the DE pin is connected to the power supply; the GND1 pin of the second differential driver chip U13 is connected to the ground line; the VCC1 pin of the second differential driver chip U13 is connected to the power supply.

[0059] Among them, the basic circuit diagram of the communication circuit is introduced as follows:

[0060] U8 and U13 are differential driver chips, and the specific chip model used may be SP485. SP485 is a communication-specific chip based on the differential signal transmission principle. The names and functions of its pins are as follows:

[0061] RO pin functions as data output terminal; RE# pin functions as data output enable control terminal; DE pin functions as data input enable control terminal; DI pin functions as data input terminal; GND1 pin functions as power ground pin; A1 pin functions as differential positive output terminal; B1 pin functions as differential negative output terminal; VCC1 pin functions as working power supply pin.

[0062] Preferably, see Figure 3 , Fig. 9 , the first gate module includes a first gate circuit U6, a second gate circuit U9, a first resistor R21, and a third resistor R20; the second gate module includes a third gate circuit U11, a fifth resistor R26, a fourth gate circuit U12, and a second resistor R27;

[0063] The first gate circuit U6, the second gate circuit U9, the third gate circuit U11, and the fourth gate circuit U12 all include an A2 pin, a B2 pin, a GND2 pin, a Y pin, and a VCC2 pin;

[0064] The A2 pin of the first gate circuit U6 and the B2 pin of the first gate circuit U6 are both connected to the RO pin of the first differential driving chip U8, the GND2 pin of the first gate circuit U6 is connected to the ground line, the Y pin of the first gate circuit U6 is connected to one end of the third resistor R20, the other end of the third resistor R20 is connected to the power supply, and the VCC2 pin of the first gate circuit U6 is connected to the power supply;

[0065] The A2 pin of the second gate circuit U9 and the B2 pin of the second gate circuit U9 are both connected to one end of the first resistor R21, the other end of the first resistor R21 is connected to the power supply, the GND2 pin of the second gate circuit U9 is connected to the ground line, the Y pin of the second gate circuit U9 is connected to the DI pin of the first differential driving chip U8, and the VCC2 pin of the second gate circuit U9 is connected to the power supply;

[0066] The A2 pin of the third gate circuit U11 and the B2 pin of the third gate circuit U11 are both connected to the RO pin of the second differential driving chip U13, the GND2 pin of the third gate circuit U11 is connected to the ground line, the Y pin of the third gate circuit U11 is connected to one end of the fifth resistor R26, the other end of the fifth resistor R26 is connected to the power supply, and the VCC2 pin of the third gate circuit U11 is connected to the power supply;

[0067] The A2 pin of the fourth gate circuit U12 and the B2 pin of the fourth gate circuit U12 are both connected to one end of the second resistor R27, the other end of the second resistor R27 is connected to the power supply, the GND2 pin of the fourth gate circuit U12 is connected to the ground line, the Y pin of the fourth gate circuit U12 is connected to the DI pin of the second differential drive chip U13, and the VCC2 pin of the fourth gate circuit U12 is connected to the power supply.

[0068] Among them, U6, U9, U11, and U12 are gate circuits. The specific chip model used may be SN74LVC1G00. SN74LVC1G00 is a general logic gate chip with SOT-23-5 package. The names and functions of its pins are as follows:

[0069] The A2 pin functions as a data input terminal; the B2 pin functions as a data input terminal; the GND2 pin functions as a power ground pin; the Y pin functions as a data inverting output terminal; and the VCC2 pin functions as a working power supply pin.

[0070] Preferably, see Figure 4 , Fig.10 , the first buffer module includes a first buffer U3 and a fourth resistor R13; the second buffer module includes a second buffer U10 and a sixth resistor R28;

[0071] The first buffer U3 and the second buffer U10 both include a 1OE# pin, a 1A pin, a 2Y pin, a GND3 pin, a 2A pin, a 1Y pin, a 2OE# pin, and a VCC3 pin;

[0072] The 1OE# pin of the first buffer U3 is connected to the Y pin of the first gate circuit U6 and one end of the third resistor R20 respectively, and the other end of the third resistor R20 is connected to the other end of the first resistor R21 and the VCC3 pin of the first buffer U3 respectively; the 1A pin of the first buffer U3 is connected to one end of the fourth resistor R13, and the other end of the fourth resistor R13 is connected to the ground line; the 2Y pin of the first buffer U3 is connected to one end of the first resistor R21, the GND3 pin of the first buffer U3 is connected to the other end of the fourth resistor R13, and the 2OE# pin of the first buffer U3 is connected to the ground line; the 1Y pin of the first buffer U3 is connected to the first NMOS module, and the 2A pin of the first buffer U3 is connected to the first PMOS module;

[0073] The 1OE# pin of the second buffer U10 is respectively connected to the Y pin of the third gate circuit U11 and one end of the fifth resistor R26, the other end of the fifth resistor R26 is respectively connected to the other end of the second resistor R27 and the VCC3 pin of the second buffer U10, the 1A pin of the second buffer U10 is connected through one end of the sixth resistor R28, the other end of the sixth resistor R28 is connected to the ground line; the 2Y pin of the second buffer U10 is connected to one end of the second resistor R27; the GND3 pin of the second buffer U10 is connected to the other end of the sixth resistor R28; the 2OE# pin of the second buffer U10 is connected to the ground line; the 1Y pin of the second buffer U10 is connected to the second NMOS module, and the 2A pin of the second buffer U10 is connected to the second PMOS module.

[0074] Among them, U3 and U10 are buffers. The specific chip model used may be SN74LVC2G240. SN74LVC2G240 is a dual three-state output buffer driver, VSSOP package, with the characteristics of small size, low power consumption, and good temperature resistance. It is specially designed to improve the performance of three-state storage address drive, clock drive and bus-oriented receivers and transmitters. The names and functions of its pins are as follows:

[0075] 1OE# pin, functions as channel 1 enable control terminal; 1A pin, functions as channel 1 input terminal; 2Y pin, functions as channel 2 reverse output terminal; GND pin, functions as power ground pin; 2A pin, functions as channel 2 input terminal; 1Y pin, functions as channel 1 reverse output terminal; 2OE# pin, functions as channel 2 enable control terminal; VCC3 pin, functions as working power pin.

[0076] Preferably, see Figure 5 , Fig.10, the first NMOS module includes a seventh resistor R18 and a first NMOS tube Q4; the second NMOS module includes an eighth resistor R24 ​​and a second NMOS tube Q7;

[0077] The 1Y pin of the first buffer U3 is connected to the seventh resistor R18, the seventh resistor R18 is connected to the drain of the first NMOS transistor Q4, the gate of the first NMOS transistor Q4 is connected to the power supply, and the source of the first NMOS transistor Q4 is connected to the first port;

[0078] The 1Y pin of the second buffer U10 is connected to the eighth resistor R24, the eighth resistor R24 ​​is connected to the drain of the second NMOS transistor Q7, the gate of the second NMOS transistor Q7 is connected to the power supply, and the source of the second NMOS transistor Q7 is connected to the second port.

[0079] Preferably, see Figure 6 , Fig.12 , the first PMOS module includes a ninth resistor R19, a tenth resistor R14, an eleventh resistor R17, a first capacitor C3, and a first PMOS tube Q5;

[0080] The second PMOS module includes a twelfth resistor R25, a thirteenth resistor R22, a fourteenth resistor R23, a second capacitor C4, and a second PMOS tube Q6;

[0081] The 2A pin of the first buffer U3 is connected in series with the ninth resistor R19 and the tenth resistor R14 and then connected in parallel with the first capacitor C3, the first capacitor C3 is connected to the ground line, the ninth resistor R19 and the tenth resistor R14 are connected in series with the drain of the first PMOS transistor Q5, the source of the first PMOS transistor Q5 is connected in series with one end of the eleventh resistor R17, the other end of the eleventh resistor R17 is connected to the gate of the first PMOS transistor Q5, and the other end of the eleventh resistor R17 is connected to the ground line;

[0082] The 2A pin of the second buffer U10 is connected in series with the twelfth resistor R25 and the thirteenth resistor R22 and then connected in parallel with the second capacitor C4, the second capacitor C4 is connected to the ground line, the twelfth resistor R25 and the thirteenth resistor R22 are connected in series with the drain of the second PMOS tube Q6, the source of the second PMOS tube Q6 is connected in series with one end of the fourteenth resistor R23, the other end of the fourteenth resistor R23 is connected to the gate of the second PMOS tube Q6, and the other end of the fourteenth resistor R23 is connected to the ground line.

[0083] Among them, Q4 and Q7 are N-channel MOS tubes, referred to as NMOS tubes, and Q5 and Q6 are P-channel MOS tubes, referred to as PMOS tubes; the characteristic of the NMOS tube is that it will be turned on when Vgs is greater than a certain value, and it is suitable for the situation when the source is connected to GND (low-end drive); the characteristic of the PMOS tube is that it will be turned on when Vgs is less than a certain value, and it is suitable for the situation when the source is connected to the power supply (high-end drive).

[0084] C3 and C4 are capacitors used to remove high-frequency interference signals.

[0085] See also Figure 7 , Fig.13 , the schematic diagram of long-distance transmission based on single-line communication is as follows Figure 1 As shown, the first device sends a data request command to the second device, and the data request command improves the anti-interference ability of the signal through the first communication circuit. Figure 7 The 1OE# pin of the first buffer U3 in the corresponding first circuit is always high, and the 2OE# pin is always low. The data request command is input through the 2A pin at a high level, and the 2Y pin is inverted to output a low level to U9; the Y pin of U9 is inverted to output a high level to the transmitter input DI pin of the differential driver chip U8, and the A1 and B1 pins of U8 are respectively output at high and low levels, and are transmitted to the long-distance transmission line. Fig.13 The A2 and B2 pins of the driver chip U13 of the second circuit shown in the figure; the receiver output RO pin of U13 outputs a high level to the gate circuit U11, and the Y pin of U11 inverts and outputs a low level to the 1OE# pin of the buffer U10; the 1Y pin of U10 is always at a low level, and the 1Y pin inverts and outputs a high level, sending the data request command to the second device. After receiving the command, the second device responds to the first device in the same way through U10, U12, U13 in the second circuit, and U8, U6, U3 in the first circuit. The sending and receiving of the command is completed.

[0086] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0087] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0088] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A circuit for realizing long-distance transmission based on single-line communication, characterized in that: The device comprises a first circuit and a second circuit, wherein a first port of the first circuit is connected to a first device, which is a downhole system of a measurement while drilling instrument, a second port of the first circuit is connected to a first port of a second circuit, and a second port of the second circuit is connected to a second device, which is a ground data processing system; The first circuit includes a first differential driver chip, a first buffer module, a first gate module, a first NMOS module and a first PMOS module; The first end of the first differential driver chip is connected to the first end of the first gate module, the second end of the first gate module is connected to the first end of the first buffer module, the second end of the first buffer module is connected to the first end of the first NMOS module and the first end of the first PMOS module, and the second end of the first NMOS module is connected to the second end of the first PMOS module and then connected to the first port of the first circuit; The second circuit includes a second differential driver chip, a second buffer module, a second gate module, a second NMOS module and a second PMOS module; The first end of the second differential driving chip is connected to the first end of the second gate module, the second end of the second differential driving chip is connected to the second end of the first differential driving chip, the second end of the second gate module is connected to the first end of the second buffer module, the second end of the second buffer module is connected to the first end of the second NMOS module and the first end of the second PMOS module, and the second end of the second NMOS module is connected to the second end of the first PMOS module and then connected to the second port of the second circuit.

2. A circuit for realizing long-distance transmission based on single-line communication according to claim 1, characterized in that: The first differential driver chip and the second differential driver chip both include an RO pin, a RE# pin, a DE pin, a DI pin, a GND1 pin, an A1 pin, a B1 pin, and a VCC1 pin; The RO pin and the DI pin of the first differential driver chip are respectively connected to the first gate module; the B1 pin of the first differential driver chip is connected to the B1 pin of the second differential driver chip, and the A1 pin of the first differential driver chip is connected to the A1 pin of the second differential driver chip; the GND1 pin of the first differential driver chip is connected to the ground wire; the VCC1 pin of the first differential driver chip is connected to the power supply; The RO pin and the DI pin of the second differential driver chip are respectively connected to the second gate module; the RE# pin of the first differential driver chip and the second differential driver chip are connected to the ground wire; the DE pin is connected to the power supply; the GND1 pin of the second differential driver chip is connected to the ground wire; and the VCC1 pin of the second differential driver chip is connected to the power supply.

3. A circuit for realizing long-distance transmission based on single-line communication according to claim 1, characterized in that: The first gate module includes a first gate circuit, a second gate circuit, a first resistor, and a third resistor; the second gate module includes a third gate circuit, a fifth resistor, a fourth gate circuit, and a second resistor; The first gate circuit, the second gate circuit, the third gate circuit, and the fourth gate circuit all include an A2 pin, a B2 pin, a GND2 pin, a Y pin, and a VCC2 pin; The A2 pin of the first gate circuit and the B2 pin of the first gate circuit are both connected to the RO pin of the first differential driving chip, the GND2 pin of the first gate circuit is connected to the ground line, the Y pin of the first gate circuit is connected to one end of the third resistor, the other end of the third resistor is connected to the power supply, and the VCC2 pin of the first gate circuit is connected to the power supply; The A2 pin of the second gate circuit and the B2 pin of the second gate circuit are both connected to one end of the first resistor, the other end of the first resistor is connected to a power supply, the GND2 pin of the second gate circuit is connected to a ground line, the Y pin of the second gate circuit is connected to the DI pin of the first differential driver chip, and the VCC2 pin of the second gate circuit is connected to a power supply; The A2 pin of the third gate circuit and the B2 pin of the third gate circuit are both connected to the RO pin of the second differential driving chip, the GND2 pin of the third gate circuit is connected to the ground wire, the Y pin of the third gate circuit is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the power supply, and the VCC2 pin of the third gate circuit is connected to the power supply; The A2 pin of the fourth gate circuit and the B2 pin of the fourth gate circuit are both connected to one end of the second resistor, the other end of the second resistor is connected to the power supply, the GND2 pin of the fourth gate circuit is connected to the ground wire, the Y pin of the fourth gate circuit is connected to the DI pin of the second differential drive chip, and the VCC2 pin of the fourth gate circuit is connected to the power supply.

4. A circuit for realizing long-distance transmission based on single-line communication according to claim 1, characterized in that: The first buffer module includes a first buffer and a fourth resistor; the second buffer module includes a second buffer and a sixth resistor; The first buffer and the second buffer each include a 1OE# pin, a 1A pin, a 2Y pin, a GND3 pin, a 2A pin, a 1Y pin, a 2OE# pin, and a VCC3 pin; The 1OE# pin of the first buffer is connected to the Y pin of the first gate circuit and one end of the third resistor respectively, and the other end of the third resistor is connected to the other end of the first resistor and the VCC3 pin of the first buffer respectively; the 1A pin of the first buffer is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground line; the 2Y pin of the first buffer is connected to one end of the first resistor, the GND3 pin of the first buffer is connected to the other end of the fourth resistor, and the 2OE# pin of the first buffer is connected to the ground line; the 1Y pin of the first buffer is connected to the first NMOS module, and the 2A pin of the first buffer is connected to the first PMOS module; The 1OE# pin of the second buffer is respectively connected to the Y pin of the third gate circuit and one end of the fifth resistor, the other end of the fifth resistor is respectively connected to the other end of the second resistor and the VCC3 pin of the second buffer, the 1A pin of the second buffer is connected through one end of the sixth resistor, and the other end of the sixth resistor is connected to the ground line; the 2Y pin of the second buffer is connected to one end of the second resistor; the GND3 pin of the second buffer is connected to the other end of the sixth resistor; the 2OE# pin of the second buffer is connected to the ground line; the 1Y pin of the second buffer is connected to the second NMOS module, and the 2A pin of the second buffer is connected to the second PMOS module.

5. A circuit for realizing long-distance transmission based on single-line communication according to claim 4, characterized in that: The first NMOS module includes a seventh resistor and a first NMOS tube; the second NMOS module includes an eighth resistor and a second NMOS tube; The 1Y pin of the first buffer is connected to the seventh resistor, the seventh resistor is connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to the power supply, and the source of the first NMOS tube is connected to the first port; The 1Y pin of the second buffer is connected to the eighth resistor, the eighth resistor is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is connected to the power supply, and the source of the second NMOS tube is connected to the second port.

6. A circuit for realizing long-distance transmission based on single-line communication according to claim 5, characterized in that: The first PMOS module includes a ninth resistor, a tenth resistor, an eleventh resistor, a first capacitor, and a first PMOS tube; The second PMOS module includes a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second capacitor, and a second PMOS tube; The 2A pin of the first buffer is connected in series with the ninth resistor and the tenth resistor and then connected in parallel with the first capacitor, the first capacitor is connected to the ground line, the ninth resistor and the tenth resistor are connected in series with the drain of the first PMOS tube, the source of the first PMOS tube is connected in series with one end of the eleventh resistor, the other end of the eleventh resistor is connected to the gate of the first PMOS tube, and the other end of the eleventh resistor is connected to the ground line; The 2A pin of the second buffer is connected in series with the twelfth resistor and the thirteenth resistor and then connected in parallel with the second capacitor, the second capacitor is connected to the ground line, the twelfth resistor and the thirteenth resistor are connected in series with the drain of the second PMOS tube, the source of the second PMOS tube is connected in series with one end of the fourteenth resistor, the other end of the fourteenth resistor is connected to the gate of the second PMOS tube, and the other end of the fourteenth resistor is connected to the ground line.

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