Delay locked loop and semiconductor memory device

Abstract

The invention provides a delay lock loop and a semiconductor memory device. The delay lock loop can complete a program for adjusting the delay of an internal clock signal in a predetermined execution period. The delay lock loop includes a DLL control circuit and a delay line circuit. The DLL control circuit sets a delay amount according to a phase difference between the input clock signal and the output clock signal. The delay line circuit performs a delay action on an input clock pulse signal according to the delay amount so as to generate an output clock pulse signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay device, and the number of the delay devices included in one of the delay units is greater than the number of the delay devices included in the other of the delay units.

Description

Technical Field

[0001] The present application relates to a delay locked loop and a semiconductor memory device. Background Art

[0002] DRAM (Dynamic Random Access Memory) is a semiconductor memory device that stores information by storing charge in a capacitor. When there is no power supply, the stored information disappears. In existing DRAMs, such as Japanese Patent Publication No. 2015-35241, a delay locked loop (DLL) is provided. The DLL can generate an internal clock signal in DRAM that is synchronized with an external clock signal and is used to output a data signal.

[0003] In existing DRAM, when a DLL is used to adjust the delay of an internal clock signal, for example, the DLL program will perform the following actions: a DLL reset action, a DLL delay (lock) action (for example, activating delay lines one by one at the same time and synchronizing the external clock and the internal clock), and an action of detecting the N value representing the number of delayed clock cycles between an input clock signal generated according to an external clock signal and an internal clock signal.

[0004] The lock time Td11 caused by the delayed action of the DLL can be expressed by the following formula:

[0005] Tint+Td11=N×tCK

[0006] Wherein, Tint represents the inherent delay time of the DLL, and tCK represents the clock cycle. For example, when the clock cycle tCK is longer than the inherent delay time Tint due to factors such as the temperature in the semiconductor memory device, as shown in the above formula, the lock time Td11 caused by the delayed action of the DLL will be extended. When the lock time Td11 is extended, the total execution time of the above DLL program will be extended, which may delay the execution of the next DLL program and may exceed the pre-set execution period tDLLK of the DLL program. Summary of the invention

[0007] In view of the above problems, an object of the present application is to provide a delay locked loop and a semiconductor memory device, which can suppress the extension of the delay action and complete the DLL program for adjusting the delay of the internal clock signal within a predetermined execution period.

[0008] The delay locked loop of the present application includes a DLL control circuit, which sets the delay amount according to the phase difference between the input clock signal and the output clock signal; and a delay line circuit, which receives the input clock signal and is configured to perform a delay action on the input clock signal according to the delay amount to generate an output clock signal; wherein the delay line circuit includes a plurality of delay units, each delay unit includes at least one delay device, and the number of delay devices included in one of the delay units is greater than the number of delay devices included in another of the delay units.

[0009] The semiconductor memory device of the present application includes the aforementioned delay locked loop and an output buffer. The output buffer receives an output clock signal and controls the output of data according to the output clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 4 is a block diagram of a structure example of a delay locked loop according to an embodiment of the present application.

[0011] Figure 2 This is a block diagram of the delay line circuit.

[0012] Figure 3 FIG. 4 is a schematic diagram showing the relationship between the number of delay units and NAND gates in a delay line circuit according to an embodiment of the present application.

[0013] Figure 4A and Figure 4B Schematic diagram of the number of NAND gates required for the corresponding delay amount.

[0014] Figure 5A and Figure 5B Schematic diagram of the locking time required for the corresponding delay amount.

[0015] Figure 6 This is a structural diagram of other delay line circuits.

[0016] Explanation of symbols

[0017] 1: Delay locked loop

[0018] 11: Input buffer

[0019] 12: Phase detection circuit

[0020] 13: DLL control circuit

[0021] 14: Delay Line Circuit

[0022] 15: Copy Circuit

[0023] 16: Output buffer

[0024] 21: Multiplexer

[0025] 22, 32: NAND gate row

[0026] 33: First NAND sub-gate row

[0027] 34: Second NAND sub-gate row

[0028] CK: external clock signal

[0029] N1~N24:NAND gate

[0030] NA, NB, NC: NAND gate

[0031] U1~U10:Delay unit

[0032] E1~E12:Delay device

[0033] clk: input clock signal

[0034] dll_clk: delay signal (output clock signal)

[0035] dll_code: control signal

[0036] fb_clk: feedback signal

[0037] SEL: Select control signal

[0038] unit_1~unit_10:unit signal

[0039] up / down: phase signal

[0040] <1> ~ <10> : Code signal DETAILED DESCRIPTION

[0041] The delay locked loop and semiconductor memory device of the embodiments of the present application are described in detail below with reference to the accompanying drawings. These embodiments are only examples and are not intended to limit the present application. In the following embodiments, the semiconductor memory device is, for example, a DRAM.

[0042] Figure 1 A semiconductor memory device and a delay locked loop 1 thereof according to an embodiment of the present application are shown. To simplify the description, only the output buffer 16 of the semiconductor memory device is shown, and other known structures (e.g., a command decoder, a memory cell array, an input / output interface, etc.) provided in the semiconductor memory device are not shown in this example.

[0043] The delay locked loop 1 includes an input buffer 11 , a phase detection circuit 12 , a DLL control circuit 13 , a delay line circuit 14 and a replica circuit 15 .

[0044] The input buffer 11 is configured to buffer the received external clock signal CK to generate an input clock signal clk. The input clock signal clk generated by the input buffer 11 will be provided to the delay line circuit 14 and the phase detection circuit 12. The delay line circuit 14 is configured to delay the input clock signal clk to generate a delayed signal (hereinafter also referred to as the output clock signal) dll_clk, and provide the delayed signal dll_clk to the output buffer 16 and the replica circuit 15. The replica circuit 15 is configured to generate a feedback signal fb_clk according to the delayed signal dll_clk, and output the feedback signal fb_clk to the phase detection circuit 12.

[0045] The phase detection circuit 12 receives the input clock signal clk and the feedback signal fb_clk, and is configured to detect the phase difference between the input clock signal clk and the feedback signal fb_clk to generate a phase signal up / down. The phase detection circuit 12 provides the phase signal up / down to the DLL control circuit 13. The phase signal up / down indicates whether the phase of the feedback signal fb_clk is ahead or behind the phase of the input clock signal clk.

[0046] The DLL control circuit 13 is configured to determine the delay amount according to the phase signal up / down to generate a control signal dll_code composed of multiple bits and a selection control signal SEL as a signal for indicating the delay amount in the locking operation (an example of the "delay operation" of the present application). The delay line circuit 14 receives the control signal dll_code and the selection control signal SEL.

[0047] The delay line circuit 14 includes a variable delay circuit for performing a locking operation. Each time the delay amount is set by the DLL control circuit 13, the variable delay circuit delays the input clock signal clk based on the delay amount (i.e., the control signal dll_code and the selection control signal SEL) to generate a delay signal dll_clk (output clock signal), and outputs the delay signal dll_clk to the output buffer 16. The output buffer 16 controls the output of the data DQS according to the delay signal dll_clk.

[0048] According to the first embodiment of the present application, Figure 2As shown, the delay line circuit 14 includes n delay units U1-Un (e.g., U1-U10), where n is a positive integer greater than 1. In this embodiment, n is equal to 10, but not limited thereto. Each delay unit U1-Un includes a delay device (e.g., one or more of E1-E12) for delaying the input clock signal clk. Moreover, among these delay units U1-Un, the number of delay devices (e.g., E9-E10) included in at least one delay unit (e.g., U9) is greater than the number of delay devices (e.g., E1) included in other delay units (e.g., U1). In this embodiment, each delay device (e.g., E1-E12) is composed of two NAND gates connected in series. These NAND gates Nm (e.g., N1-N24) are connected in series to form a NAND gate row 22. Wherein m is a positive integer greater than n. In this embodiment, m is equal to 24, but not limited thereto.

[0049] In the delay line circuit 14 of the present embodiment, the end side receiving the input clock signal clk is called the upstream side, and the opposite side is called the downstream side. In the present embodiment, the NAND gate N1 located at the most upstream side (the leftmost end in the figure) of the NAND gate row 22 receives the input clock signal clk, and the other NAND gates (such as N2 to N24) receive the output of the NAND gate of the previous stage. For example, the NAND gate N2 receives the output of the NAND gate N1.

[0050] In addition, each delay unit U1-Un receives a code signal of the control signal dll_code generated by the DLL control circuit 13. <1> ~ <n>(For example <1> ~ <10> ), and input the same code signal (e.g. <9> ). This code signals <1> ~ <n>It is used to determine whether the corresponding delay unit U1~Un is activated. <x>If the logic value of is "1", the corresponding delay unit Ux is activated, where x is a positive integer between 1 and n. For example, the same control signal dll_code is input to the NAND gates N1 and N2 included in the delay unit U1. <1> , if the code signal <1> If the logic value of is "1", the delay unit U1 is activated.

[0051] In addition, the delay line circuit 14 further includes a multiplexer 21. In each delay unit U1-Un (e.g., U9), the output of the NAND gate (e.g., N20) at the last stage (i.e., the most downstream side) is provided to the multiplexer 21 as a unit signal unit_1-unit_n (e.g., unit_9). The multiplexer 21 also receives a selection control signal SEL. The selection control signal SEL is used to indicate which of the unit signals unit_1-unit_n of the delay units U1-Un is to be selected as the output of the multiplexer 21, as the delay signal dll_clk.

[0052] In the locking operation, according to the delay signal dll_clk, starting from the delay unit U1 on the most upstream side receiving the input clock signal clk, the required delay units Ux are activated in sequence in the downstream direction until the delay amount set by the DLL control circuit 13 is achieved, and the activated delay units Ux are used to delay the input clock signal clk. For example, when the delay amount set by the DLL control circuit 13 requires the activation of 9 delay units U1 to U9 to be achieved, the DLL control circuit 13 generates a selection control signal SEL for indicating the selection of the delay unit U9, and generates a code signal including activation of the delay units U1 to U9. <1> ~ <9> The control signal dll_code is selected and the code signals whose logic values ​​are 1 are selected by the control signal SEL. <1> ~ <9> Output to the delay line circuit 14. In this case, the delay units U1 to U9 are activated to delay the input clock signal clk, thereby generating unit signals unit_1 to unit_9. Then, according to the selection control signal SEL, the unit signal unit_9 from the delay unit U9 is selected in the multiplexer 21 as the delayed signal dll_clk and output.

[0053] At Figure 2 In the embodiment, the number of NAND gates of one of the delay units U1 to Un of the delay line circuit 14 is different from the number of NAND gates of the other. For example, the delay unit U1 is composed of two-stage NAND gates N1 and N2, and the delay unit U9 is composed of four-stage NAND gates N17, N18, N19 and N20. In other words, the delay unit U1 is composed of one delay device E1, and the delay unit U9 is composed of two delay devices E9 and E10. However, the present application is not limited to this. In the example Figure 3 In the schematic diagram of the relationship between the delay units U1-Un and the NAND gates N1-Nm of the delay line circuit 14 shown, these quadrilaterals represent the delay units U1-Un, and the upper left corner of each quadrilateral indicates its number (for example, the upper left corner is 1 to indicate that the quadrilateral is the delay unit U1), and the number of NAND gates included in the delay units U1-Un is displayed in the quadrilateral. In this embodiment, the larger the number of NAND gates included, the larger the quadrilateral is drawn. The NAND gate row 22 is configured such that each of the delay units U1 to U8 has 2 stages of NAND gates (i.e., 1 delay device), each of the delay units U9 to U16 has 4 stages of NAND gates (i.e., 2 delay devices), each of the delay units U17 to U24 has 6 stages of NAND gates N (i.e., 3 delay devices), and each of the delay units U25 to U32 has 8 stages of NAND gates N (i.e., 4 delay devices).

[0054] It should be noted that in the traditional delay line circuit, each delay unit is composed of the same number of delay devices, such as Figure 4A As shown, all delay units are composed of two-stage NAND gates. As a result, when the delay amount is large, a large number of delay units need to be activated in sequence to complete the locking action. In other words, when the delay amount is large, it takes a long time to activate the required number of delay units.

[0055] In contrast, and unlike conventional delay line circuits, the number of delay devices included in at least one of the delay units U1 to Un of the delay line circuit 14 of the present embodiment is greater than the number of delay devices included in the other delay units, so that the extension of the lock time Td11 can be suppressed. Specifically, when delay units U1 to Ux are activated sequentially in order to activate the delay units Ux corresponding to the number of NAND gates required to achieve the delay amount, since the number of NAND gates included in the downstream delay unit Ux is greater, multiple NAND gates can be activated by activating only one delay unit Ux, so the required delay amount can be achieved quickly. Figure 4B As shown, in one embodiment of the present application, each of the delay units U1-U8 is a 2-stage NAND gate, and each of the delay units U9-U13 is a 4-stage NAND gate. The following uses more specific numbers to illustrate the difference in technology and function between the conventional delay line circuit and the present embodiment.

[0056] When the delay required for the locking action corresponds to activating 36 stages of NAND gates, Figure 4A In the conventional delay line circuit shown in FIG. 1 , it is necessary to activate the delay unit U1 to the delay unit U18 in sequence. In this case, Figure 5A As shown in FIG. 1 , the conventional delay line circuit needs 18 units of locking time to complete the locking action. Figure 4B In the delay line circuit 14 of the present embodiment shown, it is only necessary to activate the delay unit U1 to the delay unit U13 in sequence. Figure 5B As shown, the delay line circuit 14 of this embodiment can complete the locking action in 13 units of locking time, thereby improving the execution efficiency of the delay locked loop 1.

[0057] In detail, in this embodiment, the number of stages (4) of the NAND gates constituting each of the delay units U9 to U13 on the downstream side is greater than the number of stages (2) of the NAND gates constituting each of the delay units U1 to U8 on the upstream side, so that the activation of multiple NAND gates required to eliminate the delay time can be achieved quickly to shorten the lock time Td11. Therefore, the execution time tDLLK of the program corresponding to the lock time can be shortened. In addition, since each delay device is composed of, for example, 2 NAND gates, the number of delay devices (2) constituting each of the delay units U9 to U13 on the downstream side is greater than the number of delay devices (1) constituting each of the delay units U1 to U8 on the upstream side. Thereby, more appropriate control can be performed according to the required delay amount. In short, when the delay amount is small, the locking action corresponding to activating the delay units U1~U8 on the upstream side can be completed within the predetermined execution period. Moreover, even when the delay amount is large, by activating the delay units U9~U13 on the downstream side with more delay devices, the locking action can still be completed within the predetermined execution period, thereby improving the reliability of the output of the data DQS.

[0058] In such Figure 3 In the embodiment shown, the number of NAND gates is increased by 2 for every 8 delay units (i.e., the number of delay devices is increased by 1), but the present application is not limited thereto. The delay line circuit 14 can be configured to increase the number of delay devices by z for every y delay units starting from the delay unit U1 receiving the input clock signal clk according to the execution period tDLLK of the preset DLL program. Where y is a positive integer less than n, and z is a positive integer. Alternatively, at least one delay device number increase position y can be set in the delay units U1 to Un according to the execution period tDLLK of the preset DLL program, so that the number of delay devices from the delay unit Uy located at the delay device number increase position y to the delay unit Un (an example of a delay unit located at the other end side) is greater than the number of delay devices from the delay unit U1 (an example of a delay unit located at one end side) to the delay unit Uy-1 located at the previous position of the delay device number increase position y.

[0059] In addition, when the delay line circuit 14 sets only one delay device number increase position y, it is preferable to set the delay device number increase position y to the relatively downstream side (an example of the other end side). Figure 4B As shown, in the delay line circuit 14 composed of 13 delay units U1~U13, only one delay device number increase position y is set, and the delay device number increase position y is set to 9. Thereby, even when the delay amount is very large, by using the delay units U9~U13 with the increase in the number of delay devices, the locking action can be ended earlier than the conventional method. In addition, multiple delay device number increase positions y, y+i... can be set at different intervals in the NAND gate row 22, where i is not equal to y. Preferably, the number of delay units between these delay device number increase positions y, y+i... is less than the number of delay units from the downstream side to the most adjacent delay device number increase position. For example, the delay line circuit 14 having 24 delay units U1 to U24 can be configured to have two delay device increment positions y and y+i, with y equal to 9 and i equal to 4, so that each of the delay units U1 to U8 is composed of two stages of NAND gates, each of the delay units U9 to U12 is composed of four stages of NAND gates, and each of the delay units U13 to U24 is composed of six stages of NAND gates. In this way, since the delay units U9 to U24 on the downstream side have more delay devices than the most upstream delay unit U1, the locking action can be completed earlier than conventional methods.

[0060] In the present embodiment, one delay device is added from each delay device quantity increase position (for example, two levels of NAND gates are added), but the present application is not limited thereto. For example, a delay line circuit 14 having 24 delay units U1 to U24 can be configured to have one delay device quantity increase position y set, and y is equal to 17, so that each of delay unit U1 to delay unit U16 is composed of two levels of NAND gates, and each of delay unit U17 to delay unit U24 is composed of eight levels of NAND gates. For embodiments requiring fine control, it is preferred to gradually increase the number of delay devices. For embodiments requiring locking action efficiency, the number of delay devices increased can be set to be greater than 1.

[0061] In the first embodiment described above, the multiplexer 21 is provided on the output side of the delay line circuit 14. Figure 6 The second embodiment shown is different from the first embodiment in that the delay line circuit 14 is configured to use a selector to form a delay device (e.g., E7~E12) without the need to set a multiplexer 21. In the second embodiment, the delay line circuit 14 includes n delay units U1~Un (e.g., U1~U16, only U7~U10 are shown for simplicity), where n is a positive integer greater than 1. Each delay unit U1~Un includes a delay device (e.g., E1~E24, only E7~E12 are shown for simplicity) for delaying the input clock signal clk. Moreover, among these delay units U1~Un, the number of delay devices (e.g., E9~E10) included in at least one delay unit (e.g., U9) is greater than the number of delay devices (e.g., E1) included in other delay units (e.g., U1). In this embodiment, these delay units U1~Un constitute a NAND gate row 32. It should be noted that in Figure 6 Only a portion of the NAND gate row 32 is shown.

[0062] Specifically, the NAND gate row 32 includes a first NAND sub-gate row 33 and a second NAND sub-gate row 34. The first NAND sub-gate row 33 is composed of a plurality of first NAND gates NA and second NAND gates NB connected in series. The second NAND sub-gate row 34 includes a plurality of third NAND gates NC respectively connected to the second NAND gates NB, and these third NAND gates NC are in parallel relationship. In this embodiment, each delay device (e.g., E7 to E12) includes a selector composed of a first NAND gate NA, a second NAND gate NB, and a third NAND gate NC.

[0063] Different from the first embodiment, in the second embodiment, the input clock signal clk is provided in parallel to the input ends of these third NAND gates NC, and the delay units are given serial numbers (i.e., 1 to n) starting from the end generating the delay signal dll_clk. In the present embodiment, the delay unit U8 includes one delay device E8, and the delay unit U9 with a larger serial number includes two delay devices E9 and E10. In the present embodiment, a delay device quantity increase position y is set in the delay line circuit 14, and y is equal to 9. Each of the delay units U16 (not shown) to the delay unit U9 on the upstream side of the delay device quantity increase position y (i.e., away from the end generating the delay signal dll_clk) has two delay devices, and each of the delay units U8 to the delay unit U1 on the downstream side of the delay device quantity increase position y (i.e., toward the end generating the delay signal dll_clk) has one delay device.

[0064] The second NAND gate NB of the first NAND sub-gate row 33 receives the output of the first NAND gate NA and the output of the third NAND gate NC. The third NAND gate NC receives the input clock signal clk and the code signal of the "0" signal or the control signal dll_code. <1> ~ <n>(For example <1> ~ <16> , for simplicity only <7> ~ <10> ). Specifically, in the present embodiment, in each of the delay units U1 to U16, only the third NAND gate NC on the most upstream side receives the code signal of the control signal dll_code. <1> ~ <n>The remaining third NAND gate NC receives a "0" signal. The first NAND gate NA of the most upstream delay device of the delay line circuit 14 (i.e., the delay device farthest from the end generating the delay signal dll_clk, such as E24, not shown in this figure) receives a "1" signal and a complementary code signal of the control signal dll_code. (For example ), and the first NAND gate NA of other delay devices (such as E1 to E23) receives the output of the second NAND gate NB of the previous stage, and the "1" signal or the complementary code signal Specifically, in the present embodiment, in each of the delay units U1 to U16, only the first NAND gate NA on the most upstream side receives the complementary code signal The remaining first NAND gates NA receive a "1" signal. In this embodiment, the selection control signal SEL includes a code signal of the control signal dll_code. <1> ~ <n>and complementary code signal

[0065] In this embodiment, only the delay unit Ux selected by the selection control signal SEL input to the selector is activated. In the activated delay unit Ux, the input clock signal clk is delayed through the third NAND gate NC and the second NAND gate NB of the delay unit Ux, and is output to the adjacent first NAND gate NA to be delayed through the delay units Ux~U1 of the first NAND sub-gate row 33 and output as the delay signal dll_clk.

[0066] In short, in the delay line circuit 14 of the present embodiment, among the delay units U1 to Un connected in series, only the delay unit Ux required to achieve the delay amount is activated, and the input clock signal clk is delayed using the delay unit U1 from the activated delay unit Ux to the downstream end of the output delay signal dll_clk. For example, when the delay unit U9 is set to be activated by the DLL control circuit 13, the selection control signal SEL representing the selection of the delay unit U9 is input, so that the delay unit U9 is activated, thereby using the delay units U1 to U9 in the delay action to delay the input clock signal clk to generate and output the delay signal dll_clk. In detail, the DLL control circuit 13 provides a code signal with a logic value of "1" to the third NAND gate NC of the most upstream delay device E10 of the delay unit U9. <9> , providing a code signal with a logic value of "0" to the remaining third NAND gate NC, and providing a complementary code signal with a logic value of "0" to the first NAND gate NA of the delay device E10 And a complementary code signal with a logic value of "1" is provided to the remaining first NAND gates NA, so that the delay device E10 selects the input clock signal clk as the output and provides it to the first NAND gate NA of the delay device E9. Then the input clock signal clk is delayed through the delay unit U1 to the first NAND gate NA and the second NAND gate NB of the delay unit U8 and output as the output delay signal dll_clk. At this time, the number of NAND gates of the delay unit U8 used for the delay action is 2 (i.e., delayed through 1 third NAND gate NC and 1 second NAND gate NB), and the number of NAND gates of the delay unit U9 used for the delay action is 4 (i.e., delayed through 2 third NAND gates NC and 2 second NAND gates NB), and the delay amount provided is the same as that of the delay units U8 and U9 of the first embodiment.

[0067] Thus, even in the present embodiment, since the number of delay devices included in each delay unit on the upstream side of the delay device number increase position y (i.e., away from the end generating the delay signal dll_clk) is greater than the number of delay devices included in each delay unit on the downstream side of the delay device number increase position y (i.e., toward the end generating the delay signal dll_clk), when the delay amount is large, the required number of delay devices can be used earlier through the selection control signal SEL, so the locking time Td11 can be shortened. Therefore, the total execution time (tDLLK) of the DLL program including the locking time can also be shortened.

[0068] In the above-mentioned embodiment, the delay device is formed by a NAND gate, but the present application is not limited thereto. In addition, the configuration of the delay line circuit 14 is not particularly specified.

[0069] In the above embodiments, although the semiconductor storage device with a delay locked loop is DRAM as an example, the present application is not limited thereto. For example, the semiconductor storage device may be an SRAM (static random access memory), a flash memory, or other semiconductor storage devices.

[0070] The embodiments and variations described above are recorded for easy understanding of the present application and are not intended to limit the present application. Therefore, the elements disclosed in the embodiments and variations described above also include all design changes and equivalents within the technical scope of the present application.

[0071] The configuration of the delay locked loop 1 in the above-described embodiment is an example, and other various configurations may be appropriately changed and adopted.< / n> < / n> < / n> < / x> < / n> < / n>

Claims

1. A delay locked loop, characterized in that: include: The DLL control circuit sets the delay amount according to the phase difference between the input clock signal and the output clock signal; as well as A delay line circuit receives the input clock signal and is configured to perform a delay operation on the input clock signal according to the delay amount to generate the output clock signal; The delay line circuit includes a plurality of delay units, each of the delay units includes at least one delay device, and the number of delay devices included in one of the delay units is greater than the number of delay devices included in another of the delay units.

2. The delay locked loop according to claim 1, wherein: Also includes: An input buffer configured to buffer the received external clock signal to generate the input clock signal; a replica circuit configured to generate a feedback signal according to the output clock signal; and A phase detection circuit is coupled between the replica circuit and the DLL control circuit, receives the input clock signal and the feedback signal, and generates a phase signal indicating the phase difference to the DLL control circuit. The DLL control circuit generates a selection control signal and a control signal indicating the delay amount according to the phase signal, and the delay line circuit activates corresponding ones of the delay units according to the selection control signal and the control signal to delay the input clock signal.

3. The delay locked loop according to claim 2, wherein: The multiple delay units are connected in series, each of the delay units is configured to generate a unit signal, and one of the unit signals is selected as the output clock signal, the most upstream delay unit receives the input clock signal, and each of the remaining delay units receives the unit signal generated by the upstream delay unit.

4. The delay locked loop as claimed in claim 3, characterized in that: The delay line circuit further comprises: The multiplexer is configured to receive the unit signal and the selection control signal. The multiplexer selects one of the unit signals as the output of the multiplexer according to the selection control signal to serve as the output clock signal.

5. The delay locked loop as claimed in claim 4, characterized in that: The delay line circuit uses the delay units sequentially from one end side to the other end side to perform the delay action according to the delay amount, and the number of delay devices included in the delay unit located at the other end side is greater than the number of delay units included in the delay unit located at the one end side.

6. The delay locked loop as claimed in claim 5, characterized in that: The delay line circuit is configured such that the number of delay devices included in each of the delay units from the other end side to the position where the number of delay devices increases is greater than the number of delay devices included in each of the delay units from the previous position of the position where the number of delay devices increases to the one end side.

7. The delay locked loop according to claim 5, wherein: The number of the delay units from the other end side to a position where the number of delay devices increases is smaller than the number of the delay units from a position before the position where the number of delay devices increases to the one end side.

8. The delay locked loop as claimed in claim 3, wherein: Each of the delay devices is composed of two NAND gates connected in series.

9. The delay locked loop according to claim 1, wherein: The delay line circuit is configured to be set with multiple positions where the number of delay devices increases, and the number of delay units between the positions where the number of delay devices increases is smaller than the number of delay units between the delay unit farthest from the input clock signal and the adjacent positions where the number of delay devices increases.

10. The delay locked loop according to claim 2, wherein: Each of the delay devices comprises: First NAND gate; a second NAND gate connected in series with the first NAND gate, wherein a first input terminal of the second NAND gate is coupled to an output terminal of the first NAND gate; and The third NAND gate receives the input clock signal and the selection control signal, and the output end of the third NAND gate is coupled to the second input end of the second NAND gate.

11. The delay locked loop according to claim 10, wherein: The output end of the second NAND gate of one of the plurality of delay devices is coupled to the input end of the first NAND gate of another of the plurality of delay devices to form a first NAND sub-gate row having the first NAND gates and the second NAND gates arranged alternately, and the delay line circuit outputs the output clock signal via one end of the first NAND sub-gate row.

12. The delay locked loop according to claim 11, wherein: One of the plurality of delay cells farther from the end of the first NAND sub-gate row includes a greater number of delay cells than one of the plurality of delay cells closer to the end of the first NAND sub-gate row.

13. The delay locked loop according to claim 11, wherein: One of the plurality of delay units is activated according to the selection control signal. In the activated delay unit, the input clock signal is selected as the output of the delay device and is transmitted to the first NAND sub-gate row until it is output through the end of the first NAND sub-gate row and serves as the output clock signal.

14. The delay locked loop according to claim 11, wherein: The delay line circuit sequentially uses the delay units to perform the delay action starting from the selected ones of the multiple delay units toward the end side of the first NAND sub-gate row according to the selection control signal, and the number of the delay devices included in the selected ones of the multiple delay units is greater than the number of the delay units included in the delay units adjacent to the end side of the first NAND sub-gate row.

15. The delay locked loop according to claim 11, wherein: The delay line circuit is configured as follows: the number of delay devices included in each of the delay cells from the end of the first NAND sub-gate row to a position before a position where the number of delay devices increases is less than the number of delay devices included in each of the delay cells starting from the position where the number of delay devices increases to the other end of the first NAND sub-gate row.

16. The delay locked loop according to claim 11, wherein: The selection control signal includes a plurality of code signals and a plurality of complementary code signals, each of the code signals is provided to the third NAND gate of a corresponding one of the delay units, and each of the complementary code signals is provided to the other input end of the first NAND gate of a corresponding one of the delay units.

17. The delay locked loop according to claim 16, wherein: The input terminal of the first NAND gate of one of the plurality of delay devices farthest from the end of the first NAND sub-gate row receives a fixed first logic value.

18. The delay locked loop according to claim 17, wherein: The delay line circuit is configured such that, in each of the delay units, only the third NAND gate farthest from the end of the first NAND sub-gate row receives a corresponding one of the code signals, and the remaining third NAND gates receive a fixed second logic value, and only the first NAND gate farthest from the end of the first NAND sub-gate row receives a corresponding one of the complementary code signals, and the remaining first NAND gates receive a fixed first logic value.

19. A semiconductor storage device, characterized in that: include: A delay locked loop as claimed in any one of claims 1 to 18; and The output buffer receives the output clock signal and controls the output of data according to the output clock signal.

20. The semiconductor memory device according to claim 19, wherein The semiconductor storage device is a dynamic random access memory.

Images