A method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology

Abstract

The present invention discloses a method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology, including two operations: dithering voltage injection and high-order decimation filtering. The dithering voltage injection is performed by injecting Gaussian-distributed dithering voltage into the coarse-quantization SAR ADC input of the scaling analog-to-digital converter controlled by a capacitor array controlled by a random sequence, thereby enhancing the randomness of the quantization error. The high-order decimation filtering sums and averages the randomly distributed quantization noise, and the final quantization error obtained is smaller than the quantization error of the traditional incremental scaling analog-to-digital converter, thereby effectively improving the signal-to-noise ratio of the incremental scaling analog-to-digital converter. The analog circuit part overhead brought by the signal-to-noise ratio improvement method of the present invention is only the capacitor array used for dithering voltage injection, which has higher area and energy efficiency than other signal-to-noise ratio improvement technologies.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on a dithering technology. Background Art

[0002] With the continuous development of applications such as smart sensors and the Internet of Things, low-power and high-precision analog-to-digital converters (ADCs) in sensor applications have attracted extensive attention from researchers as core circuit modules in the signal chain. Among all types of ADCs, Δ-Σ ADCs can achieve high precision due to their oversampling and noise shaping characteristics, and are widely used in low-speed, low-power, and high-precision sensor scenarios.

[0003] The incremental working mode is to periodically reset the Δ-Σ ADC. This working mode has the following advantages in sensor applications: it simplifies the design of the extraction filter, from the cascaded integrator comb filter to the CoI (Cascade-of-Integrator) filter; the incremental Δ-Σ ADC can be reused in multi-channel sensors due to its low latency; the incremental Δ-Σ ADC is not easily affected by idle sound.

[0004] The scaling ADC is a two-step ADC that first performs coarse quantization and then fine quantization. It has high energy efficiency and is more efficient than Δ-Σ ADCs of other architectures. Therefore, the incremental scaling Δ-Σ ADC has a very high application prospect and has been applied in many fields. However, when the scaling Δ-Σ ADC works in the incremental working mode, the quantization noise will increase due to the lack of a feedforward path in the scaling Δ-Σ ADC, which will deteriorate the signal-to-quantization-noise ratio (SQNR) of the ADC. Therefore, it is necessary to optimize the quantization noise of the scaling ADC in the incremental working mode to achieve higher accuracy.

[0005] Traditionally, the method of improving the signal-to-noise ratio of zoom ADCs in incremental working mode is mostly to increase the analog circuit overhead. For example, the literature [Ji Huaikun. Research and design of zoom IADC based on PPD [D]. Zhejiang: Zhejiang University, 2023] uses a higher-order loop filter; the Chinese patent application with publication number CN117375620A proposes a cascaded extended count SAR (successive approximation) analog-to-digital converter with a higher bit number; the Chinese patent application with publication number CN115549683A proposes a high-precision incremental zoom ADC that introduces a multi-stage architecture and residual amplification. However, these technologies increase the analog circuit overhead, requiring the design of amplifiers, higher-bit SAR analog-to-digital converters, and higher integrator gains, which are not the best choice at more advanced process nodes. Summary of the invention

[0006] In view of the above, the present invention provides a method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology, which solves the problem of increased quantization noise of the scaling ADC under incremental operation with as little analog circuit overhead as possible.

[0007] A method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology, wherein the incremental scaling analog-to-digital converter includes a coarsely quantized successive approximation ADC and a finely quantized delta-sigma modulator, and the method for improving the signal-to-noise ratio includes two parts: dithering voltage injection and high-order decimation filtering, wherein the dithering voltage injection part is to improve the randomness of the quantization noise distribution by inputting a dithering voltage to the successive approximation ADC, and the high-order decimation filtering part is to achieve a higher first-order integration of the digital output of the delta-sigma modulator by summing and averaging the quantization noise.

[0008] Furthermore, the jitter voltage injection part is implemented by a jitter injection capacitor array, a pseudo-random sequence generator and a switch control logic, and the upper plate of the jitter injection capacitor array is connected to the upper plate of the capacitor array in the successive approximation ADC; in the sampling stage of the successive approximation ADC, the lower plate of the jitter injection capacitor array is connected to the common mode voltage V CM In the successive approximation ADC hold and conversion phase, the pseudo-random sequence generator generates a set of random sequences and controls the jitter injection capacitor array through the switch control logic. The lower plate is connected to the power supply voltage V DD V SS .

[0009] Furthermore, the pseudo-random sequence generator is synthesized by a hardware description language to generate a random sequence that obeys a Gaussian distribution.

[0010] Furthermore, the effective value of the jitter voltage is 0.5V LSB , where VLSB =V FS / 2 N , V FS is the full amplitude of the successive approximation ADC, and N is the number of bits of the successive approximation ADC.

[0011] Furthermore, the high-order decimation filter part is implemented by a high-order CoI decimation filter, which has an order one order higher than that of an analog loop filter in a delta-sigma modulator.

[0012] Furthermore, the high-order CoI extraction filter is composed of L+1-level digital integrators INT1~INT L+1 Each digital integrator is connected in sequence. Each level is composed of a full adder and a register. The full adder in INT1 adds the digital output of the delta-sigma modulator to the output result of INT1 in the previous cycle as the output result of INT1 in the current cycle, and stores the output result in the register. i The full adder in the previous cycle INT i-1 The output result is the same as the previous cycle INT i The output result is added as the current cycle INT i The output result is stored in the register; INT L+1 The full adder in the previous cycle INT L The output result is the same as the previous cycle INT L+1 The output result is added as the current cycle INT L+1 The output result (i.e., the final digital output result of the incremental scaling analog-to-digital converter in the current cycle) is obtained and stored in a register; wherein i is a natural number and 1<i≤L, and L is the order of the analog loop filter.

[0013] Furthermore, the number of output bits of the register in each stage of the digital integrator is determined by the number of cycles M of a Nyquist conversion of the incremental scaling analog-to-digital converter, the number of bits N of the successive approximation ADC, and the number of stages j of the digital integrator, and specifically satisfies the following relationship:

[0014] n j >log2((2 N -1)M j / j!)

[0015] Where: n j represents the number of output bits of the register in the j-th digital integrator, ! represents the factorial, j is a natural number and 1≤j≤L+1.

[0016] Furthermore, the method for improving the signal-to-noise ratio of the present invention utilizes the random distribution characteristics of the quantization noise and reduces the quantization error of the incremental scaling analog-to-digital converter from E×(L! / ML ) is reduced to E sum ×[(L+1)! / M (L+1) ], where E is the quantization error of each cycle of the incremental scaling analog-to-digital converter, E sum It is the sum of the quantization errors of the incremental scaling analog-to-digital converter within M cycles.

[0017] Based on the above technical solution, the present invention has the following beneficial technical effects:

[0018] 1. The present invention innovatively proposes a method for improving the signal-to-noise ratio from the perspective of filter design, utilizing the random distribution characteristics of quantization noise to perform a higher first-order integration, and obtains a smaller final quantization noise after averaging.

[0019] 2. The present invention innovatively utilizes dithering technology to improve the randomness of quantization noise, thereby eliminating the signal component in the quantization noise caused by insufficient number of bits of the coarse quantization SAR quantizer in the scaling ADC.

[0020] 3. The analog circuit portion of the present invention only has a jitter injection capacitor array as overhead, and does not impose any requirements on the analog loop filter portion of the scaling ADC. Compared with other signal-to-noise ratio improvement methods, the present invention has higher energy efficiency and hardware efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The system implementation block diagram of the incremental scaling analog-to-digital converter signal-to-noise ratio improvement method of the present invention.

[0022] Figure 2 FIG. 4 is a schematic diagram of the structure of a jitter injection capacitor array according to an embodiment of the present invention.

[0023] Figure 3 Schematic diagram of the structure of a high-order CoI extraction filter in an embodiment of the present invention.

[0024] Figure 4 The block diagram of the incremental scaling ADC system using the method of the present invention is shown in FIG. 1 , wherein (a) is a scaling Δ-Σ loop filter based on dithering technology, and (b) is a three-stage cascaded integrator filter.

[0025] Figure 5 Schematic diagram of the quantization noise distribution of the incremental scaling ADC before and after the application of the method of the present invention, wherein (a) is the quantization error of a common incremental 2nd-order 5-bit scaling ADC, and (b) is the quantization error of the incremental 2nd-order 5-bit scaling ADC using the method of the present invention.

[0026] Figure 6 The figure is a schematic diagram of the output spectrum of the incremental scaling ADC under AC signal input before and after the method of the present invention is applied. DETAILED DESCRIPTION

[0027] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0028] The method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology of the present invention includes two operations: dithering voltage injection and high-order decimation filtering. The dithering voltage injection is used to improve the randomness of the quantization noise distribution, and the high-order decimation filtering is used to sum and average the quantization noise, wherein:

[0029] The jitter voltage injection is completed by the jitter injection capacitor array controlled by a random sequence. The position of the jitter voltage injection is the input of the coarse quantization successive approximation ADC. The jitter injection capacitor array is controlled by a random sequence. The specific operation is as follows: in the sampling stage of the coarse quantization successive approximation ADC, the capacitor array samples the input signal; in the hold and conversion stage, the capacitor array is connected to V DD or V SS , complete the injection of the jitter voltage. The effective value of the injected jitter voltage is generally 0.5V for a coarse quantization successive approximation ADC. LSB , where V LSB =V FS / 2 N , V FS is the full amplitude of the successive approximation ADC, and N is the number of bits of the coarse quantization successive approximation ADC.

[0030] The random sequence is generated by a pseudo-random sequence generator and obeys Gaussian random distribution; the pseudo-random array generator is synthesized by a hardware description language and generates a random sequence with Gaussian distribution.

[0031] The high-order decimation filter is completed by integrating the digital output of the incremental scaling ADC by a cascaded integral decimation filter. The cascaded integral decimation filter has a higher order than the analog loop filter of the scaling ADC, and can achieve a higher order integration of the quantization error. The principle is to use the random distribution of the quantization noise, sum it and then average it. The final quantization error obtained by this process will be smaller than the quantization error without a higher order integration. The cascaded integral decimation filter is composed of a register chain. The number of bits n of the register chain is determined by the number of cycles M of an incremental conversion, the number of bits N of the successive approximation ADC and the number of stages i of the digital integrator. The number of bits of the specific register chain satisfies n>log2((2 N -1)M i / i!), n is a positive integer.

[0032] The method of the present invention utilizes the random distribution characteristics of quantization noise, and reduces the quantization error of the incremental scaling analog-to-digital converter from E×(L! / M by summing and averaging the quantization noise.L ) is reduced to E sum ×[(L+1)! / M (L+1) ], where E is the quantization error of each cycle of the scaling analog-to-digital converter, E sum is the sum of the quantization errors in M ​​cycles. Example

[0033] This embodiment provides a method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter. Figure 1 As shown, the incremental scaling analog-to-digital converter includes an N-bit SAR analog-to-digital converter (N-bit SAR) and a fine-quantized Δ-Σ modulator, and the Δ-Σ modulator includes an analog loop filter (Loop Filter) and an N-bit digital-to-analog converter (N-bit DAC).

[0034] Compared with the traditional architecture, this embodiment specifically includes two operations: (1) dithering voltage injection for the coarse quantization N-bit SAR ADC; and (2) high-order decimation filtering for the output digital code V.

[0035] Figure 2 The figure shows an implementation method of dither voltage injection for coarse quantization SAR ADC. The hardware circuit includes a set of dither injection capacitor arrays C0~C k-1 , a PRNG (Pseudo Random Number Generator) and switch control logic. The lower plates of the capacitor array are connected to control the connection to V CM 、V DD 、V SS The switch is connected to the upper plate and then connected to the upper plate of the capacitor of the coarse quantization SAR ADC. k-1 Connect to V CM , participate in sampling; in the hold and conversion phases, the lower plate is based on the Gaussian random sequence D DIT<0:k-1> The control is connected to V DD or V SS . Because the capacitance C0~C k-1 The upper plate of the ADC is directly connected to the upper plate of the coarse quantization SAR ADC, so during holding and conversion, a dithering voltage with Gaussian distribution is injected into the coarse quantization SAR ADC and included in its quantization noise.

[0036] Figure 3 The figure shows the implementation of a multi-stage CoI digital filter, which consists of L+1 digital integrators (with a transfer function of , z represents the Z transform operator) are connected in sequence, and each level of digital integrator is composed of a full adder and a register, thereby realizing the accumulation function; where V is the digital code output of the incremental scaling analog-to-digital converter, D OUT For a Nyquist conversion with a conversion period of M in the incremental working mode: the reset signal RST resets all registers. When the clock signal CLK of each cycle arrives, the digital output V of this cycle is added to the sum of the previous cycle through the full adder and then stored in the register; after M cycles, the final result of this conversion is D OUT .

[0037] The bit length of the decimation filter can be determined by the following analysis: For a first-order filter, the digital output V is N bits. After M cycles, the maximum possible output is (2 N -1)M, the corresponding filter bit number is at least log2((2 N -1)M) is rounded up. Similarly, for the i-th level digital integrator, the lowest number of bits is n>log2((2 N -1)M i / i!), 1≤i≤L+1, L is the order of the analog loop filter.

[0038] Figure 4 FIG. 1 is an embodiment of the method of the present invention. The analog loop filter part is a two-order 5-bit scaling delta-sigma ADC. The specific filter coefficients are shown in the figure, where U is the input of the ADC, E0 and E1 are the quantization noise of the coarse quantization SAR ADC and the fine quantization delta-sigma modulator in the scaling ADC, V0 and V1 are the digital outputs of the coarse quantization SAR ADC and the fine quantization delta-sigma modulator, and E0 is the quantization noise of the coarse quantization SAR ADC and the fine quantization delta-sigma modulator, respectively. dit is the injected jitter voltage with Gaussian distribution; V0 and V1 are summed in the digital domain and then passed through a three-stage cascaded integrator filter to obtain the final output.

[0039] Figure 5 The quantization noise of an incremental two-stage 5-bit scaling Δ-Σ ADC before and after the application of the signal-to-noise ratio improvement method of the present invention is shown. It can be seen that the quantization noise is significantly reduced after the application of the present invention. Under the conditions of conversion period M=200 and input signal size of a sine wave of -0.9dBFS, the output spectrum before and after the application of the signal-to-noise ratio improvement method of the present invention is as follows: Figure 6As shown in the figure, the SQNR of this incremental two-order 5-bit scaling ADC is improved from 107.2dB to 114.5dB, achieving an improvement of more than 7dB. Compared with the method of solving this problem by the traditional incremental scaling Δ-Σ ADC, the signal-to-noise ratio improvement method of the present invention has extremely small overhead of the analog circuit part, which is only a set of jitter voltage injection capacitor arrays. The remaining overhead comes from a higher-order filter and a pseudo-random sequence generator, which are all digital circuit overheads, and has greater advantages in advanced processes and low-voltage working environments.

[0040] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments. Improvements and modifications made by those skilled in the art to the present invention based on the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology, wherein the incremental scaling analog-to-digital converter comprises a coarse quantization successive approximation ADC and a fine quantization delta-sigma modulator, characterized in that: The method for improving the signal-to-noise ratio of the incremental scaling analog-to-digital converter includes two parts: jitter voltage injection and high-order decimation filtering. The jitter voltage injection part is to improve the randomness of the quantization noise distribution by inputting the jitter voltage to the successive approximation ADC, and the high-order decimation filtering part is to achieve a higher first-order integration of the digital output of the delta-sigma modulator by summing and averaging the quantization noise. The jitter voltage injection part is implemented by a jitter injection capacitor array, a pseudo-random sequence generator and a switch control logic. The upper plate of the jitter injection capacitor array is connected to the upper plate of the capacitor array in the successive approximation ADC. In the sampling phase of the successive approximation ADC, the lower plate of the jitter injection capacitor array is connected to the common mode voltage V CM In the successive approximation ADC hold and conversion phase, the pseudo-random sequence generator generates a set of random sequences and controls the jitter injection capacitor array through the switch control logic. The lower plate is connected to the power supply voltage V DD V SS ; The high-order extraction filter part is implemented by a high-order CoI extraction filter, which has a higher order than the analog loop filter in the Δ-Σ modulator; the high-order CoI extraction filter is composed of L+1-level digital integrators INT1~INT L+1 Each digital integrator is connected in sequence. Each level is composed of a full adder and a register. The full adder in INT1 adds the digital output of the delta-sigma modulator to the output result of INT1 in the previous cycle as the output result of INT1 in the current cycle, and stores the output result in the register. i The full adder in the previous cycle INT i-1 The output result is the same as the previous cycle INT i The output result is added as the current cycle INT i The output result is stored in the register; INT L+1 The full adder in the previous cycle INT L The output result is the same as the previous cycle INT L+1 The output result is added as the current cycle INT L+1 The output result is obtained and stored in a register; wherein i is a natural number and 1<i≤L, and L is the order of the analog loop filter; The number of output bits of the register in each digital integrator is determined by the number of cycles M of a Nyquist conversion of the incremental scaling analog-to-digital converter, the number of bits N of the successive approximation ADC, and the number of stages j of the digital integrator, and specifically satisfies the following relationship: n j >log2((2 N -1)M j / j!) Where: n j represents the number of output bits of the register in the j-th digital integrator, ! represents the factorial, j is a natural number and 1≤j≤L+1.

2. The method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology according to claim 1, characterized in that: The pseudo-random sequence generator is synthesized by hardware description language and generates a random sequence obeying Gaussian distribution.

3. The method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology according to claim 1, characterized in that: The effective value of the jitter voltage is 0.5V LSB , where V LSB =V FS / 2 N , V FS is the full amplitude of the successive approximation ADC, and N is the number of bits of the successive approximation ADC.

4. The method for improving the signal-to-noise ratio of an incremental scaling analog-to-digital converter based on dithering technology according to claim 1, characterized in that: The SNR improvement method utilizes the random distribution characteristics of quantization noise and reduces the quantization error of the incremental scaling analog-to-digital converter from E×(L! / M by summing and averaging the quantization noise. L ) is reduced to E sum ×[(L+1)! / M (L+1) ], where E is the quantization error of each cycle of the incremental scaling analog-to-digital converter, E sum It is the sum of the quantization errors of the incremental scaling analog-to-digital converter within M cycles.

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