Time reference correction system and clock establishment and maintenance method

Abstract

The invention discloses a time reference correction system, which comprises a clock initialization module and a virtual clock module, and is characterized in that the clock initialization module is connected with the virtual clock module; the clock initialization module comprises a GPS device, a 5G communication module, an RTC clock, a counter capture channel, a credibility calculation module, a priority selector and an oscillator. The invention further comprises a clock establishment method of the time reference correction system, the composition of the system is improved and optimized, based on an embedded system scheme, a new time reference correction system is formed in a software and hardware combination mode, a GPS and a 5G time service source are combined, the time service jitter behavior generated due to environment willing during independent GPS time service is eliminated, and the time service accuracy is improved. The method has the advantages that no accumulated error exists, no jitter error exists in a local vibrator, a periodic quasi-local oscillator is calibrated through a GPS time service source or a 5G network time service source, and local time and coordinated world time are kept synchronous.

Description

Technical Field

[0001] The invention belongs to the field of manufacturing, and in particular relates to a time reference correction system and a clock establishment and maintenance method. Background Art

[0002] The autonomous driving algorithm needs to process the information status of all sensors on the vehicle at the same time in order to make driving behavior decisions, which makes the autonomous driving car very dependent on the time synchronization of the entire vehicle. The current solution is that the GPS device converts the satellite's timing signal into a second pulse signal and a message signal, and then translates the satellite's timing information into a network PTP timing message to provide timing and synchronization to the sensor equipment on the vehicle. This solution is prone to time deviations between sensors with different interfaces. In addition, since this solution directly uses the GPS timing source, once the GPS timing source is affected by the driving conditions, it is very easy to cause the PPS pulse signal to jitter, causing the whole vehicle time synchronization to jump, affecting the decision-making of the autonomous driving algorithm.

[0003] The current plan is Figure 1 As shown, 𝑡1 represents the GPS timing time, Indicates the jitter time of GPS itself, Indicates the fixed delay of the network synchronization device itself. represents the fixed delay of the CAN synchronization device itself, because , causing the timing between different hardware interface devices to be out of sync; In addition, the PPS (1Hz full-second pulse signal) signal of the GPS timing device on the current self-driving car directly synchronizes the time of the entire vehicle, but the quality of the GPS signal is easily affected by weather and driving conditions, causing the output PPS signal to jitter. When the vehicle enters a tunnel or under an overpass, it is easy for the vehicle's timing to be inaccurate and the timing timestamp to be discontinuous, which brings potential harm to the self-driving car.

[0004] In addition, the GPS timing clock is not processed in any way and directly uses several conversion devices to provide timing to different sensors of the vehicle, resulting in discontinuous and asynchronous time jumps between the sensors of the entire vehicle. Summary of the invention

[0005] Purpose of the invention: In order to overcome the above shortcomings, the purpose of the present invention is to provide a time reference correction system, which improves and optimizes the composition of the system, is based on an embedded system solution, and constitutes a new time reference correction system through a combination of software and hardware. It combines GPS and 5G timing sources, eliminates the timing jitter behavior caused by the environment when GPS timing is alone, has the advantages of no cumulative error and no jitter error of the local vibrator, and periodically calibrates the local oscillator through the GPS timing source or the 5G network timing source to keep the local time synchronized with the coordinated universal time.

[0006] Technical solution: In order to achieve the above-mentioned purpose, the present invention provides a time reference correction system, including: system external hardware devices, gateway hardware entities and control chips, the system external hardware devices include GPS devices, a group of sensors, the gateway hardware entity includes a 5G communication module, an RTC clock and a trusted data processing module, wherein the trusted data processing module includes a group of trust calculation modules, a priority selector and a coordinated world time parser; The control chip includes a group of counter capture channels, oscillators and virtual clock modules. The GPS device, 5G communication module and RTC clock are respectively connected to the corresponding technical capture channels by telecommunications. Each counter capture channel is connected to the corresponding trust calculation module, and an output end of the trust calculation module is connected to the priority selector. Another port of the GPS device, 5G communication module and RTC clock is connected to UTC through a coordinated world time resolver. Another output port of the trust calculation module is connected to the coordinated world time resolver, and the output port of the coordinated world time resolver is connected to the priority selector. The output end of the priority selector is connected to the virtual clock module; The ports of the oscillator are respectively connected to the counter capture channel connected to the GPS device and the 5G communication module and the virtual clock module.

[0007] The virtual clock module includes a time processing module and a group of Ethernet communication modules, the output end of the priority selector is connected to the input end of the time processing module, and the output end of the time processing module is connected to the corresponding sensor through the Ethernet communication module.

[0008] Furthermore, the time processing module includes a time register and a timer, the time register uses a year-month-day-minute-second register, and the timer uses a system sub-second timer.

[0009] Preferably, an edge capture calculator is provided in the counter capture channel.

[0010] The clock establishment and maintenance method of the time reference correction system described in the present invention has the following specific steps: 1): The local RTC clock will periodically send out 1Hz PPS pulses and timing information; 2): The PPS pulse is sent to the counter capture channel in the SOC. The counter in the counter capture channel automatically accumulates with 10MHz as the clock source. Once the PPS edge triggers the capture channel, the counter value will be captured; 3): After each channel captures two edges, the count difference is sent to the trust calculation module of the channel; 4): The trust calculation module compares the standard deviation of the counter difference with the empirical value obtained through training. According to statistical theory, a new counter difference is considered to be a true and valid signal when the deviation between it and the training value is between ±3σ. The trust calculation module will release the counter difference of the channel to enter the priority selector. 5): The priority selector will send the highest precision data to the local time maintenance system according to the precision priority, and update the clock of the system's internal time processing module; 6): The system stores the year, month, day, hour, minute and second in BCD code in the local year, month, day, hour and minute registers, which are updated once per second. The sub-second is maintained by the 32-bit physical timer inside the system. When the second bit is updated, the difference between the currently selected trusted channel counter value and the counter value at the time of triggering is written into the sub-second timer to calibrate the data processing time of the SOC itself; the source of the sub-second timer is the same as the clock source of the capture channel, both of which are 10MHz. The timestamp accuracy of the internal timing source can reach 100ns. At this point, the internal system clock has been established.

[0011] The timing process of the time reference correction system is as follows: when the system provides external time, the corresponding interface driver layer directly accesses the local time register 91 and sub-second timer 92, and multiplies the value of the sub-second timer 92 by a deviation correction coefficient before providing a timing timestamp for the external device.

[0012] The clock establishment and maintenance method of the time reference correction system described in the present invention is that the system is in a blank state at the beginning of the time reference correction system, and it is necessary to provide an empirical data as the boundary condition of the entire algorithm for subsequent iterative behavior. After the system is powered on, the clock initialization process is first executed once and then the clock maintenance process is entered. The specific clock initialization process is as follows: 1): Initialize three channel timers, set the clock source of the timer to a 10MHz homologous clock, set the mode of the timer to capture mode, and set three timer overflow interrupts at the same time, and record the carry behavior of the timer; 2): Wait for the peripheral initialization to succeed, that is, to provide an empirical data as the boundary condition of the entire algorithm for subsequent iterative behavior. After the system is powered on, the clock initialization process is first executed and then the clock maintenance process is entered; 3): The three channels start to capture the PPS signals of the GPS device (1), 5G communication module (2), and RTC clock (3). Each time the PPS rising edge arrives, the value of the counter is recorded. 𝑥,𝑏 , then calculate the counter difference between the two trigger edges and find 𝐶 according to formula 1 𝑥𝑏 , and record it as 𝐶 𝑥𝑏 : Formula 1 Among them, C represents the difference between the counter being triggered twice by the PPS edge, x represents the channel number, and b represents the pulse number; After recording 11 trigger times, calculate the average value of the counter according to the following formula 2 and formula 3 𝑥 and standard deviation 𝜎 𝑥 , Formula 2 Formula 3 x represents the channel number and is recorded; 4): Set the judgment conditions according to the actual hardware indicators. The PPS pulse jitter of the GPS device should not be greater than 10us when it is normal. For the 5G device, the PPS pulse jitter should not be greater than 30us when it is normal. Because the clock source of the counter is 10MHz, the theoretical equivalent clock period is 0.1us. The standard deviation 𝜎1 of channel 1 should not be greater than 100, and 𝜎2 of channel 2 should not be greater than 300; if the standard deviation 𝜎 𝑥 If the value is greater than the set value, the data is considered invalid, the first pulse is discarded, and the mean and standard deviation are recalculated at the 11th pulse interval until a timeout is issued; The trustworthiness calculation module (5) will mark the data of this channel as untrustworthy, and the data will be replaced by the default empirical value of the program, that is, the worst indicator of the hardware specification. Otherwise, the TMP of the corresponding channel will directly use the calculated 𝜇 𝑥 with 𝜎 𝑥 Perform subsequent iterations; channel 2 calculates the deviation value from the trigger counters of channel 1 and channel 0 according to the PPS edge error calculation formula 4 between channels, and converts the last deviation 𝛥 𝑥 Sent to the priority selector, x represents the channel number; Formula 4; 5): The priority selector selects the average value of the highest priority channel counter 𝜇 according to the trust indication given by the TPM module 𝑥The whole second part of the synchronization message corresponding to the hardware interface is written into the system local register in the format of BCD code, and the current count value of the selected trusted channel is subtracted from the value of the counter when it is triggered to obtain ∆𝑇, see formula 9, ∆ will be written into the system's 32-bit sub-second timer to eliminate the error generated in the system processing process and maintain the accuracy of the sub-second timer; in addition, the correction coefficient N is calculated according to the correction formula 5. The correction coefficient represents the ratio of the pulse count of 1s absolute time to the theoretical number of pulses of the local clock. The calculation formula of the system clock correction coefficient is as follows: Formula 5 6): Step 6: Transmit the correction coefficient N to the timing driver layer. When the driver layer sends time to the external device, the driver layer directly obtains the value of the internal timer and automatically multiplies it by the correction coefficient N to obtain the real UTC time, completing the time synchronization of the external device; 7): Overwrite the local RTC clock. In order to synchronize the local RTC clock with the most trusted time source, the 𝛥 in step 4 needs to be written. 𝑥 The parameter is used as a delay parameter to force the PPS clock edge of the local RTC clock to align with the PPS edge with the highest priority. Otherwise, when the reliability selector switches the clock source, sub-second time jitter will be generated, causing the timing accuracy of the entire system to decrease. 8): After overwriting the local RTC clock, start the local PPS signal to complete the system clock initialization process.

[0013] The timing process of the time reference correction system in the present invention is as follows: when the system provides external time, the corresponding interface driver layer directly accesses the local time register and sub-second timer, and multiplies the value of the sub-second timer by a deviation correction coefficient before providing a timing timestamp for the external device.

[0014] The clock establishment and maintenance method of the time reference correction system described in the present invention, the clock maintenance process is as follows: 1): The three capture channels recapture the new pulse edge and record the difference between the current counter and the previous counter. ; 2): Channel 0 and channel 1 make a trust judgment channel through the trust judgment formula 6. The channel data that does not meet the trust will be discarded, and an untrustworthy indication will be given to allow the subsequent priority selector to shield the data of the untrusted channel. Channel 2 belongs to the local oscillator and is not affected by the external environment. There is no need to make a trust judgment and it is always in the lowest priority state. After each trigger, the trustworthiness of channel 2, channel 1 and channel 0 needs to be calculated according to formula 4. , used for PPS edge alignment calibration in subsequent steps; Formula 6 3): When the trust condition is met, the average value of this channel is iterated again according to the moving window average iteration formula 7 and the moving window standard deviation iteration formula 8 With standard deviation ; Formula 7 and Formula 8 are as follows: Formula 7 Formula 8; 4): The priority selector selects the average value of the highest priority channel counter based on the trust indication given by the TPM module The whole second part of the timing message corresponding to the hardware interface is written into the system local register in the format of BCD code, and the current count value of the selected trusted channel is subtracted from the value of the counter when it is triggered to obtain ∆𝑇, see formula 9 for the error generated by the system processing data, ∆𝑇 will be written into the system's 32-bit sub-second timer to eliminate the error generated in the system processing process and maintain the accuracy of the sub-second timer; the correction coefficient 𝑁′ is calculated according to the correction formula 5, and the correction coefficient represents the ratio of the pulse count of 1s absolute time to the theoretical number of pulses of the local clock; the formula 9 for the error generated by the system processing data is as follows: Formula 9; where 𝐸 𝑥,𝑏 Indicates the counter value of the channel when triggered, 𝑆 𝑥 The value of the channel counter after processing the channel data field message; 5): The correction coefficient 𝑁′ is transmitted to the timing driver layer. When timing is provided to external devices, the driver layer directly obtains the value of the internal timer and automatically multiplies it by the correction coefficient 𝑁′ to obtain the real UTC time, thus completing the time synchronization of the external device. 6): Overwrite the local RTC clock. In order to synchronize the local RTC clock with the most trusted time source, you need to replace the time in step 2 with the time in step 2. The parameter is used as a delay parameter to force the PPS clock edge of the local RTC to be aligned with the PPS edge with the highest priority. Otherwise, when the reliability selector switches the clock source, sub-second time jitter will be generated, causing the timing accuracy of the entire system to decrease. 7): After overwriting the local RTC clock, restart the local PPS signal to complete a system time maintenance process.

[0015] It can be seen from the above technical solution that the present invention has the following beneficial effects: 1. The time reference correction system described in the present invention improves and optimizes the composition of the system, is based on an embedded system solution, and constitutes a new time reference correction system through a combination of software and hardware. It combines GPS and 5G timing sources, eliminates the timing jitter behavior caused by the environment when using GPS timing alone, has the advantages of no cumulative error and no jitter error of the local vibrator, and periodically calibrates the local oscillator through the GPS timing source or the 5G network timing source to keep the local time synchronized with the coordinated universal time.

[0016] 2. The internal clock of the system is constructed by the sliding average method, which effectively isolates the jitter behavior of the timing source and improves the time accuracy of the timing. The larger the sliding average window, the smaller the jitter of the timing, but it consumes more computing resources. However, the window size is adjustable by the algorithm, and the window size can be adjusted according to the computing power of different systems to achieve a balance between accuracy and resources.

[0017] 3. The present invention automatically corrects time deviations through iterative learning, and becomes more stable as the system is used for a longer period of time; it can adapt to external environmental factors and effectively reduce the system's dependence on the environment.

[0018] 4. The present invention utilizes 5G signals to effectively increase the accuracy and stability of the timing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the prior art mentioned in the background technology part of the present invention; Figure 2 Composition for the invention in the present invention; Figure 3 This is a flow chart of the algorithm of the clock correction system in the present invention; In the figure: GPS device 1, 5G communication module 2, RTC clock 3, a set of counter capture channels 4, a set of trust calculation modules 5, priority selector 6, coordinated world time parser 7, oscillator 8, time processing module 9, Ethernet communication module 10, time register 91, sub-second timer 92. DETAILED DESCRIPTION

[0020] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments.

[0021] Example like Figures 2 to 3A time reference correction system shown includes: a system external hardware device, a gateway hardware entity and a control chip, wherein the system external hardware device includes a GPS device 1 and a group of sensors 10, and the gateway hardware entity includes a 5G communication module 2, an RTC clock 3 and a trusted data processing module, wherein the trusted data processing module includes a group of trustworthiness calculation modules 5, a priority selector 6 and a coordinated universal time parser 7; The control chip includes a group of counter capture channels 4, an oscillator 8 and a virtual clock module. The GPS device 1, the 5G communication module 2, and the RTC clock 3 are respectively connected to the corresponding technical capture channels 4 by telecommunications. Each counter capture channel 4 is connected to the corresponding trust calculation module 5, and an output end of the trust calculation module 5 is connected to the priority selector 6. Another port of the GPS device 1, the 5G communication module 2, and the RTC clock 3 is connected to UTC through the coordinated world time resolver 7, another output port of the trust calculation module 5 is connected to the coordinated world time resolver 7, and the output port of the coordinated world time resolver 7 is connected to the priority selector 6; The output end of the priority selector 6 is connected to the virtual clock module; The ports of the oscillator 8 are respectively connected to the counter capture channel 4 and the virtual clock module connected to the GPS device 1 and the 5G communication module 2. It should be noted that the trusted data processing module is an embedded module.

[0022] It should be noted that Figure 1 The middle counter capture channel 4 is Edge capture-CH0 / 1 / 2, the trust calculation module 5 is TPM / 1 / 2, the priority selector 6 is SWITCH, the coordinated universal time parser 7 is the UTC chip (Coordinated Universal Time), the oscillator 8 is XO 10MHz; the time register 91 is YMDHMS T 1; Sub-second timer 92 is SYSTEM TIMER Sub-second.

[0023] In this embodiment, the virtual clock module includes a time processing module 9 and a group of Ethernet communication modules 10. The output end of the priority selector 6 is connected to the input end of the time processing module 9, and the output end of the time processing module 9 is connected to the corresponding sensor through the Ethernet communication module 10; the time processing module 9 includes a time register 91 and a sub-second timer 92. The time register 91 adopts a year-month-day-minute-second register, and the sub-second timer 92 adopts a system sub-second timer.

[0024] The counter capture channel 4 of the present invention is provided with an edge capture calculator.

[0025] The clock establishment and maintenance method of the time reference correction system described in this embodiment has the following specific steps: 1): The local RTC clock 3 will periodically send out 1Hz PPS (Pulse Per Second, frequency 1Hz) pulses and timing information; 2): The PPS pulse is sent to the counter capture channel 4 in the SOC. The counter in the counter capture channel 4 automatically accumulates with 10MHz as the clock source. Once the PPS edge triggers the capture channel 4, the value of the counter will be captured; 3): After each channel captures two edges, the count difference is sent to the trust calculation module 5 of the channel; 4): The trust calculation module 5 compares the standard deviation of the counter difference with the empirical value obtained through training. According to statistical theory, a new counter difference is considered to be a true and valid signal when the deviation between the new counter difference and the training value is between ±3σ. The trust calculation module 5 will release the counter difference of the channel to enter the priority selector 6. 5): The priority selector 6 will send the data with the highest accuracy to the local time maintenance system according to the accuracy priority, and update the clock of the time processing module 9 inside the system; 6): The system stores the year, month, day, hour, minute and second in BCD code in the local year, month, day, hour and minute registers, which are updated once per second. The sub-second is maintained by the 32-bit physical timer 92 inside the system. When the second bit is updated, the difference between the currently selected trusted channel counter value and the counter value at the time of triggering is written into the sub-second timer to calibrate the data processing time of the SOC itself; the source of the sub-second timer is the same as the clock source of the capture channel, both of which are 10MHz. The timestamp accuracy of the internal timing source can reach 100ns. At this point, the internal system clock has been established.

[0026] It should be noted that the training process in step 5) is to capture the first 10 PPS pulses when the power is turned on, and calculate the reference average value μ and standard deviation σ. The subsequent μ and σ are updated through continuous iteration of valid pulses.

[0027] The clock establishment and maintenance method of the time reference correction system described in this embodiment is that the system is in a blank state at the beginning of the time reference correction system, and it is necessary to provide an empirical data as the boundary condition of the entire algorithm for subsequent iterative behavior. After the system is powered on, the clock initialization process is first executed once and then the clock maintenance process is entered. The specific clock initialization process is as follows: 1): Initialize three channel timers, set the clock source of the timer to a 10MHz homologous clock, set the mode of the timer to capture mode, and set three timer overflow interrupts at the same time, and record the carry behavior of the timer; 2): Wait for the peripheral initialization to succeed, that is, to provide an empirical data as the boundary condition of the entire algorithm for subsequent iterative behavior. After the system is powered on, the clock initialization process is first executed and then the clock maintenance process is entered; 3): The three channels start to capture the PPS signals of GPS device 1, 5G communication module 2, and RTC clock 3, and record the value of the counter every time the PPS rising edge arrives 𝑥,𝑏 , then calculate the counter difference between the two trigger edges and find 𝐶 according to formula 1 𝑥𝑏 , and record it as 𝐶 𝑥𝑏 : Formula 1 Among them, C represents the difference between the counter being triggered twice by the PPS edge, x represents the channel number, and b represents the pulse number; After recording 11 trigger times, calculate the average value of the counter according to the following formula 2 and formula 3 𝑥 and standard deviation 𝜎 𝑥 , Formula 2 Formula 3 x represents the channel number and is recorded; 4): Set the judgment conditions according to the actual hardware indicators. The PPS pulse jitter of GPS device 1 should not be greater than 10us when it is normal. For 5G device 2, the PPS pulse jitter should not be greater than 30us when it is normal. Because the clock source of the counter is 10MHz, the theoretical equivalent clock period is 0.1us. The standard deviation 𝜎1 of channel 1 should not be greater than 100, and 𝜎2 of channel 2 should not be greater than 300. If the standard deviation 𝜎 𝑥 If the value is greater than the set value, the data is considered invalid, the first pulse is discarded, and the mean and standard deviation are recalculated at the 11th pulse interval until a timeout is issued; The trustworthiness calculation module (5) will mark the data of this channel as untrustworthy, and the data will be replaced by the default empirical value of the program, that is, the worst indicator of the hardware specification. Otherwise, the TMP of the corresponding channel will directly use the calculated 𝜇 𝑥 with 𝜎 𝑥 Perform subsequent iterations; channel 2 calculates the deviation value from the trigger counters of channel 1 and channel 0 according to the PPS edge error calculation formula 4 between channels, and converts the last deviation 𝛥 𝑥 Sent to the priority selector, x represents the channel number; Formula 4; 5): The priority selector selects the average value of the highest priority channel counter 𝜇 according to the trust indication given by the TPM module 𝑥The whole second part of the synchronization message corresponding to the hardware interface is written into the system local register in the format of BCD code, and the current count value of the selected trusted channel is subtracted from the value of the counter when it is triggered to obtain ∆𝑇, see formula 9, ∆ will be written into the system's 32-bit sub-second timer to eliminate the error generated in the system processing process and maintain the accuracy of the sub-second timer; in addition, the correction coefficient N is calculated according to the correction formula 5. The correction coefficient represents the ratio of the pulse count of 1s absolute time to the theoretical number of pulses of the local clock. The calculation formula of the system clock correction coefficient is as follows: Formula 5 6): Step 6: Transmit the correction coefficient N to the timing driver layer. When the driver layer sends time to the external device, the driver layer directly obtains the value of the internal timer and automatically multiplies it by the correction coefficient N to obtain the real UTC time, completing the time synchronization of the external device; 7): Overwrite the local RTC clock. In order to synchronize the local RTC clock 3 with the most trusted time source, the 𝛥 in step 4 needs to be written. 𝑥 The parameter is used as a delay parameter to force the PPS clock edge of the local RTC clock 3 to be aligned with the PPS edge with the highest priority. Otherwise, when the reliability selector switches the clock source, sub-second time jitter will be generated, causing the timing accuracy of the entire system to decrease. 8): After overwriting the local RTC clock 3, start the local PPS signal and complete the system clock initialization process. It should be noted that the empirical data in step 2) refers to the standard deviation σ of the PPS pulse period of the external time source device under normal conditions. This indicator is usually given by the manufacturer of the timing equipment, and most of them are between hundreds of ns and 1us. Each manufacturer will be different.

[0028] In addition, the timer in step 1) refers to a pulse period capture timer, which is a timer used to calculate the pulse period; the sub-second timer is a timer used to maintain the internal clock.

[0029] The clock establishment and maintenance method of the time reference correction system described in this embodiment, the clock maintenance process is as follows: 1): The three capture channels recapture the new pulse edge and record the difference between the current counter and the previous counter. ; 2): Channel 0 and channel 1 make a trust judgment channel through the trust judgment formula 6. The channel data that does not meet the trust will be discarded, and an untrustworthy indication will be given to allow the subsequent priority selector to shield the data of the untrusted channel. Channel 2 belongs to the local oscillator and is not affected by the external environment. There is no need to make a trust judgment and it is always in the lowest priority state. After each trigger, the channel 2, channel 1 and channel 0 need to be calculated according to formula 4. , used for PPS edge alignment calibration in subsequent steps; Formula 6 3): When the trust condition is met, the average value of this channel is iterated again according to the moving window average iteration formula 7 and the moving window standard deviation iteration formula 8 With standard deviation ; Formula 7 and Formula 8 are as follows: Formula 7 Formula 8; 4): The priority selector selects the average value of the highest priority channel counter based on the trust indication given by the TPM module The whole second part of the timing message corresponding to the hardware interface is written into the system local register in the format of BCD code, and the current count value of the selected trusted channel is subtracted from the value of the counter when it is triggered to obtain ∆𝑇, see formula 9 for the error generated by the system processing data, ∆𝑇 will be written into the system's 32-bit sub-second timer to eliminate the error generated in the system processing process and maintain the accuracy of the sub-second timer; the correction coefficient 𝑁′ is calculated according to the correction formula 5, and the correction coefficient represents the ratio of the pulse count of 1s absolute time to the theoretical number of pulses of the local clock; the formula 9 for the error generated by the system processing data is as follows: Formula 9; where 𝐸 𝑥,𝑏 Indicates the counter value of the channel when triggered, 𝑆 𝑥 The value of the channel counter after processing the channel data field message; 5): The correction coefficient 𝑁′ is transmitted to the timing driver layer. When timing is provided to external devices, the driver layer directly obtains the value of the internal timer and automatically multiplies it by the correction coefficient 𝑁′ to obtain the real UTC time, thus completing the time synchronization of the external device. 6): Overwrite the local RTC clock. In order to synchronize the local RTC clock with the most trusted time source, you need to replace the time in step 2 with the time in step 2. The parameter is used as a delay parameter to force the PPS clock edge of the local RTC to be aligned with the PPS edge with the highest priority. Otherwise, when the reliability selector switches the clock source, sub-second time jitter will be generated, causing the timing accuracy of the entire system to decrease. 7): After overwriting the local RTC clock, restart the local PPS signal to complete a system time maintenance process.

[0030] It should be noted that the internal clock of the system is constructed by the sliding average method of formula 7 and formula 8 in step 2), which effectively isolates the jitter behavior of the timing source and improves the time accuracy of the timing. The larger the sliding average window, the smaller the jitter of the timing, but it consumes more computing resources. However, the window size is adjustable by the algorithm, and the window size can be adjusted according to the computing power of different systems to achieve a balance between accuracy and resources.

[0031] In the actual working process, it should be noted that the time base of the GPS receiver comes from the atomic clock of the satellite, which can be considered as a clock without deviation. However, the signal of the GPS receiver will be affected by external environmental factors, and the clock signal output will occasionally jitter. Once the jitter disappears, the accuracy of the timing will return to normal. It can be considered that the GPS timing source will not have cumulative errors. The local RTC and XO oscillators are composed of temperature compensated oscillators, which can be considered to be basically unaffected by environmental changes, but there is a deviation in the absolute accuracy of the local RTC and XO. If no calibration is performed, the deviation between the local time and the real coordinated time of GPS will become larger and larger over time. It can be considered that the local oscillator will not have jitter errors. The present invention combines the advantages of both. When the GPS signal is judged to be valid by TPM (Trusted Parameter Module), the system will use the precise time of GPS to build the local system clock, and calibrate the RTC module with a higher precision source. When the GPS signal is judged to be invalid by TPM (Trusted Parameter Module), SWITCH (priority selector) automatically switches to 5G timing. The architecture of the present invention adds a 5G communication module, and uses the timing message SIB9 of the 5G network to perform local time calibration, which increases the redundancy and robustness of the entire timing correction system. When both the GPS and 5G modules are judged to be untrustworthy by TMP, SWITCH (priority selector) automatically switches to the local RTC timing source to maintain the local system clock without jitter.

[0032] The above description is only a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements without departing from the principle of the present invention, and these improvements should also be regarded as within the protection scope of the present invention.

Claims

1. A time reference correction system, characterized in that: include: System external hardware devices, gateway hardware entities and control chips, wherein the system external hardware devices include a GPS device (1) and a group of sensors (10), and the gateway hardware entity includes a 5G communication module (2), an RTC clock (3) and a trusted data processing module, wherein the trusted data processing module includes a group of trustworthiness calculation modules (5), a priority selector (6) and a coordinated universal time parser (7); The control chip comprises a group of counter capture channels (4), an oscillator (8) and a virtual clock module; the GPS device (1), the 5G communication module (2) and the RTC clock (3) are respectively connected to the corresponding technical capture channels (4) by telecommunication; each counter capture channel (4) is connected to the corresponding trustworthiness calculation module (5); and an output end of the trustworthiness calculation module (5) is connected to the priority selector (6); another port of the GPS device (1), the 5G communication module (2) and the RTC clock (3) is connected to UTC via a coordinated world time resolver (7); another output port of the trustworthiness calculation module (5) is connected to the coordinated world time resolver (7); and an output port of the coordinated world time resolver (7) is connected to the priority selector (6); The output end of the priority selector (6) is connected to the virtual clock module; The ports of the oscillator (8) are respectively connected to the counter capture channel (4) connected to the GPS device (1) and the 5G communication module (2) and the virtual clock module.

2. The time reference correction system according to claim 1, characterized in that: include: The virtual clock module comprises a time processing module (9), the output end of the priority selector (6) is connected to the input end of the time processing module (9), the CAN-MAC, RGMII and UART terminals at the output end of the time processing module (9) are connected to the corresponding external sensors (10) via CAN-PHY, ETH-PHY and RS232-PHY respectively, and the PWM and RS232-PHY at the output end of the time processing module (9) are simultaneously connected to an external sensor (10).

3. The time reference correction system according to claim 2, characterized in that: include: The time processing module (9) comprises a time register (91) and a sub-second timer (92), wherein the time register (91) adopts a year-month-day-minute-second register, and the sub-second timer (92) adopts a system sub-second timer.

4. The time reference correction system according to claim 1, characterized in that: include: An edge capture calculator is provided in the counter capture channel (4).

5. The clock establishment and maintenance method of the time reference correction system according to claim 3, characterized in that: The specific steps are as follows: 1): The local RTC clock (3) will periodically send out 1Hz PPS pulses and timing information; 2): The PPS pulse is sent to the counter capture channel (4) in the SOC. The counter in the counter capture channel (4) automatically accumulates with 10MHz as the clock source. Once the PPS edge triggers the capture channel (4), the value of the counter will be captured; 3): After each channel captures two edges, the count difference is sent to the trust calculation module of the channel (5); 4): The trust calculation module (5) compares the standard deviation of the counter difference with the empirical value obtained through training. According to statistical theory, a new counter difference is considered to be a true and valid signal when the deviation between the new counter difference and the training value is within ±3σ. The trust calculation module (5) will release the counter difference of the channel to enter the priority selector (6). 5): The priority selector (6) will send the highest precision data to the local time maintenance system according to the precision priority, and update the clock of the system's internal time processing module (9); 6): The system stores the year, month, day, hour, minute, and second in BCD code in the local year, month, day, hour, minute register, which is updated once a second. The sub-second is maintained by the 32-bit physical sub-second timer (92) inside the system. When the second bit is updated, the difference between the currently selected trusted channel counter value and the counter value at the time of triggering is written into the sub-second timer to calibrate the data processing time of the SOC itself. The source of the sub-second timer is the same as the clock source of the capture channel, both of which are 10MHz. The timestamp accuracy of the internal timing source can reach 100ns. At this point, the internal system clock has been established.

6. The clock establishment and maintenance method of the time reference correction system according to claim 5, characterized in that: The timing process of the time reference correction system is as follows: when the system provides external time, the corresponding interface driver layer directly accesses the local time register (91) and the sub-second timer (92), and multiplies the value of the sub-second timer (92) by a deviation correction coefficient before providing a timing timestamp for the external device.

7. The clock establishment and maintenance method of the time reference correction system according to claim 5, characterized in that: The time reference correction system is in a blank state at the beginning. It is necessary to provide an empirical data as the boundary condition of the entire algorithm for subsequent iterative behavior. After the system is powered on, the clock initialization process is first executed and then the clock maintenance process is entered. The specific clock: The initialization process is as follows: 1): Initialize three channel timers, set the timer clock source to the 10MHz homologous clock, set the timer mode to capture mode, set three timer overflow interrupts at the same time, and record the timer carry behavior; 2): Wait for the peripheral initialization to succeed, that is, to provide an empirical data as the boundary condition of the entire algorithm for subsequent iterative behavior. After the system is powered on, the clock initialization process is first executed and then the clock maintenance process is entered; 3): The three channels start to capture the PPS signals of the GPS device (1), 5G communication module (2), and RTC clock (3). Each time the PPS rising edge arrives, the value of the counter is recorded. 𝑥,𝑏 , then calculate the counter difference between the two trigger edges and find 𝐶 according to formula 1 𝑥𝑏 , and record it as 𝐶 𝑥𝑏 : Formula 1 Among them, C represents the difference between the counter being triggered twice by the PPS edge, x represents the channel number, and b represents the pulse number; After recording 11 trigger times, calculate the average value of the counter according to the following formula 2 and formula 3 𝑥 and standard deviation 𝜎 𝑥 , Formula 2 Formula 3 x represents the channel number and is recorded; 4): Set the judgment conditions according to the actual hardware indicators. For GPS devices (1), the PPS pulse jitter should not be greater than 10us during normal timing. For 5G devices (2), the PPS pulse jitter should not be greater than 30us during normal timing. Because the clock source of the counter is 10MHz, the theoretical equivalent clock period is 0.1us. The standard deviation 𝜎1 of channel 1 should not be greater than 100, and 𝜎2 of channel 2 should not be greater than 300. If the standard deviation 𝜎 𝑥 If the value is greater than the set value, the data is considered invalid, the first pulse is discarded, and the mean and standard deviation are recalculated at the 11th pulse interval until a timeout is issued; The trust calculation module (5) will mark the data of the channel as untrustworthy, and the data will be replaced by the default experience value of the program, that is, the worst indicator of the hardware specification. Otherwise, the trust calculation module (5) of the corresponding channel will directly use the calculated 𝜇 𝑥 with 𝜎 𝑥 Perform subsequent iterations; channel 2 calculates the deviation value from the trigger counters of channel 1 and channel 0 according to the PPS edge error calculation formula 4 between channels, and converts the last deviation 𝛥 𝑥 Sent to the priority selector, x represents the channel number; Formula 4: 5): The priority selector (5) selects the average value 𝜇 of the highest priority channel counter according to the trust indication given by the TPM module 𝑥 The whole second part of the synchronization message corresponding to the hardware interface is written into the system local register in the format of BCD code, and the current count value of the selected trusted channel is subtracted from the value of the counter when it is triggered to obtain ∆𝑇, see formula 9, ∆ will be written into the system's 32-bit sub-second timer (92), eliminating the error generated in the system processing process and maintaining the accuracy of the sub-second timer (92); in addition, the correction coefficient N is calculated according to the correction formula 5. The correction coefficient represents the ratio of the pulse count of 1s absolute time to the theoretical number of pulses of the local clock. The calculation formula of the system clock correction coefficient is as follows: Formula 5 6): Step 6: Transmit the correction coefficient N to the timing driver layer. When the driver layer sends time to the external device, the driver layer directly obtains the value of the internal timer and automatically multiplies it by the correction coefficient N to obtain the real UTC time, completing the time synchronization of the external device; 7): Overwrite the local RTC clock. In order to synchronize the local RTC clock (3) with the most trusted time source, the 𝛥 in step 4 needs to be written. 𝑥 The parameter is used as a delay parameter to force the PPS clock edge of the local RTC clock (3) to be aligned with the PPS edge with the highest priority. Otherwise, when the reliability selector switches the clock source, sub-second time jitter will be generated, causing the timing accuracy of the entire system to decrease. 8): After overwriting the local RTC clock (3), start the local PPS signal and complete the system clock initialization process.

8. The clock establishment and maintenance method of the time reference correction system according to claim 5, characterized in that: The clock maintenance process is as follows: 1): The three capture channels recapture the new pulse edge and record the difference between the current counter and the previous counter. ; 2): Channel 0 and channel 1 make a trust judgment channel through the trust judgment formula 6. The channel data that does not meet the trust will be discarded, and an untrustworthy indication will be given to allow the subsequent priority selector to shield the data of the untrusted channel. Channel 2 belongs to the local oscillator and is not affected by the external environment. There is no need to make a trust judgment and it is always in the lowest priority state. After each trigger, the channel 2, channel 1 and channel 0 need to be calculated according to formula 4. , used for PPS edge alignment calibration in subsequent steps; Formula 6 3): When the trust condition is met, the average value of this channel is iterated again according to the moving window average iteration formula 7 and the moving window standard deviation iteration formula 8 With standard deviation ; Formula 7 and Formula 8 are as follows: Formula 7 Formula 8: 4): The priority selector selects the average value of the highest priority channel counter based on the trust indication given by the trust calculation module (5) The whole second part of the timing message corresponding to the hardware interface is written into the system local register in the format of BCD code, and the current count value of the selected trusted channel is subtracted from the value of the counter when it is triggered to obtain ∆𝑇, see formula 9 for the error generated by system processing data, ∆𝑇 will be written into the system's 32-bit sub-second timer to eliminate the error generated in the system processing process and maintain the accuracy of the sub-second timer; the correction coefficient 𝑁′ is calculated according to correction formula 5, and the correction coefficient represents the ratio of the pulse count of 1s absolute time to the theoretical number of pulses of the local clock; formula 9 for the error generated by system processing data is as follows: Formula 9: where 𝐸 𝑥,𝑏 Indicates the counter value of the channel when triggered, 𝑆 𝑥 The value of the channel counter after processing the channel data field message; 5): The correction coefficient 𝑁′ is transmitted to the timing driver layer. When timing is provided to external devices, the driver layer directly obtains the value of the internal timer and automatically multiplies it by the correction coefficient 𝑁′ to obtain the real UTC time, thus completing the time synchronization of the external device. 6): Overwrite the local RTC clock. In order to synchronize the local RTC clock with the most trusted time source, you need to replace the time in step 2 with the time in step 2. The parameter is used as a delay parameter to force the PPS clock edge of the local RTC to be aligned with the PPS edge with the highest priority. Otherwise, when the reliability selector switches the clock source, sub-second time jitter will be generated, causing the timing accuracy of the entire system to decrease. 7): After overwriting the local RTC clock, restart the local PPS signal to complete a system time maintenance process.

Images