Chip connection structure and chip

Abstract

The application provides a chip connecting structure and a chip, the chip connecting structure is used for connecting the chip and a circuit board, the chip is arranged above the circuit board, the chip connecting structure comprises at least one signal bonding wire, a reflow bonding wire, a first pad and a second pad; the first pad and the second pad are arranged on a first surface of the chip, the first pad is connected with a first end of the signal bonding wire, the second pad is connected with a first end of the reflow bonding wire, a second end of the signal bonding wire is connected with the circuit board, and a second end of the reflow bonding wire is connected with the circuit board; the signal bonding wire and the reflow bonding wire are arranged on the same plane, and along the direction in which the signal bonding wire extends outward from the projection point of the center point of the chip on the plane, the signal bonding wire is arranged on the outer side of the reflow bonding wire. In the direction of the center of the chip, the electromagnetic wave signal of the signal bonding wire is reflow-absorbed by the reflow bonding wire, the electromagnetic wave signal in the direction of the center of the chip is reduced, and the interference of the electromagnetic wave signal of the signal bonding wire on the chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a chip connection structure and chip for reducing signal interference. Background Technology

[0002] Chips are typically connected to circuit boards via chip interconnect structures. See also Figure 1 and Figure 2 The existing chip connection structure is used to connect chip 11 and circuit board 12. The chip is positioned above the circuit board. The chip connection structure includes a signal bonding wire 142, a return bonding wire 141, a first pad 132, and a second pad 131. The first end of the signal bonding wire 142 is connected to the first pad 132, and the second end of the signal bonding wire 142 is connected to the signal transmission terminal of the circuit board 12. The first end of the return bonding wire 141 is connected to the first end of the second pad 131, and the second end of the return bonding wire 141 is connected to the ground terminal of the circuit board 12. The first pad 132 and the second pad 131 are arranged parallel to the first side of chip 11, and the signal bonding wire 142 and the return bonding wire 141 are also arranged parallel to the first side of chip 11. The arc length and radius of curvature of the signal bonding wire 142 and the return bonding wire 141 are the same. The signal bonding wire 142 is used to output the communication signal of the chip 11, and the return bonding wire 141 is used to connect to the ground terminal, forming a transmission loop with the signal bonding wire 142.

[0003] During communication, the signal bonding wire 142 generates an electromagnetic field signal, which radiates and propagates into the surrounding space from the signal bonding wire 142. Since the existing chip connection structure's signal bonding wire 142 and return bonding wire 141 are arranged parallel to the first side of the chip 11, and the return bonding wire 141 can return the electromagnetic field signal from the signal bonding wire 142, the electromagnetic field signal propagating along the first side of the chip 11 is returned by the return bonding wire 141, thus weakening the electromagnetic field signal along the first side. However, the electromagnetic wave signal along the chip direction does not form a return current with the return bonding wire 141, allowing it to pass through the chip 11 and interfere with its internal structure. Furthermore, since the electromagnetic wave signal can pass through the chip 11 and reach the other side of the chip, it interferes with the signal transmission of the signal bonding wires on the other side of the chip 11.

[0004] A current chip packaging structure involves mounting a first chip on a substrate and forming an electrical arc between the first chip and the substrate. The electrical arc includes a connecting arc and a shielding arc. The shielding arc is formed outside the connecting arc, and multiple shielding arcs are disposed on at least two sides of the first chip. The first chip is electrically connected to the substrate through the connecting arc. The shielding arc is connected to a first conductive post. An insulating post is also disposed within the first molding compound, extending to the shielding arc. The shielding arc surrounds the first chip, thereby achieving electromagnetic shielding of the first chip, i.e., preventing electromagnetic signals from external chips from interfering with the first chip.

[0005] However, the chip packaging structure cannot prevent the electromagnetic waves generated by the electrical arc connected to the first chip from interfering with the first chip, causing the first chip to still suffer from electromagnetic wave interference from its electrical arc. Furthermore, there is also an electrical arc on the other side of the chip packaging structure, and the electromagnetic wave signal of this electrical arc can pass through the first chip, thus affecting the electrical arc on the other side. Summary of the Invention

[0006] The first objective of this invention is to provide a chip connection structure that reduces interference caused by signal bonding lines to a first chip.

[0007] A second objective of this invention is to provide a chip that utilizes the above-described chip interconnection structure.

[0008] To achieve the first objective of this invention, the present invention provides a chip connection structure for connecting a chip to a circuit board. The chip connection structure includes at least one signal bonding wire, a reflow bonding wire, a first pad, and a second pad. Both the first pad and the second pad are disposed on a first surface of the chip. The first pad is connected to a first end of the signal bonding wire, and the second pad is connected to a first end of the reflow bonding wire. The second end of the signal bonding wire is connected to the circuit board, and the second end of the reflow bonding wire is also connected to the circuit board. The signal bonding wire and the reflow bonding wire are arranged on the same plane, which extends along the length of the chip and extends outward from the projection point of the chip's center point on the plane. The signal bonding wire is disposed outside the reflow bonding wire.

[0009] As can be seen from the above scheme, since the signal bonding wire and the return bonding wire are set on the same plane, and along the direction extending outward from the projection point of the chip's center point on the plane, the signal bonding wire is located outside the return bonding wire, meaning that the signal bonding wire and the chip are separated by the return bonding wire. During communication, the chip transmits communication signals through the signal bonding wire. At this time, the signal bonding wire radiates electromagnetic wave signals into the surrounding space, and the return bonding wire provides electromagnetic wave signal return. Because the return bonding wire is close to the chip and the signal bonding wire is far from the chip, the electromagnetic wave signals propagated by the signal bonding wire are absorbed and returned by the return bonding wire along the direction extending from the signal bonding wire to the projection point of the chip's center point on the plane. This reduces the amount of electromagnetic wave signal radiated from the signal bonding wire to the chip, thus reducing interference from the signal bonding wire to the chip. Simultaneously, it reduces interference to signal bonding wires on other sides of the chip.

[0010] In a further embodiment, both the first and second pads pass through the aforementioned plane, with the first pad being closer to the vertical centerline of the chip than the second pad.

[0011] As can be seen, since the signal bonding wires and reflow bonding wires are also connected to the circuit board, the first pad is closer to the vertical center line of the chip than the second pad. This arrangement allows the signal bonding wires to not directly face the chip along the direction of the projection point of the chip center point on the plane from the signal bonding wire to the projection point of the chip center point on the plane. Along the direction of the projection point of the chip center point on the plane from the signal bonding wire to the chip center point, the signal bonding wires are spaced apart from the chip by the reflow bonding wires. The reflow bonding wires can perform signal reflow, reducing the interference of the electromagnetic field generated by the signal bonding wires on the chip.

[0012] In a further embodiment, the circuit board is provided with a signal transmission end and a ground end, the second end of the signal bonding wire is connected to the signal transmission end, and the return bonding wire is connected to the ground end.

[0013] Therefore, it can be seen that the chip can communicate with peripheral circuits through the signal transmission terminal of the circuit board, and the chip can return signals through the ground terminal.

[0014] In a further design, the grounding terminal is positioned close to the chip, while the signal transmission terminal is positioned far away from the chip.

[0015] Therefore, placing the grounding end closer to the chip makes the return bonding wires closer to the chip, while placing the signal transmission end further away from the chip makes the signal bonding wires further away from the chip.

[0016] In a further design, the first pad, the second pad, the ground terminal, and the signal transmission terminal all penetrate the plane, and the distance between them and the projection point of the chip's center point on the plane gradually increases along the length of the chip.

[0017] As can be seen, the signal bonding wire connects the first pad to the signal transmission end, and the return bonding wire connects the second pad to the ground end, thus forming a signal bonding wire surrounding the return bonding wire.

[0018] In a further embodiment, the highest point of the signal bonding wire relative to the circuit board is designated as the first highest point, and the highest point of the return bonding wire relative to the circuit board is designated as the second highest point; the distance between the first highest point and the circuit board is greater than the distance between the second highest point and the circuit board.

[0019] Therefore, it is important to ensure that the signal bonding wires and the return bonding wires do not come into contact, thereby avoiding short circuits that could burn out the chip.

[0020] In a further design, the radius of curvature of the signal bonding wire is greater than that of the reflow bonding wire.

[0021] Therefore, it can be seen that the radius of curvature of the signal bonding wire is greater than that of the return bonding wire, so that the signal bonding wire and the return bonding wire do not come into contact, thus avoiding short circuit and burning out the chip.

[0022] In a further embodiment, the signal bonding wire includes a first inclined segment, a first horizontal segment, and a second inclined segment connected in sequence; the return bonding wire includes a third inclined segment, a second horizontal segment, and a fourth inclined segment connected in sequence; and in the vertical direction, the first horizontal segment is located above the second horizontal segment.

[0023] Therefore, by positioning the first horizontal segment above the second horizontal segment, the distance between the signal bonding wire and the highest point of the circuit board is greater than the distance between the return bonding wire and the highest point of the circuit board.

[0024] To achieve the second objective, the chip provided by the present invention has a circuit board disposed below it, and the chip and the circuit board are connected by the chip connection structure described above.

[0025] In a further design, at least one chip connection structure is provided on each side of the chip.

[0026] As can be seen from the above scheme, the chip connection structure is set on each side of the chip to reduce the influence of electromagnetic wave signals generated by the signal bonding wires on the chip. Attached Figure Description

[0027] Figure 1 This is a structural diagram of the chip interconnection structure in the existing technology.

[0028] Figure 2 yes Figure 1A magnified view of point A.

[0029] Figure 3 This is a structural diagram of an embodiment of the chip connection structure of the present invention.

[0030] Figure 4 yes Figure 3 Enlarged view of point B.

[0031] Figure 5 This is a side view from another perspective of an embodiment of the chip connection structure of the present invention.

[0032] Figure 6 yes Figure 5 Enlarged view of point C.

[0033] Figure 7 This is a top view of an embodiment of the chip connection structure of the present invention.

[0034] Figure 8 This is a cross-sectional view of an embodiment of the chip connection structure of the present invention.

[0035] Figure 9 This is a simulation diagram of signal crosstalk between the chip connection structure embodiment of the present invention and the chip connection structure of the prior art.

[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0037] This invention provides a chip connection structure on a chip. The signal bonding wires and return bonding wires on the chip connection structure are arranged on the same plane, which extends along the length of the chip and extends outward from the projection point of the chip's center point on the plane. The signal bonding wires are arranged outside the return bonding wires, thereby enabling the return bonding wires to provide electromagnetic field signal return, reducing electromagnetic waves toward the chip, reducing interference from the electromagnetic wave signals of the signal bonding wires to the chip, and simultaneously reducing interference to signal bonding wires on other sides of the chip.

[0038] See Figure 3 and Figure 4 In this embodiment, the chip connection structure is used to connect chip 22 and circuit board 21. Chip 22 is disposed above circuit board 21. The chip connection structure includes at least one signal bonding line 241, a reflow bonding line 242, a first pad 231, and a second pad 232. In this embodiment, two signal bonding lines 241, two reflow bonding lines 242, a first pad 231, and a second pad 232 are provided on the first side of the chip.

[0039] First pad 231 and second pad 232 are disposed on the first surface of chip 22. First pad 231 is connected to the first end of signal bonding line 241, and second pad 232 is connected to the first end of reflow bonding line 242. The second end of signal bonding line 241 is connected to circuit board 21, and the second end of reflow bonding line 242 is also connected to circuit board 21. Specifically, circuit board 21 is provided with signal transmission terminal 221 and ground terminal 222. The second end of signal bonding line 241 is connected to signal transmission terminal 221, and reflow bonding line 242 is connected to ground terminal 222. Since chip 22 is connected to circuit board 21 through chip connection structure, chip 22 can communicate with peripheral circuits through signal transmission terminal 221 of circuit board 21, and chip 22 can perform signal reflow through ground terminal 222.

[0040] Specifically, the chip connection structure in this embodiment includes two signal bonding lines 241 and two return bonding lines 242. The two signal bonding lines 241 and the two return bonding lines 242 are arranged side by side. The first end of each of the two signal bonding lines 241 is connected to a first pad 231, and the first end of each of the two return bonding lines 242 is connected to a second pad 232. The second end of each of the two signal bonding lines 241 is connected to the signal transmission terminal 221 of the circuit board 21, and the two return bonding lines 242 are connected to the ground terminal 222 of the circuit board 21. Each signal bonding line 241 does not contact each other or the return bonding lines 242. In another embodiment, there can be two first pads 231, with the first end of one signal bonding line 241 connected to one first pad 231; there can also be two second pads 232, with the first end of each return bonding line 242 connected to one second pad 232.

[0041] See Figure 7 and Figure 8 , Figure 7 This is a top view of an embodiment of the chip interconnection structure of the present invention. A cross-section of the chip interconnection structure, chip, and circuit board is taken along plane BB of the top view, yielding... Figure 8 A cross-sectional view of the chip interconnection structure. The BB plane is the plane of this embodiment.

[0042] Both the first pad 231 and the second pad 232 pass through the plane, with the first pad 231 being closer to the vertical centerline of the chip 22 than the second pad 232. The ground terminal 222 is positioned close to the chip 22, while the signal transmission terminal 221 is positioned away from the chip 22. The first pad 231, the second pad 232, the ground terminal 222, and the signal transmission terminal 221 all pass through the plane, and their projections onto the plane from the chip's center point gradually increase along the length of the chip.

[0043] See Figure 5 , Figure 6 , Figure 7 and Figure 8 The signal bonding wire 241 and the return bonding wire 242 are arranged on the same plane. In this embodiment, see... Figure 8 This cross-section is the plane of this embodiment, extending along the length of the chip 22. Along the direction extending outward from the projection point 225 of the center point of the chip 22 onto the plane, the signal bonding wire 241 is positioned outside the reflow bonding wire 242. That is, on this plane, the overall structure of the signal bonding wire 241 does not directly face the chip 22; the reflow bonding wire 242 is spaced between the overall structure of the signal bonding wire 241 and the chip 22. Figure 8 It can be seen that the overall structure of the signal bonding wire 241 and the overall structure of the reflow bonding wire 242 are both set on the same plane, and the overall structure of the signal bonding wire 241 and the overall structure of the reflow bonding wire 242 are both cut by this plane.

[0044] Specifically, each signal bonding line 241 and its corresponding reflow bonding line 242 are arranged on the same plane. Along the direction extending outward from the center point 225 of the chip, each signal bonding line 241 is located outside its corresponding reflow bonding line 242.

[0045] Specifically, the highest point of the signal bonding wire 241 relative to the circuit board 21 is the first highest point, and the highest point of the return bonding wire 242 relative to the circuit board 21 is the second highest point; the distance between the first highest point and the circuit board 21 is greater than the distance between the second highest point and the circuit board 21. Specifically, the signal bonding wire 241 includes a first inclined segment 2411, a first horizontal segment 2412, and a second inclined segment 2413 connected in sequence; the return bonding wire 242 includes a third inclined segment 2421, a second horizontal segment 2422, and a fourth inclined segment 2423 connected in sequence. The first highest point is on the first horizontal segment 2412, and the second highest point is on the second horizontal segment 2422. Vertically, the first horizontal segment 2412 is located above the second horizontal segment 2422.

[0046] Specifically, the first inclined segment 2411, the first horizontal segment 2412, and the second inclined segment 2413 of the signal bonding line 241 are arranged on the same plane as the third inclined segment 2421, the second horizontal segment 2422, and the fourth inclined segment 2423 of the return bonding line 242.

[0047] An alternative is to have the radius of curvature of the signal bonding wire 241 be greater than that of the reflow bonding wire 242, so as to ensure that the signal bonding wire 241 and the reflow bonding wire 242 do not come into contact, thereby avoiding short circuit and burning out the chip 22.

[0048] Since the overall structure of the signal bonding line 241 is separated from the chip 22 by the return bonding line 242, the electromagnetic wave signal propagating from the signal bonding line 241 along the plane from the signal bonding line to the projection point 225 of the chip center point on the plane is absorbed by the return bonding line 242. At this time, the electromagnetic wave signal propagating from the signal bonding line 241 along the chip center direction is reduced, reducing the interference of the electromagnetic wave signal of the signal bonding line 241 to the chip 22, and at the same time, reducing the interference caused to the signal bonding lines 241 on other sides of the chip 22.

[0049] See Figure 9 , Figure 9 Curve 1 in the figure represents the simulation results of signal crosstalk of the chip under the prior art chip interconnection structure, and curve 2 represents the simulation results of signal crosstalk of the chip under the chip interconnection structure of this embodiment. As can be seen from the figure, by applying the chip interconnection structure of this embodiment, the signal crosstalk of the chip is suppressed in all simulated frequency bands, and the resonant peak value of the signal crosstalk is reduced.

[0050] Chip Example:

[0051] A circuit board 21 is disposed below the chip 22, and the chip 22 and the circuit board 21 are connected by the chip connection structure of the above-described chip connection structure embodiment. At least one chip connection structure is disposed on each side of the chip 22, so that the influence of electromagnetic wave signals generated by the signal bonding line 241 is reduced on each side of the chip.

[0052] The above are merely preferred embodiments of the present invention, but the design concept of the invention is not limited thereto. Without departing from the concept of the present invention, many other equivalent embodiments may be included. Those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the protection scope of the present invention.

Claims

1. A chip connection structure for connecting a chip to a circuit board, wherein the chip is disposed above the circuit board, and the chip connection structure includes at least one signal bonding wire, a reflow bonding wire, a first pad, and a second pad; The first pad and the second pad are both disposed on the first surface of the chip. The first pad is connected to the first end of the signal bonding line, the second pad is connected to the first end of the reflow bonding line, the second end of the signal bonding line is connected to the circuit board, and the second end of the reflow bonding line is connected to the circuit board. Its features are: Each of the signal bonding wires and its corresponding return bonding wires are arranged on the same plane, which extends along the length of the chip and extends outward from the projection point of the chip's center point on the plane. Each of the signal bonding wires is located outside its corresponding return bonding wire, so that the electromagnetic wave signal propagated by the signal bonding wire is absorbed by the return bonding wire in the direction extending along the plane from the signal bonding wire to the projection point of the chip's center point on the plane. The radius of curvature of the signal bonding wire is greater than that of the reflow bonding wire.

2. The chip interconnection structure according to claim 1, characterized in that: Both the first pad and the second pad pass through the plane, with the first pad being closer to the vertical centerline of the chip than the second pad.

3. The chip interconnection structure according to claim 1, characterized in that: The circuit board is provided with a signal transmission terminal and a ground terminal. The second end of the signal bonding wire is connected to the signal transmission terminal, and the return bonding wire is connected to the ground terminal.

4. The chip interconnection structure according to claim 3, characterized in that: The grounding terminal is located close to the chip, while the signal transmission terminal is located away from the chip.

5. The chip interconnection structure according to claim 4, characterized in that: The first pad, the second pad, the ground terminal, and the signal transmission terminal all penetrate the plane, and the distance between them and the projection point of the chip's center point on the plane gradually increases along the length of the chip.

6. The chip interconnection structure according to any one of claims 1 to 5, characterized in that: The highest point of the signal bonding wire relative to the circuit board is the first highest point, and the highest point of the return bonding wire relative to the circuit board is the second highest point. The distance between the first highest point and the circuit board is greater than the distance between the second highest point and the circuit board.

7. The chip interconnection structure according to claim 6, characterized in that: The signal bonding wire includes a first inclined segment, a first horizontal segment, and a second inclined segment connected in sequence. The reflux bond wire includes a third inclined segment, a second horizontal segment, and a fourth inclined segment connected in sequence; In the vertical direction, the first horizontal segment is located above the second horizontal segment.

8. A chip, wherein a circuit board is disposed beneath the chip, characterized in that, The chip and the circuit board are connected by the chip connection structure according to any one of claims 1 to 7.

9. The chip according to claim 8, characterized in that: At least one chip connection structure is provided on either side of the chip.

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