Heat dissipation module and electronic device

Abstract

The invention provides a heat dissipation module and an electronic device. The heat dissipation module comprises a first plane component; a partition wall coupled to the first planar assembly and defining a first path, one side of the first path being closed by the first planar assembly, the first path forming a closed loop; and a working fluid disposed in the first path. The heat dissipation module and the electronic device including the heat dissipation module according to an embodiment may be improved in heat dissipation efficiency.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0103088, filed on August 7, 2023, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a heat dissipation module and an electronic device including the heat dissipation module. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices and organic light emitting display devices has increased.

[0005] An electronic device including a display device may generate heat during its operation. The heat generated during the operation of the electronic device may reduce the performance of the electronic device and, in some cases, shorten the life of the electronic device. Therefore, a solution is needed that can effectively dissipate the heat generated from the electronic device. Summary of the invention

[0006] Various embodiments of the present disclosure are directed to a heat dissipation module with improved heat dissipation efficiency and an electronic device including the heat dissipation module.

[0007] An embodiment of the present disclosure may provide a heat dissipation module, comprising: a first planar component; a partition wall coupled to the first planar component and defining a first path, one side of the first path being closed by the first planar component, the first path forming a closed loop; and a working fluid disposed in the first path.

[0008] The heat dissipation module according to the embodiment may further include a second planar component, the second planar component coupled to the partition wall and defining a second path disposed between the partition wall and the second planar component, the partition wall being disposed between the first planar component and the second planar component. The second path may be in communication with the outside of the heat dissipation module.

[0009] The first planar component may include a first surface and the second planar component may include a second surface.

[0010] The partition wall may be arranged to be inclined relative to the first surface and the second surface. The first path may have a width of a third size arranged adjacent to the first surface, and a width of a fourth size smaller than the third size arranged adjacent to the second surface. The second path may have a width of a fifth size arranged adjacent to the first surface, and a width of a sixth size larger than the fifth size arranged adjacent to the second surface.

[0011] An inclination angle formed between the partition wall and the first surface in a region corresponding to the first path is an acute angle.

[0012] The partition wall may include at least two stepped portions. The first path may have a width of a seventh dimension disposed between the first surface and the second surface, and the seventh dimension may be smaller than the third dimension and larger than the fourth dimension. The second path may have a width of an eighth dimension disposed between the first surface and the second surface, and the eighth dimension may be larger than the fifth dimension and smaller than the sixth dimension.

[0013] The partition wall may include an opening in a region facing away from the first planar component, and the opening may be used to communicate with the outside of the heat dissipation module.

[0014] The first path may have a width of a first dimension, and the second path may have a width of a second dimension that is smaller than the first dimension.

[0015] The partition wall may include one or more stepped portions. The first path may have a width of a third dimension set adjacent to the first surface, and may have a width of a fourth dimension smaller than the third dimension set adjacent to the second surface. The second path may have a width of a fifth dimension set adjacent to the first surface, and may have a width of a sixth dimension smaller than the fifth dimension set adjacent to the second surface.

[0016] The working fluid may include liquid and air layers.

[0017] The volume of the liquid in the working fluid may be 20% or more and less than 100%.

[0018] The heat dissipation module may further include a second planar component coupled to the partition wall and defining a second path disposed between the partition wall and the second planar component. The second planar component may include a hole exposing at least a portion of the partition wall.

[0019] An embodiment of the present disclosure may include an electronic device, the electronic device including: a display panel provided with a plurality of pixels arranged to display an image in a front surface of the display panel; and a heat dissipation module disposed on a rear surface of the display panel. The heat dissipation module may include: a first planar component facing the rear surface of the display panel; a partition wall coupled to the first planar component and defining a first path and a second path, one side of the first path being closed by the first planar component, the second path being spaced apart from the first path and the second path being connected to the outside of the heat dissipation module, the first path forming a closed loop; and a working fluid disposed in the first path.

[0020] The electronic device may further include an adhesive component attached to the rear surface of the display panel and configured to attach the rear surface of the display panel to the first planar component of the heat dissipation module.

[0021] The first planar component may include a first surface connected to the partition wall, and a second planar component facing the first planar component may include a second surface connected to the partition wall.

[0022] The partition wall may be arranged to be inclined relative to the first surface and the second surface. The first path may have a width of a third size arranged adjacent to the first surface, and a width of a fourth size smaller than the third size arranged adjacent to the second surface. The second path may have a width of a fifth size arranged adjacent to the first surface, and a width of a sixth size larger than the fifth size arranged adjacent to the second surface.

[0023] The partition wall may include at least one stepped portion. The first path may have a width of a third size set adjacent to the first surface, and may have a width of a fourth size smaller than the third size set adjacent to the second surface. The second path may have a width of a fifth size set adjacent to the first surface, and may have a width of a sixth size smaller than the fifth size set adjacent to the second surface.

[0024] The partition wall may include an opening in a region facing away from the first planar component, and the opening connects the second path to the outside of the heat dissipation module (ie, the second path communicates with the outside of the heat dissipation module through the opening).

[0025] The first path may have a width of a first dimension, and the second path may have a width of a second dimension that is smaller than the first dimension.

[0026] The electronic device may further include a second planar component facing the first planar component, the partition wall being disposed between the first planar component and the second planar component. The second planar component may include a hole exposing at least a portion of the partition wall. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0028] Figure 2 yes Figure 1 An exploded perspective view of the display device shown in FIG.

[0029] Figure 3 is a system block diagram of a display module according to an embodiment of the present disclosure.

[0030] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0031] Figure 5 Yes Figure 4 A cross-sectional view of a display panel showing a pixel.

[0032] Figure 6 is a perspective view of a display module and a heat dissipation module according to an embodiment of the present disclosure.

[0033] Figure 7 is a perspective cross-sectional view of a heat dissipation module according to an embodiment of the present disclosure.

[0034] Figure 8 It is shown Figure 7 A cross-sectional view of a region X in an embodiment of a heat dissipation module.

[0035] Fig. 9 is a diagram for describing a heat dissipation module having a liquid injected therein.

[0036] Fig.10 is a rear perspective view of a heat dissipation module according to an embodiment of the present disclosure.

[0037] Fig.11 is a diagram for describing heat dissipation performance in a heat dissipation module according to an embodiment of the present disclosure.

[0038] Fig.12 It is shown Figure 7 A cross-sectional view of a region X in another embodiment of a heat dissipation module.

[0039] Fig.13 It is shown Figure 7 A cross-sectional view of a region X in another embodiment of a heat dissipation module.

[0040] Fig.14 It is shown Figure 7 A cross-sectional view of a region X in another embodiment of a heat dissipation module.

[0041] Fig.15 is a rear view of a heat dissipation module according to other embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the inventive concept. The present disclosure may be implemented in various forms and is not limited to the embodiments to be described herein below.

[0043] In the accompanying drawings, in order to explain the present disclosure more clearly, parts not related to the present disclosure will be omitted. Reference should be made to the accompanying drawings, in which similar reference numerals are used throughout the different drawings to represent similar components. Therefore, the aforementioned reference numerals may be used in other drawings.

[0044] For reference, for the purpose of explanation, the size of each component and the thickness of the lines showing the components are arbitrarily expressed, and the present disclosure is not limited to what is shown in the drawings. In the drawings, the thickness of the components may be exaggerated to clearly depict multiple layers and multiple regions.

[0045] In addition, the expression "same" may mean "substantially the same". In other words, the expression "same" may include a range that can be accepted by those skilled in the art. Other expressions may also be expressions from which "substantially" is omitted.

[0046] It will be understood that although the terms "first", "second", etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0047] The terms "under", "below", "above", and "on" etc. are used herein to explain the relationship between one or more components shown in the drawings. These terms may be relative terms describing the positions of components in the drawings, but the positions of components are not limited thereto.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the inventive concept belongs. In addition, unless explicitly defined in the description, terms as defined in general dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and terms are not ideally or excessively interpreted as having formal meanings.

[0049] It will also be understood that when the terms "includes," "comprising," "having," etc. are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components and / or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0050] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a perspective view of an electronic device 100 according to an embodiment of the present disclosure. Figure 2 yes Figure 1 An exploded perspective view of the electronic device 100 is shown in FIG. Figure 3 is a system block diagram of a display module DM according to an embodiment of the present disclosure.

[0052] The electronic device 100 according to an embodiment of the present disclosure may include a top cover TC, a display panel 210, a data driver 220, a scan driver 230, a heat dissipation module 240, a driving circuit substrate 250, a bottom cover BC, and the like.

[0053] The bottom cover BC, the driving circuit substrate 250 , the heat dissipation module 240 , the display panel 210 , and the top cover TC may overlap with each other in one direction (eg, the third direction DR3 ) and may be disposed in the electronic device 100 .

[0054] The display panel 210 , the data driver 220 , and the scan driver 230 may form a display module DM. In an embodiment, at least some components (eg, the timing controller 310 ) disposed on the driving circuit substrate 250 may form the display module DM.

[0055] The electronic device 100 may provide information about the image IM to a user of the electronic device 100 through the display area DA. As an example of the image IM, a butterfly is shown.

[0056] The top cover TC may be configured to protect the display panel 210. The top cover TC may include a cover opening OP-TC. The cover opening OP-TC may expose the front surface of the display panel 210, thereby allowing the display area DA to be exposed to the outside.

[0057] The heat dissipation module 240 may be configured to dissipate heat generated from the display module DM and the driving circuit substrate 250, etc., to the outside. For example, the heat dissipation module 240 may be configured to dissipate heat generated from the display panel 210, the data driver 220, the driving circuit substrate 250, etc., to the outside. Figure 6 Detailed description and drawings of the characteristics and configuration of the heat dissipation module 240 according to an embodiment of the present disclosure are given in more detail.

[0058] The driving circuit substrate 250 may include circuit components such as a timing controller 310. In an embodiment, the timing controller 310 may be formed in a single integrated circuit together with at least some components of the data driver 220. Hereinafter, an example is given in which the timing controller 310 and the data driver 220 are installed in the electronic device 100 as separate circuit components, but the embodiments of the present disclosure are not limited thereto. An additional power generation circuit (not shown) for generating various constant voltages supplied to the display module DM may be installed on the driving circuit substrate 250. The power generation circuit may be implemented, for example, using a power management integrated circuit (PMIC).

[0059] The bottom cover BC may be configured to cover the display panel 210, the heat dissipation module 240, the driving circuit substrate 250, etc. The bottom cover BC may protect the aforementioned components from external impact or contamination.

[0060] The display module DM according to an embodiment of the present disclosure may include a display panel 210 , a data driver 220 , a scan driver 230 , and the like.

[0061] A plurality of pixels PX are provided in the display panel 210. A plurality of data lines DL1, ..., and DLm (where m is an integer of 2 or more) electrically connected to the plurality of pixels PX, a plurality of scan lines SL1, SL2, ..., and SLn (where n is an integer of 2 or more), etc. may be provided in the display panel 210. One or more power supply voltage lines configured to apply a power supply voltage (e.g., a first power supply voltage ELVDD and a second power supply voltage ELVSS, etc.) to the plurality of pixels PX may be provided in the display panel 210.

[0062] The display panel 210 may include a display area DA in which a plurality of pixels PX are disposed and a non-display area positioned in a peripheral area of ​​the display area DA (eg, an edge area of ​​the display area DA).

[0063] Although the display panel 210 can be formed to be flat (e.g., uniformly flat), the embodiments of the present disclosure are not limited thereto. For example, the display panel 210 may include a curved surface portion (not shown) formed on each of its left and right ends. The curved surface portion may have a constant curvature or a variable curvature. In addition, the display panel 210 may be formed to be flexible so that the display panel 210 can be bent, curved, folded, or curled.

[0064] Each of the pixels PX may include two or more sub-pixels. For example, the sub-pixels may be arranged in a matrix structure, or may be arranged as Structure, etc. However, the embodiments of the present disclosure are not limited to the aforementioned structure.

[0065] A plurality of scan lines SL1 to SLn may be disposed in the display panel 210 and extend in a first direction DR1. The first direction DR1 may be, for example, a left-to-right direction of the display panel 210. However, embodiments of the present disclosure are not limited to the aforementioned structure.

[0066] A plurality of data lines DL1 to DLm may be disposed in the display panel 210 and extend in a second direction DR2. The second direction DR2 may be a direction different from the first direction DR1. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1. The second direction DR2 may be, for example, a direction from an upper side to a lower side of the display panel 210.

[0067] The scan driver 230 may be configured to output a scan signal having a high level voltage or a low level voltage to the plurality of scan lines SL1 to SLn in response to a scan driver control signal SCS received from the timing controller 310. For example, the scan driver control signal SCS may include a start signal indicating a frame start and a horizontal synchronization signal for outputting a scan signal at a correct timing for applying a data voltage, and the like.

[0068] The scan driver 230 may include a plurality of stage circuits STG configured to supply scan signals to the plurality of scan lines SL1 to SLn.

[0069] The scan driver 230 may be implemented as an integrated circuit (e.g., a gate driver integrated circuit (GDIC)) formed independently from the display panel 210. The scan driver 230 may be formed together with the display panel 210, and may be formed in at least some areas on the non-display area of ​​the display panel 210. In an embodiment, at least a portion of the scan driver 230 may be positioned to overlap the display area DA.

[0070] The data driver 220 may supply data voltages to the plurality of data lines DL1 to DLm. The data driver 220 may generate data voltages based on the image data DATA and the data driver control signal DCS received from the timing controller 310, and output the generated data voltages to the plurality of data lines DL1 to DLm at the correct timing. The data driver control signal DCS may include, for example, a source start pulse (SSP), a source shift clock (SSC), a source output enable signal (SOE), and the like.

[0071] The data driver 220 may include, for example, a source printed circuit board SPCB, a circuit film CF, and a data driver integrated circuit D-IC. The source printed circuit board SPCB may be configured to transmit various voltages to the data driver integrated circuit D-IC. The circuit film CF may be connected between the source printed circuit board SPCB and the display panel 210. The data driver integrated circuit D-IC may be disposed on the circuit film CF.

[0072] The timing controller 310 may be configured to control the data driver 220 and the scan driver 230. The timing controller 310 may receive control signals (e.g., synchronization signals and data enable signals, etc.) and clock signals, etc. from an external device (e.g., a host and a set-top box, etc.). The timing controller 310 may generate and output control signals DCS and SCS based on the received control signals and clock signals to control the data driver 220 and the scan driver 230, etc.

[0073] The timing controller 310 may be provided in the form of a logic circuit or a processor in the electronic device 100. The timing controller 310 may include one or more registers.

[0074] The display module DM according to the embodiment of the present disclosure can be used not only as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile personal computer (UMPC), but also as a display screen of various products such as a television, a notebook, a monitor, a billboard, and an Internet of Things (IoT) device. The display module DM according to the embodiment of the present disclosure can be used as a display screen of a virtual reality (VR) device and an augmented reality (AR) device, etc.

[0075] In the case where the display module DM is used as a display screen for VR devices, AR devices, etc., the electronic device 100 can be positioned very close to the user's eyes. In the case where the display module DM is used as a display screen for VR devices, AR devices, etc., the electronic device 100 can have a high pixel density. As a method of increasing the pixel density, the pixel PX can be formed on a silicon substrate. The technology of forming pixel circuits and related light-emitting elements (e.g., organic light-emitting diodes (OLEDs)) on a silicon substrate can be referred to as OLEDoS (OLED on silicon).

[0076] Figure 4 is an equivalent circuit diagram of a pixel PX according to an embodiment of the present disclosure.

[0077] The pixel PX according to an embodiment of the present disclosure may include a pixel circuit PXC and a light emitting element LE.

[0078] The pixel circuit PXC according to an embodiment of the present disclosure may include one or more transistors and one or more capacitors. Figure 4 , the pixel circuit PXC may include a first transistor DTR, a second transistor STR, and a storage capacitor Cstg. However, the pixel circuit PXC according to an embodiment of the present disclosure is not limited to the aforementioned structure, and the pixel circuit PXC may include three or more transistors, or may include two or more capacitors. Hereinafter, for the purpose of explanation, an example in which the pixel circuit PXC includes two transistors and one capacitor will be described.

[0079] The first transistor DTR may include a first electrode (e.g., a source electrode or a drain electrode), a second electrode (e.g., the remaining one of the source electrode and the drain electrode) and a gate electrode. The first electrode (e.g., the drain electrode) of the first transistor DTR may be connected (e.g., electrically connected) to the first power supply line PL1. The second electrode (e.g., the source electrode) of the first transistor DTR may be connected (e.g., electrically connected) to the second node N2. The gate electrode of the first transistor DTR may be connected (e.g., electrically connected) to the first node N1. Depending on the size of the voltage applied to the first node N1, the size of the current (e.g., the drive current) flowing through the first transistor DTR may be adjusted. The first power supply voltage ELVDD may be applied to the first power supply line PL1. The first power supply voltage ELVDD may be a high potential power supply voltage. The first transistor DTR may be referred to as a drive transistor.

[0080] The second transistor STR may be configured to switch the electrical connection between the data line DLi (wherein i is an integer between 1 and m) and the first node N1 in response to a scan signal SCAN[j] (wherein j is an integer between 1 and n). The scan signal SCAN[j] may be applied to the scan line SLj. The scan signal SCAN[j] may have an on level (e.g., a high level or a low level) or an off level (e.g., the other of the high level and the low level). If the second transistor STR is turned on, the data voltage Vdata or a voltage corresponding to the data voltage Vdata may be applied to the first node N1. The second transistor STR may be referred to as a scan transistor.

[0081] The storage capacitor Cstg may be configured to maintain a voltage difference between the first node N1 and the second node N2. The storage capacitor Cstg may include a first electrode connected (e.g., electrically connected) to the first node N1 and a second electrode connected (e.g., electrically connected) to the second node N2. The storage capacitor Cstg may be intentionally formed as a physical capacitor element rather than a parasitic capacitor.

[0082] The light emitting element LE may be connected between the second node N2 and the second power supply line PL2. The second power supply voltage ELVSS may be applied to the second power supply line PL2. The second power supply voltage ELVSS may be a low potential power supply voltage. The light emitting element LE may include a first electrode (e.g., an anode electrode) connected (e.g., electrically connected) to the second node N2 and a second electrode (e.g., a cathode electrode) connected (e.g., electrically connected) to the second power supply line PL2. The light emitting element LE may also include an emission layer disposed between the anode electrode and the cathode electrode, and is configured to emit light.

[0083] The emission layer may include a high molecular weight or low molecular weight organic light emitting material. The emission layer may include an inorganic light emitting material, or may include quantum dots. For example, the emission layer may include a high molecular weight or low molecular weight organic light emitting material for emitting light of a specific wavelength band (e.g., a blue wavelength band, a green wavelength band, or a red wavelength band). However, the embodiments of the present disclosure are not limited to the foregoing examples.

[0084] One or more transistors forming the pixel circuit PXC may include a P-type or N-type semiconductor layer. For example, at least one of the first transistor DTR and the second transistor STR may be implemented as a field effect transistor (FET) including a P-channel metal oxide semiconductor (PMOS). For example, at least one of the first transistor DTR and the second transistor STR may be implemented as a field effect transistor including an N-channel metal oxide semiconductor (NMOS).

[0085] Reference Figure 4, an example is given in which each of the first transistor DTR and the second transistor STR includes an N-channel metal oxide semiconductor. However, the embodiments of the present disclosure are not limited to the aforementioned structure. For example, at least one of the first transistor DTR and the second transistor STR can be implemented as a field effect transistor including a P-channel metal oxide semiconductor (NMOS).

[0086] The transistors forming the pixel circuit PXC may include amorphous silicon (a-Si) semiconductors, oxide semiconductors, low temperature polysilicon (LTPS) semiconductors, etc. For example, one of the two transistors forming the pixel circuit PXC may include a low temperature polysilicon semiconductor, and the other of the two transistors may include an oxide semiconductor.

[0087] Figure 5 Yes Figure 4 2 is a cross-sectional view of a display panel 210 showing a pixel PX.

[0088] The display panel 210 may include a base substrate BS, a buffer layer BFL, a semiconductor layer SML, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer ILD, a source electrode SE, a drain electrode DE, a passivation layer PAS, a pixel defining layer PDL, a light emitting element LE, an encapsulation layer SIL, and the like.

[0089] The buffer layer BFL may be disposed on one surface of the base substrate BS. The buffer layer BFL may be configured to prevent impurities from penetrating or diffusing from the base substrate BS during a manufacturing process. The buffer layer BFL may prevent impurities from diffusing into the semiconductor layer SML. Impurities may be introduced from the outside or may be generated by thermal decomposition of the base substrate BS. Impurities may include gas or sodium exhausted from the base substrate BS. The buffer layer BFL may block water penetrating from the outside.

[0090] The semiconductor layer SML may be disposed on the buffer layer BFL. The semiconductor layer SML may include a polycrystalline silicon semiconductor, an amorphous silicon semiconductor, an oxide semiconductor, etc. The semiconductor layer SML may include a channel region where electrons or holes can move, and a first ion doped region (e.g., a source region) and a second ion doped region (e.g., a drain region), and the channel region is between the first ion doped region and the second ion doped region.

[0091] The gate insulating layer GI may be disposed on the semiconductor layer SML. The gate insulating layer GI may cover the semiconductor layer SML. The gate insulating layer GI may include an organic layer and / or an inorganic layer. The gate insulating layer GI may include a plurality of inorganic thin films. The inorganic thin film may include a silicon nitride layer, a silicon oxide layer, and the like.

[0092] The gate electrode GE of the first transistor DTR may be disposed on the gate insulating layer GI.

[0093] The interlayer insulating layer ILD may be disposed on the gate electrode GE. The interlayer insulating layer ILD may include an organic layer and / or an inorganic layer. The interlayer insulating layer ILD may include a plurality of inorganic thin films. The inorganic thin films may include a silicon nitride layer, a silicon oxide layer, and the like.

[0094] The first electrode (e.g., drain electrode DE) and the second electrode (e.g., source electrode SE) of the first transistor DTR may be disposed on the interlayer insulating layer ILD. The first electrode (i.e., drain electrode DE) of the first transistor DTR may be connected (e.g., electrically connected) to the semiconductor layer SML of the first transistor DTR through the second contact hole CH2. The second electrode (i.e., source electrode SE) of the first transistor DTR may be connected (e.g., electrically connected) to the semiconductor layer SML of the first transistor DTR through the first contact hole CH1. The first contact hole CH1 may be formed by removing at least a portion of the gate insulating layer GI and at least a portion of the interlayer insulating layer ILD. The second contact hole CH2 may be formed by removing at least a portion of the gate insulating layer GI and at least a portion of the interlayer insulating layer ILD.

[0095] The passivation layer PAS may be disposed on the interlayer insulating layer ILD to cover the first electrode and the second electrode of the first transistor DTR. The passivation layer PAS may include an organic layer and / or an inorganic layer. For example, the passivation layer PAS may include an organic layer to planarize the area above the first electrode and the second electrode.

[0096] The pixel defining layer PDL is disposed on the passivation layer PAS. The pixel defining layer PDL may define an opening OP by removing at least a portion of the pixel defining layer. The light emitting element LE may be formed in an active area AA corresponding to the opening OP. The active area AA may correspond to an emission area where light is emitted from the light emitting element LE.

[0097] The light emitting element LE may be disposed on the passivation layer PAS. The light emitting element LE may be implemented, for example, using an organic light emitting diode (OLED) including an organic emission layer. In an embodiment, the light emitting element LE may be implemented using an inorganic light emitting element including an inorganic emission layer. Hereinafter, for the purpose of explanation, an example in which the light emitting element LE according to an embodiment of the present disclosure includes an organic light emitting diode will be described, but it should be noted that the embodiments of the present disclosure are not limited thereto.

[0098] The anode electrode AND may be disposed on the passivation layer PAS. The anode electrode AND may be connected (e.g., electrically connected) to the second electrode of the first transistor DTR through the third contact hole CH3. The third contact hole CH3 may be formed in the passivation layer PAS. The anode electrode AND may have conductivity. The anode electrode AND may be a pixel electrode or a positive electrode. The anode electrode AND may have light transmittance. In an embodiment where the anode electrode AND is a transparent electrode, the anode electrode AND may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In an embodiment where the anode electrode AND is a semi-transmissive and semi-reflective electrode or a reflective electrode, the anode electrode AND may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture of the foregoing metals. The anode electrode AND may have a single-layer or multilayer structure made of a transparent metal oxide or a metal. For example, the anode electrode AND may have a single-layer structure including ITO, Ag or a metal mixture (e.g., a mixture of Ag and Mg), a double-layer structure of ITO / Mg or ITO / MgF, or a triple-layer structure of ITO / Ag / ITO, but the embodiments of the present disclosure are not limited to the foregoing embodiments.

[0099] The emission layer EML may be disposed on the anode electrode AND. In an embodiment, a first functional layer (not shown) may be interposed between the anode electrode AND and the emission layer EML. In an embodiment, a second functional layer (not shown) may be interposed between the emission layer EML and the cathode electrode CTD.

[0100] The first functional layer may be positioned on the anode electrode AND and configured to inject and / or transport holes. The first functional layer may include at least one of a hole injection layer (not shown), a hole transport layer (not shown), and an electron blocking layer (not shown). The first functional layer may have, for example, a single layer formed of a single material, a single layer formed of a plurality of different materials, or a multilayer structure having a plurality of layers formed of a plurality of different materials.

[0101] The emission layer EML may have a single layer formed of a single material, a single layer formed of a plurality of different materials, or a multilayer structure having a plurality of layers formed of a plurality of different materials. The emission layer EML may be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Buget (LB), inkjet printing, laser printing, and laser induced thermal imaging (LITI). The emission layer EML is not limited to a specific material as long as it is a commonly used material. For example, the emission layer EML may be formed of a material that emits light in a red wavelength band, light in a green wavelength band, and / or light in a blue wavelength band, and may include a fluorescent or phosphorescent material. In addition, the emission layer EML may include a host and a dopant.

[0102] The second functional layer may be positioned below the cathode electrode CTD and is configured to inject and / or transport electrons. The second functional layer may include an electron transport layer (not shown) and an electron injection layer (not shown), but is not limited thereto. The second functional layer may have a structure including a continuously stacked electron transport layer and an electron injection layer. In addition, the second functional layer may have a single-layer structure containing a mixture of two or more materials, but the embodiments of the present disclosure are not limited thereto. The second functional layer may be formed using various methods such as vacuum deposition, spin coating, casting, LB, inkjet printing, laser printing, and laser induced thermal imaging (LITI) methods.

[0103] The cathode electrode CTD may be disposed on the emission layer EML, and may be made of a metal or alloy having a low work function, or a conductive compound, or a mixture of the foregoing materials. The cathode electrode CTD may be a common electrode or a negative electrode. The cathode electrode CTD may be a transmissive electrode, a semi-transmissive semi-reflective electrode, or a reflective electrode. In the case where the cathode electrode CTD is a transmissive electrode, the cathode electrode CTD may include Li, Ca, LiF, Al, Mg, Ag, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a multilayer structure material such as LiF / Ca, LiF / Al. The cathode electrode CTD may include an auxiliary electrode. The auxiliary electrode may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In the case where the cathode electrode CTD is a semi-transmissive and semi-reflective electrode or a reflective electrode, the cathode electrode CTD may include Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a multilayer structure material such as LiF / Ca, LiF / Al. Alternatively, the cathode electrode CTD may include a transparent metal oxide formed of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0104] In the case where the light emitting element LE is a top-emitting light emitting element, the anode electrode AND may be a reflective electrode, and the cathode electrode CTD may be a transmissive electrode or a semi-transmissive and semi-reflective electrode. In the case where the light emitting element LE is a bottom-emitting light emitting element, the anode electrode AND may be a transmissive electrode or a semi-transmissive and semi-reflective electrode, and the cathode electrode CTD may be a reflective electrode.

[0105] Figure 6 is a perspective view of a display module DM and a heat dissipation module 240 according to an embodiment of the present disclosure.

[0106] According to an embodiment of the present disclosure, the heat dissipation layer RHP may be disposed on the rear surface of the display panel 210. For example, the front surface of the display panel 210 may be a portion of the display panel 210 on which an image IM can be displayed (see FIG. Figure 1 ), and the rear surface of the display panel 210 may be a surface of the display panel 210 that is opposite to the front surface and does not display the image IM.

[0107] The heat dissipation layer RHP may be configured to dissipate heat generated from the display module DM (e.g., the display panel 210). The heat dissipation layer RHP may have a thermal emissivity (or thermal radiation coefficient) of a certain value or greater. For example, the thermal emissivity of the heat dissipation layer RHP may be 0.8 or higher. The heat dissipation layer RHP may be a coating formed by applying a heat dissipation coating. The heat dissipation layer RHP may include, for example, a ceramic composite material. In an embodiment of the present disclosure, the heat dissipation module 240 may also be disposed below the display module DM (e.g., the display panel 210) to enhance the heat dissipation of the display module DM. When the heat dissipation module 240 is disposed below the display module DM, the heat dissipation layer RHP disposed on the rear surface of the display panel 210 may be omitted.

[0108] The adhesive assembly TP may be disposed on the rear surface of the display panel 210. The adhesive assembly TP may attach the display module DM (eg, the display panel 210) to the heat dissipation module 240 (eg, the first plane assembly UL (refer to FIG. 2 )) (eg, by adhesive force). Figure 8 )). The adhesive component TP may have a certain thickness WW in the third direction DR3. The adhesive component TP may extend in the second direction DR2.

[0109] A plurality of adhesive assemblies TP may be disposed on the rear surface of the display panel 210. The adhesive assemblies TP may be disposed to be spaced apart from each other in the first direction DR1. For example, the adhesive assemblies TP may be disposed to be spaced apart from each other by a certain distance WD. Each of the adhesive assemblies TP may extend in the second direction DR2.

[0110] The adhesive component TP may include pores. The pores may be provided to absorb impact applied to the adhesive component TP. The adhesive component TP may be interposed between the display module DM (eg, the display panel 210) and the heat dissipation module 240 to absorb external impact. The adhesive component TP may be implemented, for example, using a foam tape.

[0111] Figure 7 is a perspective cross-sectional view of a heat dissipation module 240 according to an embodiment of the present disclosure.

[0112] Reference Figure 7The heat dissipation module 240 according to an embodiment of the present disclosure may include a first surface SF1 (or a first wall SF1 ) and a second surface SF2 (or a second wall SF2 ) and a partition wall PW disposed between the first surface SF1 and the second surface SF2 .

[0113] The first surface SF1 may refer to a surface facing the display module DM (refer to Figure 6 ) surface. The first surface SF1 may be attached to the adhesive component TP (refer to Figure 6 ) surface.

[0114] The second surface SF2 may refer to a surface disposed away from the display module DM and opposite to the first surface SF1 .

[0115] The partition wall PW may include corrugations. The corrugations may form a first path PT1 and a second path PT2 isolated from each other. The first path PT1 may be formed between the partition wall PW and the first surface SF1.

[0116] The second path PT2 may be formed between the partition wall PW and the second surface SF2 .

[0117] The first path PT1 may be an area formed to receive a fluid (e.g., liquid) for heat dissipation. The first path PT1 may include one or more closed loops. The fluid may include an air layer (e.g., bubbles). Due to the heat applied to at least a portion of the first path PT1, the volume of the air layer in the corresponding area may expand. Due to the heat radiated from the remaining portion of the first path PT1, the volume of the air layer in the corresponding area may shrink. Due to expansion and contraction, the fluid may vibrate. Heat is transferred through the fluid, so that heat can be dissipated in the heat dissipation module 240. The first path PT1 may be surrounded by a partition wall PW and a first surface SF1.

[0118] The second path PT2 may be an area exposed to the outside. The second path PT2 may be an area through which external air flows into the heat dissipation module 240 or through which internal air is discharged from the heat dissipation module 240. For example, the second path PT2 may be connected to the outside of the heat dissipation module 240 (i.e., communicated with the outside of the heat dissipation module 240) in the first direction DR1 and / or the second direction DR2. In an embodiment, the second path PT2 may be connected to the outside of the heat dissipation module 240 in the third direction DR3. The second path PT2 may be surrounded by a partition wall PW. In an embodiment, the second path PT2 may also be surrounded by a second surface SF2.

[0119] In an embodiment, the first surface SF1 and the partition wall PW may be formed integrally with each other. For example, the first surface SF1 and the partition wall PW may be formed integrally with each other so that the first surface SF1 and the partition wall PW are continuously formed using a three-dimensional (3D) printing method. However, in an embodiment of the present disclosure, the method of integrally forming the first surface SF1 and the partition wall PW is not limited to the 3D printing method, and the foregoing examples are merely illustrative.

[0120] In an embodiment, the first surface SF1 and the partition wall PW may be formed as separate components. For example, the partition wall PW may be attached (or coupled) to the first surface SF1 having a planar shape, thereby forming the heat dissipation module 240. In an embodiment, the second surface SF2 may be formed together with the first surface SF1 and the partition wall PW by the aforementioned 3D printing method. In an embodiment, the second surface SF2 may be prepared separately and attached (or coupled) to the partition wall PW, thereby forming the heat dissipation module 240.

[0121] Hereinafter, for the purpose of explanation, an example in which the heat dissipation module 240 according to an embodiment of the present disclosure includes the second surface SF2 will be described, but it should be noted that the embodiments of the present disclosure are not limited thereto. Hereinafter, for the purpose of explanation, an example in which the heat dissipation module 240 according to an embodiment of the present disclosure has a structure in which the first surface SF1, the partition wall PW, and the second surface SF2 are formed separately from each other will be described, but it should be noted that the embodiments of the present disclosure are not limited thereto.

[0122] Figure 8 It is shown Figure 7 2 is a cross-sectional view of a region X in an embodiment of a heat dissipation module 240 . Fig. 9 is a diagram for describing the heat dissipation module 240 having the liquid FL injected therein.

[0123] Reference Figure 8 and Fig. 9 The heat dissipation module 240 according to an embodiment of the present disclosure may include a first planar component (or plate) UL (eg, a first plate-shaped member), a partition wall PW, and a second planar component (or plate) LL (eg, a second plate-shaped member).

[0124] The first planar component UL may include a first surface SF1 as an outer surface of the heat dissipation module 240. The first planar component UL may be connected (e.g., attached or coupled) to the partition wall PW on an inner surface of the first planar component UL facing away from the first surface SF1. In an embodiment, the first planar component UL may include a high heat transfer material, such as a metal. In another embodiment, the first planar component UL may include a polymer having a thermal conductivity lower than that of a metal (e.g., copper (Cu), gold (Au), etc.). For example, since substantial heat dissipation in the heat dissipation module 240 is performed by filling a liquid FL between the partition wall PW and the first planar component UL, the material used for the first planar component UL may be selected from a material having a relatively lower thermal conductivity than a metal (e.g., a polymer).

[0125] The second planar component LL may include a second surface SF2 as an outer surface of the heat dissipation module 240 opposite to the first surface SF1. The second planar component LL may be connected (e.g., attached or coupled) to the partition wall PW on the inner surface of the second planar component LL facing away from the second surface SF2. In an embodiment, the second planar component LL may include a high heat transfer material, such as a metal. In another embodiment, the second planar component LL may include a polymer having a thermal conductivity lower than that of a metal (e.g., copper (Cu), gold (Au), etc.). For example, since substantial heat dissipation in the heat dissipation module 240 is performed by filling the liquid FL between the partition walls PW, the material used for the second planar component LL may be selected from a material having a relatively lower thermal conductivity than a metal (e.g., a polymer).

[0126] The first plane component UL can enhance the rigidity of the heat dissipation module 240. The second plane component LL can also enhance the rigidity of the heat dissipation module 240. The first plane component UL and the second plane component LL can also be used as a chassis to prevent the display panel 210 (refer to Figure 2 ) etc. due to being applied to the electronic device 100 (refer to Figure 1 The first planar component UL and the second planar component LL may include, for example, a material having a relatively low thermal conductivity and being able to provide a relatively high rigidity.

[0127] The partition wall PW may form a first path PT1 and a second path PT2. Each of the first path PT1 and the second path PT2 may have a certain width. For example, each channel in the first path PT1 may have a uniform width of a first dimension D1. For example, each of the second paths PT2 may have a uniform width of a second dimension D2.

[0128] The first dimension D1 is a dimension sufficient to allow the liquid FL filled in the first path PT1 to move by capillary phenomenon to transfer heat and is not limited in size. The first dimension D1 may be determined and designed to vary according to the type of the liquid FL contained in the first path PT1.

[0129] The liquid FL may be, for example, water, freon, methanol, or ethanol, but the embodiments of the present disclosure are not limited thereto. The liquid FL and the air layer (eg, air bubbles) VP (refer to Fig.11 ) can be referred to as the working fluid WZ (refer to Fig.11 ).

[0130] In an embodiment, the first dimension D1 may be greater than the second dimension D2. For example, the increase in the surface area of ​​the portion of the first planar component UL in contact with the liquid FL may enhance the heat dissipation effect of the heat dissipation module 240. However, the embodiments of the present disclosure are not limited to the foregoing examples. The first dimension D1 may be the same (or substantially the same) as the second dimension D2. In an embodiment, the first dimension D1 may be smaller than the second dimension D2.

[0131] Fig.10 is a rear perspective view of the heat dissipation module 240 according to an embodiment of the present disclosure. Fig.11 is used to describe the heat dissipation module 240 (refer to Fig.10 ) is a diagram of the heat dissipation performance.

[0132] Reference Fig.10 , showing Figure 7 2 is a rear view of the heat dissipation module 240, and the representation of the second surface SF2 is omitted to effectively illustrate the arrangement of the partition wall PW in the heat dissipation module 240.

[0133] The partition wall PW can form a closed loop. Fig. 9 ) may be contained in a closed loop. In an embodiment, the partition wall PW may further include an opening (not shown) to allow the liquid FL to be injected into the space formed by the closed loop in the partition wall PW. In an embodiment, during the process of manufacturing the partition wall PW (or the heat dissipation module 240), the liquid FL may be injected into the space formed by the closed loop in the partition wall PW. After the liquid FL is injected, the opening allowing the liquid FL to be injected into the space formed by the closed loop in the partition wall PW may be sealed. In this case, the partition wall PW may have no opening.

[0134] Reference Fig.10 , shows an embodiment in which the heat dissipation module 240 includes only one closed loop defined by the partition wall PW. However, the embodiments of the present disclosure are not limited to the aforementioned structure. For example, the heat dissipation module 240 may include two or more closed loops.

[0135] Two or more closed loops may be placed on a plane defined by the first direction DR1 and the second direction DR2. For example, two or more closed loops may be arranged parallel to each other in the first direction DR1 or the second direction DR2, and the embodiments of the present disclosure are not limited thereto.

[0136] Reference Fig.10 and Fig.11 , the high temperature zone HZ and the low temperature zone LZ may be defined in the heat dissipation module 240. Also refer to Figure 2 In response to the ambient temperature of the heat dissipation module 240, a high temperature zone HZ (or high temperature area HZ) and a low temperature zone LZ (or low temperature area LZ) may be defined in the electronic device 100. The high temperature zone HZ and the low temperature zone LZ in the heat dissipation module 240 may be adaptable and may not be predefined areas. The high temperature zone HZ may be an area positioned to overlap with the data driver 220 (e.g., the data driver integrated circuit D-IC). For example, the high temperature zone HZ may be an area corresponding to the area where the image IM is displayed with high brightness (refer to Figure 1 ) overlaps with the display panel 210. The low temperature zone LZ may be, for example, a region away from the data driver 220 (eg, referring to Figure 2 , a region at one end of the display panel 210 opposite to the second direction DR2). However, it should be noted that the high temperature region HZ and the low temperature region LZ are relatively defined, and the embodiments of the present disclosure are not limited to the aforementioned examples.

[0137] Reference Fig.11 , the working fluid WZ may include a liquid FL and an air layer VP. The air layer VP (e.g., steam) may increase in volume in the high temperature region HZ and decrease in volume in the low temperature region LZ. If the volume of the air layer VP increases in the high temperature region HZ, the air layer VP may transfer the liquid FL. The liquid FL transferred from the high temperature region HZ by the air layer VP may move to the low temperature region LZ. In the low temperature region LZ, the liquid FL releases heat. Therefore, the heat dissipation module 240 (refer to Fig.10 ) can perform heat dissipation function.

[0138] According to the design of those skilled in the art, the volume of the air layer VP in the working fluid WZ (or the volume of the liquid FL) can be designed to be unrestricted within the range that allows the liquid FL to move by capillary action. For example, the volume of the liquid FL in the working fluid WZ can be approximately 20% or more and less than 100%. For example, the volume of the liquid FL in the working fluid WZ can be approximately 50%.

[0139] Fig.12 It is shown Figure 7FIG. 2 is a cross-sectional view of a region X in another embodiment of a heat dissipation module 240 .

[0140] Reference Fig.12 In the heat dissipation module 240 according to the embodiment of the present disclosure, the second plane component LL (refer to Fig. 9 ). Therefore, the second path PT2 (or the partition wall PW) may include an opening OPN, and may be connected to the outside of the heat dissipation module 240 in the opening OPN. The external air of the heat dissipation module 240 may easily flow through the second path PT2 through the opening OPN. Therefore, the heat exchange between the liquid FL in the first path PT1 and the external air in the second path PT2 may be more easily performed. Therefore, the heat dissipation effect of the heat dissipation module 240 may be enhanced.

[0141] Fig.13 It is shown Figure 7 FIG. 2 is a cross-sectional view of a region X in another embodiment of a heat dissipation module 240 .

[0142] Reference Fig.13 , a certain inclination angle θ may be formed between the partition wall PW and the first surface SF1. For example, the first path PT1 may have a width of a third dimension D3 on a side of the first path PT1 adjacent to the first surface SF1, and may have a width of a fourth dimension D4 different from the third dimension D3 on a side of the first path PT1 adjacent to the second surface SF2. For example, the second path PT2 may have a width of a fifth dimension D5 on a side of the second path PT2 adjacent to the first surface SF1, and may have a width of a sixth dimension D6 different from the fifth dimension D5 on a side of the second path PT2 adjacent to the second surface SF2.

[0143] In an embodiment, a certain inclination angle θ may be an acute angle less than a right angle (90°). For example, in the region corresponding to the first path PT1, the inclination angle θ between the partition wall PW and the first surface SF1 may be an acute angle. In the aforementioned embodiment, the third dimension D3 may be greater than the fourth dimension D4. The fifth dimension D5 may be less than the sixth dimension D6. In the aforementioned embodiment, the liquid FL may have a relatively large contact area with the region where heat is introduced into the first planar component UL. In addition, due to the diagonal arrangement of the partition wall PW, the surface area of ​​the liquid FL in contact with the second path PT2 may be relatively increased. Therefore, the heat dissipation effect of the heat dissipation module 240 according to an embodiment of the present disclosure may be enhanced.

[0144] Fig.14 It is shown Figure 7 FIG. 2 is a cross-sectional view of a region X in another embodiment of a heat dissipation module 240 .

[0145] Reference Fig.14, shows an embodiment in which the partition wall PW includes one or more step portions. For example, the first path PT1 may have a width of a third dimension D3 on a side of the first path PT1 adjacent to the first surface SF1, and may have a width of a fourth dimension D4 different from the third dimension D3 on a side of the first path PT1 adjacent to the second surface SF2. For example, the second path PT2 may have a width of a fifth dimension D5 on a side of the second path PT2 adjacent to the first surface SF1, and may have a width of a sixth dimension D6 different from the fifth dimension D5 on a side of the second path PT2 adjacent to the second surface SF2.

[0146] The angle between the partition wall PW and the first surface SF1 may be a right angle, but the embodiments of the present disclosure are not limited thereto. The angle between the partition wall PW and the second surface SF2 may be a right angle, but the embodiments of the present disclosure are not limited thereto.

[0147] In the embodiment where the partition wall PW includes one stepped portion, the first path PT1 may have a width of a third dimension D3 and a fourth dimension D4. In the aforementioned embodiment, the second path PT2 may have a width of a fifth dimension D5 and a sixth dimension D6.

[0148] In an embodiment where the partition wall PW includes two or more step portions, the first path PT1 may have a width of a third dimension D3, a fourth dimension D4, and a seventh dimension D7. The seventh dimension D7 may be smaller than the third dimension D3 and larger than the fourth dimension D4. In the aforementioned embodiment, the second path PT2 may have a width of a fifth dimension D5, a sixth dimension D6, and an eighth dimension D8. The eighth dimension D8 may be larger than the fifth dimension D5 and smaller than the sixth dimension D6.

[0149] In the embodiment where the partition wall PW includes two or more step portions, the surface area of ​​the liquid FL flowing through the first path PT1 in contact with the second path PT2 through the partition wall PW can be increased. Therefore, the heat dissipation effect can be enhanced.

[0150] Fig.15 is a rear view of a heat dissipation module 240 according to other embodiments of the present disclosure.

[0151] Reference Fig.15 In the heat dissipation module 240 according to an embodiment of the present disclosure, a hole HOLE may be formed in the second plane component LL. The hole HOLE may expose at least a portion of the partition wall PW to the outside of the heat dissipation module 240. The hole HOLE may expose at least a portion of the partition wall PW in an area corresponding to an area in which heat dissipation in the display module DM is higher than other areas.

[0152] In an embodiment, the second planar component LL may include a plurality of holes HOLE. The holes HOLE may be positioned adjacent to each other in the first direction DR1, or may be positioned adjacent to each other in the second direction DR2. However, the embodiments of the present disclosure are not limited to the aforementioned examples.

[0153] Due to the holes HOLE, a surface area of ​​the partition wall PW in contact with the external air of the heat dissipation module 240 may be increased, thereby being able to enhance the heat dissipation effect.

[0154] The heat dissipation module and the electronic device including the same according to the embodiments of the present disclosure may be improved in heat dissipation efficiency.

[0155] Although the preferred embodiments of the present disclosure have been disclosed for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present disclosure as disclosed in the appended claims. Therefore, the limits and scope of the present disclosure should be determined by the technical spirit of the appended claims.

Claims

1. A heat dissipation module, wherein: The heat dissipation module comprises: a first planar component; a partition wall coupled to the first planar component and defining a first path, one side of the first path being closed by the first planar component, the first path forming a closed loop; and A working fluid is arranged in the first path.

2. The heat dissipation module according to claim 1, wherein: The heat dissipation module further includes a second planar component coupled to the partition wall and defining a second path disposed between the partition wall and the second planar component, wherein the partition wall is disposed between the first planar component and the second planar component. Wherein, the second path is communicated with the outside of the heat dissipation module.

3. The heat dissipation module according to claim 2, wherein: The first planar component includes a first surface and the second planar component includes a second surface.

4. The heat dissipation module according to claim 2, in, The partition wall is arranged to be inclined relative to the first surface and the second surface, wherein the first path has a width of a third dimension set adjacent to the first surface, and has a width of a fourth dimension smaller than the third dimension and set adjacent to the second surface, and The second path has a width of a fifth dimension disposed adjacent to the first surface, and has a width of a sixth dimension that is greater than the fifth dimension and disposed adjacent to the second surface.

5. The heat dissipation module according to claim 4, wherein: an inclination angle formed between the partition wall and the first surface in a region corresponding to the first path is an acute angle, Wherein, the partition wall comprises at least two step portions, wherein the first path has a width of a seventh dimension disposed between the first surface and the second surface, and the seventh dimension is smaller than the third dimension and larger than the fourth dimension, and The second path has a width of an eighth dimension disposed between the first surface and the second surface, and the eighth dimension is greater than the fifth dimension and less than the sixth dimension.

6. The heat dissipation module according to claim 1, wherein: The partition wall includes an opening in a region facing away from the first planar component, and the opening is used to communicate with the outside of the heat dissipation module.

7. The heat dissipation module according to claim 2, wherein: The first path has a width of a first dimension, and the second path has a width of a second dimension that is smaller than the first dimension.

8. The heat dissipation module according to claim 2, wherein: The first planar component includes a first surface, and the second planar component includes a second surface, wherein the partition wall comprises one or more step portions, wherein the first path has a width of a third dimension set adjacent to the first surface, and has a width of a fourth dimension smaller than the third dimension and set adjacent to the second surface, and The second path has a width of a fifth dimension disposed adjacent to the first surface, and has a width of a sixth dimension smaller than the fifth dimension disposed adjacent to the second surface.

9. The heat dissipation module according to claim 1, wherein: The working fluid includes liquid and air layers.

10. The heat dissipation module according to claim 9, wherein: The volume of the liquid in the working fluid is 20% or more and less than 100%.

11. The heat dissipation module according to claim 1, wherein: The heat dissipation module further includes a second planar component coupled to the partition wall and defining a second path disposed between the partition wall and the second planar component. Wherein, the second planar component includes a hole exposing at least a portion of the partition wall.

12. An electronic device, wherein: The electronic device comprises: A display panel including a plurality of pixels arranged to display an image in a front surface of the display panel; and A heat dissipation module is arranged on the rear surface of the display panel. Wherein, the heat dissipation module comprises: A first planar component facing the rear surface of the display panel; a partition wall coupled to the first planar component and defining a first path and a second path, wherein one side of the first path is closed by the first planar component, the second path is spaced apart from the first path and communicates with the outside of the heat dissipation module, and the first path forms a closed loop; and A working fluid is arranged in the first path.

13. The electronic device according to claim 12, wherein: The electronic device also includes an adhesive component attached to the rear surface of the display panel and configured to attach the rear surface of the display panel to the first planar component of the heat dissipation module.

14. The electronic device according to claim 12, wherein: The first planar component includes a first surface connected to the partition wall, and a second planar component facing the first planar component includes a second surface connected to the partition wall.

15. The electronic device according to claim 12, wherein: The electronic device further includes a second planar component facing the first planar component, and the partition wall is disposed between the first planar component and the second planar component. Wherein, the second planar component includes a hole exposing at least a portion of the partition wall.

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