Memory and manufacturing method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a memory and a manufacturing method thereof, the memory comprises a substrate and at least one memory layer, the memory layer is formed on the substrate, the memory layer comprises a memory unit, and the memory unit comprises a read transistor, comprising a first grid electrode, a first semiconductor layer at least horizontally surrounding the peripheral side of the first grid electrode and a first grid insulating layer formed between the first grid electrode and the first semiconductor layer, the first grid electrode comprises a grid bottom wall and a grid side wall, the grid side wall horizontally surrounds the grid bottom wall and extends in the direction away from the substrate, and a grid groove is defined by the grid side wall and the grid bottom wall; the writing transistor comprises a second grid electrode, a second semiconductor layer at least horizontally surrounding the peripheral side of the second grid electrode and a second grid insulating layer formed between the second grid electrode and the second semiconductor layer, and part of the second semiconductor layer is embedded in the grid electrode groove and is in contact with at least part of the grid electrode groove. The memory of the scheme can reduce the technical difficulty of the process while improving the storage density.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and particularly relates to a memory and a method for manufacturing the same. Background Art

[0002] With the miniaturization of technology nodes, the storage cells of DRAM (Dynamic Random Access Memory) have gradually changed from a 1T1C structure (a combination of 1 transistor and 1 capacitor) to a planar 2T0C structure (i.e., a structure with 2 horizontally arranged transistors and no capacitor). However, this design still results in a relatively low storage density of DRAM and a more complicated manufacturing process. Summary of the invention

[0003] The present disclosure provides a memory and a method for manufacturing the same, which can improve storage density while reducing process technology difficulty.

[0004] A first aspect of the present disclosure provides a memory, which may include a substrate and at least one storage layer, wherein the storage layer is formed on the substrate and includes a storage unit, wherein the storage unit includes:

[0005] A read transistor, comprising a first gate, a first semiconductor layer at least horizontally surrounding an outer peripheral side of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer, wherein the first gate comprises a gate bottom wall and a gate side wall, wherein the gate side wall horizontally surrounds the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall form a gate groove;

[0006] A write transistor includes a second gate, a second semiconductor layer at least horizontally surrounding the outer peripheral side of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, wherein a portion of the second semiconductor layer is embedded in the gate groove and contacts with at least a portion of the gate groove.

[0007] A second aspect of the present disclosure provides a method for manufacturing a memory, the method comprising:

[0008] providing a substrate;

[0009] At least one storage layer is formed on the substrate, wherein the step of forming the storage layer comprises:

[0010] A read transistor is formed on the substrate, the read transistor comprising a first gate, a first semiconductor layer at least horizontally surrounding an outer peripheral side of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer, the first gate comprising a gate bottom wall and a gate side wall, the gate side wall is horizontally arranged around the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall form a gate groove;

[0011] A write transistor is formed at the gate groove to form a storage unit, the write transistor including a second gate, a second semiconductor layer at least horizontally surrounding the outer peripheral side of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, a portion of the second semiconductor layer is embedded in the gate groove and contacts with at least a portion of the gate groove.

[0012] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0013] In the present disclosure, by vertically nesting part of the CAA type write transistor in the memory cell inside the CAA type read transistor, compared to the planar 2T0C type memory cell, while ensuring the storage density of the memory cell, not only the horizontal area occupied by the memory cell can be reduced, but also the vertical height of the memory cell can be reduced. In other words, the entire volume of the memory cell can be reduced, that is: the space occupied by the memory cell is reduced, so that more memory cells can be arranged in a memory of a certain volume, thereby improving the storage density of the memory.

[0014] In addition, the present invention enables the semiconductor layer of the write transistor to be located at the gate groove of the gate in the read transistor, so that it can directly contact the gate of the read transistor, thereby realizing the connection between the write transistor and the read transistor. Compared with the planar 2T0C storage unit, there is no need to design an additional connection pattern to connect the write transistor and the read transistor together, thereby reducing the requirements for the photolithography process in the manufacturing process, thereby improving the product yield and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0016] Figures 1 to 6 The schematic diagrams of the structures of memories in different embodiments of the present disclosure are shown respectively.

[0017] Figures 7 to 24The schematic diagrams respectively show the structures of the manufacturing method of the memory disclosed in the present invention after executing different steps. DETAILED DESCRIPTION

[0018] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0019] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0020] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0021] An embodiment of the present disclosure provides a memory, which may include a substrate and at least one storage layer.

[0022] The memory according to the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0023] refer to Figure 1 As shown, the substrate 1 may be a stacked structure, for example: the substrate 1 may include a semiconductor substrate layer 10 and an insulating substrate layer 11 formed on the semiconductor substrate layer 10, the semiconductor substrate layer 10 may include semiconductor materials such as single crystal silicon, but not limited to this, and may also include semiconductor materials such as germanium (Ge), the insulating substrate layer 11 may include insulating materials such as silicon dioxide, but not limited to this, and the insulating substrate layer 11 may also be made of other materials with insulating properties, depending on the actual situation.

[0024] It should be understood that the substrate 1 of this embodiment is not limited to Figure 1 The stacked structure shown may also be a single-layer structure. For example, the substrate 1 may be a single-layer structure made of a semiconductor material, or a single-layer structure made of an insulating material, etc., depending on the specific circumstances.

[0025] refer to Figure 1 As shown, the storage layer 2 may be formed on the substrate 1. For example, when the substrate 1 is a stacked structure including a semiconductor substrate layer 10 and an insulating substrate layer 11, the storage layer 2 may be formed on the top surface of the insulating substrate layer 11 away from the semiconductor substrate layer 10.

[0026] Continue to refer Figure 1 As shown, the storage layer 2 may include a storage unit. The storage unit may include two transistors, for example: a read transistor 201 and a write transistor 202, both of which may be a CAA (Channel-All-Around, vertical annular channel structure) type, specifically, the read transistor 201 may include a first gate 2011, a first semiconductor layer 2012 at least horizontally surrounding the outer peripheral side of the first gate 2011, and a first gate insulating layer 2013 formed between the first gate 2011 and the first semiconductor layer 2012, and the write transistor 202 may include a second gate 2021, a second semiconductor layer 2022 at least horizontally surrounding the outer peripheral side of the second gate 2021, and a second gate insulating layer 2023 formed between the second gate 2021 and the second semiconductor layer 2022.

[0027] For example, the materials of the first semiconductor layer 2012 and the second semiconductor layer 2022 can be the same, for example, the first semiconductor layer 2012 and the second semiconductor layer 2022 can both be made of IGZO (indium gallium zinc oxide). By using IGZO to make the semiconductor layer, there is no need to dope the first semiconductor layer 2012 and the second semiconductor layer 2022 to form source and drain regions, and the leakage current is small, thereby increasing the storage time and improving the storage performance; but not limited to this, the first semiconductor layer 2012 and the second semiconductor layer 2022 can also be made of other semiconductor materials such as IAZO (indium aluminum zinc oxide), as long as the storage time and storage performance of the transistor can be guaranteed; in addition, the materials of the first semiconductor layer 2012 and the second semiconductor layer 2022 can also be different, depending on the specific circumstances.

[0028] For example, the materials of the first gate 2011 and the second gate 2021 can be the same, for example, the first gate 2011 and the second gate 2021 can both be made of conductive materials such as metal tungsten, but are not limited to this, and other materials with good conductive properties can also be used, depending on specific needs; in addition, the materials of the first gate 2011 and the second gate 2021 can also be different, depending on the specific situation.

[0029] For example, the materials of the first gate insulating layer 2013 and the second gate insulating layer 2023 can be the same, for example, the first gate insulating layer 2013 and the second gate insulating layer 2023 can both be made of insulating materials such as silicon dioxide, but are not limited to this, and can also be made of other insulating materials. In addition, the materials of the first gate insulating layer 2013 and the second gate insulating layer 2023 can also be different, depending on the specific circumstances.

[0030] In this embodiment, the first gate 2011 of the read transistor 201 may be designed in a groove shape. Specifically, in the read transistor 201: the first gate 2011 may include a gate side wall 2011a and a gate bottom wall 2011b, the gate side wall 2011a is horizontally arranged around the gate bottom wall 2011b and extends in a direction away from the substrate 1, and the gate side wall 2011a and the gate bottom wall 2011b form a gate groove; and a portion of the write transistor 202 may be vertically nested in the read transistor 201, specifically, a portion of the second semiconductor layer 2022 in the write transistor 202 is embedded in the gate groove of the first gate 2011 and contacts at least a portion of the gate groove in the first gate 2011, that is, it may contact at least one of the gate side wall 2011a and the gate bottom wall 2011b.

[0031] In the present disclosure, by vertically nesting part of the CAA type write transistor 202 in the storage cell inside the CAA type read transistor 201, compared to the planar 2T0C type storage cell, while ensuring the storage density of the storage cell, not only the horizontal area occupied by the storage cell can be reduced, but also the vertical height of the storage cell can be reduced, that is: the entire volume of the storage cell can be reduced, thereby reducing the space occupied by the storage cell, so that more storage cells can be arranged in a memory of a certain volume to improve the storage density of the memory.

[0032] In addition, the present disclosure enables the semiconductor layer of the write transistor 202 to be located at the gate groove of the gate in the read transistor 201, so that it can directly contact the gate of the read transistor 201, thereby realizing the connection between the write transistor 202 and the read transistor 201. Compared with the planar 2T0C storage unit, there is no need to design an additional connection pattern to connect the write transistor 202 and the read transistor 201 together, thereby reducing the requirements for the photolithography process in the manufacturing process, thereby improving product yield and reducing production costs.

[0033] It should be understood that the position where the gate groove in the first gate 2011 contacts the second semiconductor layer 2022 can be understood as a storage node of the storage unit, for example: Figure 1 The position where the middle gate bottom wall 2011 b contacts the second semiconductor layer 2022 can be understood as a storage node.

[0034] In some embodiments, reference Figure 1As shown, in the write transistor 202: the second semiconductor layer 2022, the second gate 2021 and the second gate insulating layer 2023 may have an embedded portion and an extended portion, and the embedded portion may be a portion of the second semiconductor layer 2022, the second gate 2021 and the second gate insulating layer 2023 embedded in the gate groove. It should be understood that the embedded portion of the second semiconductor layer 2022 is in contact with at least a portion of the gate groove to achieve a connection between the write transistor 202 and the read transistor 201, and the extended portion may be a portion of the second semiconductor layer 2022, the second gate 2021 and the second gate insulating layer 2023 located on the side of the embedded portion away from the substrate 1, and this extended portion protrudes relative to the read transistor 201 in a direction away from the substrate 1.

[0035] In this embodiment, by embedding the bottoms of the second semiconductor layer 2022, the second gate 2021 and the second gate insulating layer 2023 in the write transistor 202 into the gate groove of the first gate 2011, the vertical height of the storage unit can be further reduced while ensuring the storage density.

[0036] For example, refer to Figure 1 As shown, the embedded portion of the second semiconductor layer 2022 may include a second semiconductor side wall 2022a and a second semiconductor bottom wall 2022b. The second semiconductor side wall 2022a is horizontally arranged around the second semiconductor bottom wall 2022b and extends in a direction away from the substrate 1. The second semiconductor side wall 2022a and the second semiconductor bottom wall 2022b form a second semiconductor groove. The embedded portion of the second gate 2021 and the embedded portion of the second gate insulation layer 2023 are located in the second semiconductor groove.

[0037] refer to Figure 1 As shown, the bottom surface of the second semiconductor bottom wall 2022b and the bottom surface of the second semiconductor side wall 2022a are both in contact with the gate bottom wall 2011b. This design can ensure the contact area between the second semiconductor layer 2022 and the first gate 2011, and the process difficulty is also relatively low during manufacturing.

[0038] In some embodiments, reference Figure 1As shown, the storage unit may also include an insulating dielectric sidewall 203a, which is embedded in the gate groove and horizontally surrounds the outer peripheral side of the embedded portion in the second semiconductor layer 2022, wherein the outer peripheral surface of the embedded portion in the second semiconductor layer 2022 is insulated from the gate sidewall 2011a by the insulating dielectric sidewall 203a, and the bottom surface of the embedded portion in the second semiconductor layer 2022 is in contact with the gate bottom wall 2011b. Such a design can realize the connection between the write transistor 202 and the read transistor 201 while making the embedded portion of the second semiconductor layer 2022 a part of the channel in the write transistor 202, so as to reduce the height of the second semiconductor layer 2022 protruding from the read transistor 201 while ensuring that the channel length of the write transistor 202 meets the requirements, that is, reduce the height of the extension portion in the second semiconductor layer 2022, thereby further reducing the vertical height of the storage unit.

[0039] In some embodiments, the insulating dielectric sidewall 203a may include a low dielectric material portion, which is made of a material with a dielectric constant lower than 3.0. This low dielectric material portion may horizontally surround the outer peripheral side of the embedded portion of the second semiconductor layer 2022 to reduce the parasitic capacitance generated between the second semiconductor layer 2022 and the first gate 2011.

[0040] In other embodiments, the insulating dielectric sidewall 203a may also include a silicon dioxide material layer, which horizontally surrounds the outer peripheral side of the embedded portion of the second semiconductor layer 2022, so as to achieve insulation between the embedded portion of the second semiconductor layer 2022 and the gate sidewall 2011a of the first gate 2011 while reducing material costs.

[0041] In some other embodiments, the insulating dielectric sidewall 203a may include a stacked structure in which a low dielectric material portion and a silicon dioxide material layer are nested together, thereby reducing material cost and parasitic capacitance.

[0042] In some embodiments of the present disclosure, reference Figure 1 As shown, the storage layer 2 may include a first signal line 204 and a second signal line 205 in addition to the storage unit. Figures 1 to 3As shown, a first signal line 204 is formed on a substrate 1, the first signal line 204 extends in a first horizontal direction X, and contacts the bottom surface of the first semiconductor layer 2012 and / or the bottom area of ​​the outer peripheral surface of the first semiconductor layer 2012; a second signal line 205 is formed on a side of the first signal line 204 away from the substrate 1, a first interlayer insulating layer 206 is formed between the layer where the second signal line 205 is located and the layer where the first signal line 204 is located, the second signal line 205 extends in a second horizontal direction Y intersecting with the first horizontal direction X, the second signal line 205 and the first interlayer insulating layer 206 horizontally surround the outer peripheral side of the first semiconductor layer 2012, and the second signal line 205 contacts the top area of ​​the outer peripheral surface of the first semiconductor layer 2012, wherein one of the first signal line 204 and the second signal line 205 is a read bit line, and the other is a read word line.

[0043] For example, the first signal line 204 and the second signal line 205 may be made of the same material, for example, both may be made of conductive materials such as metal tungsten, but not limited thereto, and may also be made of other materials with conductive properties. In addition, the first signal line 204 and the second signal line 205 may be signal lines made of a single material, but not limited thereto, and may also be composite signal lines formed by stacking multiple materials, depending on the specific situation. The first interlayer insulating layer 206 may be made of materials such as silicon dioxide, but not limited thereto, and may also be made of other insulating materials, depending on the specific situation.

[0044] refer to Figure 1 As shown, the first semiconductor layer 2012 of the read transistor 201 is formed on a side of the first signal line 204 away from the substrate 1, and the first semiconductor layer 2012 and the first gate insulating layer 2013 of the read transistor 201 can both be designed in a groove shape. In this embodiment, the first gate insulating layer 2013 and the first gate 2011 can be designed according to the shape of the first semiconductor layer 2012 and cooperate with each other, so as to simplify the process steps and reduce the process cost while ensuring the channel length of the read transistor 201.

[0045] For detailed description, refer to Figure 1 As shown, the first semiconductor layer 2012 may include a first semiconductor side wall 2012a and a first semiconductor bottom wall 2012b, the first semiconductor side wall 2012a is horizontally arranged around the first semiconductor bottom wall 2012b and extends in a direction away from the substrate 1, the first semiconductor side wall 2012a and the first semiconductor bottom wall 2012b form a first semiconductor groove, wherein the bottom surfaces of the first semiconductor side wall 2012a and the first semiconductor bottom wall 2012b are both in contact with the first signal line 204.

[0046] refer to Figure 1As shown, the first gate insulating layer 2013 includes a first gate insulating side wall 2013a and a first gate insulating bottom wall 2013b, the first gate insulating bottom wall 2013b is located in the first semiconductor groove and contacts the top surface of the first semiconductor bottom wall 2012b, the first gate insulating side wall 2013a is at least located in the first semiconductor groove and horizontally surrounds the first gate insulating bottom wall 2013b, the first gate insulating side wall 2013a extends in a direction away from the substrate 1, and forms a first gate insulating groove with the first gate insulating bottom wall 2013b, and the outer peripheral surface of the first gate insulating side wall 2013a contacts the inner peripheral surface of the first semiconductor side wall 2012a, wherein the gate bottom wall 2011b is located in the first gate insulating groove and contacts the top surface of the first gate insulating bottom wall 2013b, the gate side wall 2011a is at least located in the first gate insulating groove, and the outer peripheral surface of the gate side wall 2011a contacts the inner peripheral surface of the first gate insulating side wall 2013a.

[0047] In some embodiments, reference Figure 1 As shown, the top surface of the first semiconductor sidewall 2012a, the top surface of the first gate insulating sidewall 2013a and the top surface of the gate sidewall 2011a may be flush with the top surface of the second signal line 205; but not limited thereto, in other embodiments, refer to Figure 4 As shown, the top of the first semiconductor side wall 2012a has a first semiconductor overlap portion 2012c extending horizontally outward, and the first semiconductor overlap portion 2012c is formed on the top surface of the second signal line 205, the top of the first gate insulating side wall 2013a has a first gate insulating overlap portion 2013c extending horizontally outward, and the first gate insulating overlap portion 2013c is formed on the top surface of the first semiconductor overlap portion 2012c, and the top of the gate side wall 2011a has a gate overlap portion 2011c extending horizontally outward, and the gate overlap portion 2011c is formed on the top surface of the first gate insulating overlap portion 2013c.

[0048] In some embodiments of the present disclosure, reference Figure 1 As shown, the storage layer 2 may include a write bit line 207 and a write word line 208 in addition to the storage unit, the first signal line 204 and the second signal line 205. The write bit line 207 may be formed on the side of the second signal line 205 away from the substrate 1, and a second interlayer insulating layer 209 is formed between the layer where the write bit line 207 is located and the layer where the second signal line 205 is located. The write bit line 207 and the second interlayer insulating layer 209 horizontally surround the outer peripheral side of the extension of the second semiconductor layer 2022, and the write bit line 207 is in contact with the outer peripheral surface of the first semiconductor layer 2012; the write word line 208 may be formed on the side of the extension of the write bit line 207 and the second gate 2021 away from the substrate 1, and a third interlayer insulating layer 210 is formed between the layer where the write word line 208 is located and the layer where the write word line 207 is located, and the write word line 208 is connected to the top surface of the extension of the second gate 2021.

[0049] Among them, combined Figure 2 and Figure 3 As shown, the write bit line 207 can extend in the first horizontal direction X, and the write word line 208 can extend in the second horizontal direction Y, so that the area of ​​the overlapping region between the write bit line 207 and the second signal line 205 can be reduced, thereby reducing the generation of parasitic capacitance between the two; but not limited to this, the write bit line 207 can also extend in the second horizontal direction Y, and the write word line 208 can extend in the first horizontal direction X, depending on the specific situation.

[0050] For example, the material of the write word line 208 and the write bit line 207 can be the same, for example, both can be made of conductive materials such as metal tungsten, but not limited to this, and can also be made of other materials with conductive properties. In addition, the write word line 208 and the write bit line 207 can be signal lines made of a single material, but not limited to this, and can also be composite signal lines formed by stacking multiple materials, depending on the specific situation. The second interlayer insulating layer 209 and the third interlayer insulating layer 210 can be made of materials such as silicon dioxide, but not limited to this, and can also be made of other insulating materials, depending on the specific situation.

[0051] In some embodiments, reference Figure 1 and Figure 4 As shown, the top of the extension portion in the second semiconductor layer 2022 has a second semiconductor overlap portion 2022c extending horizontally outward, and the second semiconductor overlap portion 2022c is formed on the top surface of the write word line 208. The top of the extension portion in the second gate insulation layer 2023 has a second gate insulation overlap portion 2023c extending horizontally outward, and the second gate insulation overlap portion 2023c is formed on the top surface of the second semiconductor overlap portion 2022c. The top surface of the extension portion in the second gate 2021 is flush with the top surface of the second gate insulation overlap portion 2023c, and the storage layer 2 also includes a conductive contact pad 2024, the bottom surface of the conductive contact pad 2024 is in contact with the top surface of the second gate insulation overlap portion 2023c and the top surface of the extension portion in the second gate 2021, and the top surface of the conductive contact pad 2024 is in contact with the bottom surface of the write word line 208. This design can increase the contact area between the write transistor 202 and the write word line 208, thereby ensuring the connection stability.

[0052] For example, the conductive contact pad 2024 of the present embodiment may be integrally formed with the second gate 2021 to reduce the process cost, but is not limited thereto and may also be separately formed, depending on the specific situation.

[0053] In the embodiments of the present disclosure, Figure 2 and Figure 3As shown, the storage layer 2 may include a plurality of storage cells, and the plurality of storage cells are arranged in an array in a first horizontal direction X and a second horizontal direction Y. The number of first signal lines 204 is equal to the number of rows of the storage cell array structure, and the number of second signal lines 205 is equal to the number of rows of the storage cell array structure. The first signal lines 204 are arranged at intervals in the second horizontal direction Y, and each first signal line 204 is connected to the first semiconductor layer 2012 of the read transistor 201 in all storage cells in the corresponding row, and the second signal lines 205 are arranged at intervals in the first horizontal direction X, and each second signal line 205 is connected to the first semiconductor layer 2012 of the read transistor 201 in all storage cells in the corresponding column.

[0054] refer to Figure 2 and Figure 3 As shown, if the write bit lines 207 extend in the first horizontal direction X and the write word lines 208 extend in the second horizontal direction Y, the number of the write bit lines 207 is equal to the number of rows of the memory cell array structure, and the number of the write word lines 208 is equal to the number of rows of the memory cell array structure. The write bit lines 207 are arranged at intervals in the second horizontal direction Y, and each write bit line 207 is connected to the second semiconductor layer 2022 of the write transistor 202 in all the memory cells in the corresponding row, and the write word lines 208 are arranged at intervals in the first horizontal direction X, and each write word line 208 is connected to the second gate 2021 of the write transistor 202 in all the memory cells in the corresponding column.

[0055] If the write bit lines 207 extend in the second horizontal direction Y and the write word lines 208 extend in the first horizontal direction X, the number of the write bit lines 207 is equal to the number of columns of the memory cell array structure, and the number of the write word lines 208 is equal to the number of rows of the memory cell array structure. The write bit lines 207 are arranged at intervals in the first horizontal direction X, and each write bit line 207 is connected to the second semiconductor layer 2022 of the write transistor 202 in all the memory cells in the corresponding column, and the write word lines 208 are arranged at intervals in the second horizontal direction Y, and each write word line 208 is connected to the second gate 2021 of the write transistor 202 in all the memory cells in the corresponding row.

[0056] In this embodiment, vertically nested storage units are used to reduce the horizontal area they occupy, thereby reducing the space occupied by the storage units so that more storage units can be arranged in each storage layer 2 to improve the storage density of the storage layer 2.

[0057] In the embodiments of the present disclosure, reference Figure 5 and Figure 6As shown, the number of storage layers 2 can be multiple layers, and multiple storage layers 2 can be stacked in a direction perpendicular to the substrate 1. In this embodiment, the vertical height of the storage layer 2 can be reduced by adopting vertically nested storage units, so that more layers of storage layers 2 can be arranged when the height of the memory is constant to improve the storage density of the memory.

[0058] In some embodiments, the storage layer 2 close to the substrate 1 in two adjacent storage layers 2 is defined as the bottom storage layer, and the storage layer 2 far from the substrate 1 is defined as the top storage layer. Figure 5 As shown, in at least two adjacent storage layers 2: a fourth interlayer insulating layer 211 is formed between the layer where the first signal line 204 of the top storage layer is located and the layer where the write line 208 of the bottom storage layer is located. This design allows each storage layer 2 to be controlled more flexibly.

[0059] In other embodiments, reference Figure 6 As shown, in at least two adjacent storage layers 2: the write line 208 of the bottom storage layer can be shared as the first signal line 204 of the top storage layer. This design arranges more storage layers 2 at a certain height, thereby further improving the storage density of the memory.

[0060] The disclosed embodiments further provide a method for manufacturing a memory, which is used to manufacture the memory described in any of the aforementioned embodiments. The structure of the memory will not be described repeatedly below, and the manufacturing method of the memory will be mainly described in detail.

[0061] In an embodiment of the present disclosure, the method for manufacturing a memory may include step S100 and step S102.

[0062] In step S100: a substrate 1 is provided. For example, an insulating substrate layer 11 may be formed on a semiconductor substrate layer 10 to form the substrate 1. Figure 7 shown.

[0063] In step S102: at least one storage layer 2 is formed on the substrate 1. The step of forming the storage layer 2 may at least include:

[0064] Step S1021, forming a read transistor 201 on the substrate 1. The read transistor 201 of this embodiment has a gate groove;

[0065] Step S1022 , forming a write transistor 202 at the gate groove of the read transistor 201 to form a memory cell.

[0066] Combine the following Figures 1 to 24 The manufacturing method of forming a storage layer on a substrate 1 disclosed in the present invention is described in detail.

[0067] In some embodiments of the present disclosure, before step S1021, the step of forming the storage layer 2 may further include step S10200, step S10201, step S10202, and step S10203.

[0068] In step S10200: a first signal line 204 is formed on the substrate 1, and the first signal line 204 extends in a first horizontal direction X. Figure 8 For example, a first metal film covering the entire surface may be deposited on the insulating substrate layer 11 of the substrate 1, and then the first metal film may be patterned to form a plurality of first signal lines 204 spaced apart in the second horizontal direction Y, as shown in FIG. Fig. 9 shown.

[0069] Among them, continue to refer to Fig. 9 As shown, a first insulating isolation column 212 may be formed between adjacent first signal lines 204 to achieve mutual insulation between adjacent first signal lines 204, and the top surface of the first insulating isolation column 212 may be flush with the top surface of the first signal line. It should be noted that the first insulating isolation column 212 may be formed on the substrate 1 before the first signal line 204, or the first signal line 204 may be formed on the substrate 1 before the first insulating isolation column 212.

[0070] In step S10201: a first interlayer insulating layer 206 is formed on the top surface of the first signal line 204. For example, after forming a plurality of first signal lines 204 spaced apart in the second horizontal direction Y, the first interlayer insulating layer 206 covering the entire surface may be deposited. In addition to covering the top surface of the first signal line 204, the first interlayer insulating layer 206 may also cover the top surface of the first insulating isolation column 212. Afterwards, the top surface of the first interlayer insulating layer 206 may be polished into a flat surface by a chemical mechanical polishing process.

[0071] It should be noted that if the first insulating isolation column 212 is formed after the first signal line 204, the first interlayer insulating layer 206 can be integrally formed with the first insulating isolation column 212, but is not limited to this, and can also be formed separately, that is: the first insulating isolation column 212 is formed first, and then the first interlayer insulating layer 206 is formed.

[0072] In step S10202 , a second signal line 205 is formed on the top surface of the first interlayer insulating layer 206 . The second signal line 205 extends in the second horizontal direction Y, and an orthographic projection of the second signal line 205 on the substrate 1 and an orthographic projection of the first signal line 204 on the substrate 1 have a first overlapping region.

[0073] For example, step S10202 may include steps S102021 and S102022. In step S102021: firstly, a second metal film 205a covering the entire surface is deposited on the top surface of the first interlayer insulating layer 206, referring to Fig.10 In step S102022 : the second metal film 205 a is patterned to form a plurality of second signal lines 205 arranged in a first horizontal direction X at intervals.

[0074] In step S10203 : a first receiving hole 213 is formed, the orthographic projection of the first receiving hole 213 on the substrate 1 is located in the first overlapping area, the first receiving hole 213 penetrates the second signal line 205 and the first interlayer insulating layer 206 , and exposes the first signal line 204 .

[0075] Among them, reference Fig.11 As shown, step S10203 can be performed after step S102021 and before step S102022. In this case, the first accommodating hole 213 penetrating the second signal line 205 mentioned in step S10203 can be understood as the first accommodating hole 213 penetrating the part of the second metal film 205a used to form the second signal line 205; it should be understood that step S10203 can also be performed after step S102022 is executed, depending on the specific circumstances.

[0076] For example, refer to Fig.11 As shown, the first receiving hole 213 can extend to the inside of the first signal line 204, so as to ensure the contact area between the subsequently formed read transistor 201 and the first signal line 204, but it is not limited thereto, the first receiving hole 213 can also just extend to the top surface of the first signal line 204, or the first receiving hole 213 can also pass through the first signal line 204, depending on the specific situation. In addition, the first receiving hole 213 of this embodiment can have multiple, and they are arranged in an array in the first horizontal direction X and the second horizontal direction Y, with reference to Fig.12 shown.

[0077] In some embodiments of the present disclosure, the step of forming the read transistor 201 may include: forming a first semiconductor layer 2012, a first gate insulating layer 2013 and a first gate 2011 in the first accommodating hole 213, the first semiconductor layer 2012 at least horizontally surrounds the outer peripheral side of the first gate 2011, the first gate insulating layer 2013 is formed between the first gate 2011 and the first semiconductor layer 2012, the first gate 2011 includes a gate bottom wall 2011b and a gate side wall 2011a, the gate side wall 2011a is horizontally arranged around the gate bottom wall 2011b and extends in a direction away from the substrate 1, and the gate side wall 2011a and the gate bottom wall 2011b form a gate groove; wherein the first signal line 204 may contact the bottom surface of the first semiconductor layer 2012 and / or the bottom area of ​​the outer peripheral surface of the first semiconductor layer 2012, and the second signal line 205 surrounds the outer peripheral side of the first semiconductor layer 2012 and contacts the top area of ​​the outer peripheral surface of the first semiconductor layer 2012.

[0078] It should be noted that step S102022 can be performed after forming the read transistor 201, but is not limited thereto. It can also be performed before forming the read transistor 201, depending on the specific situation.

[0079] In detail, the steps of forming the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate electrode 2011 include step S10210, step S10211, step S10212, step S10213 and step S10214.

[0080] In step S10210: a first semiconductor film 214 is formed on the substrate 1, referring to Fig.13 As shown, the first semiconductor film 214 completely covers the top surface of the second signal line 205, the hole wall surface of the first receiving hole 213, and the exposed surface of the first signal line 204 exposed by the first receiving hole 213. For example, the first semiconductor film 214 can be deposited by atomic layer deposition process, and the first semiconductor film 214 can be formed in accordance with the shape of the underlying structural layer. It should be understood that the portion of the first semiconductor film 214 located in the first receiving hole 213 belongs to the first semiconductor layer 2012 mentioned above.

[0081] It should be noted that if step S102022 is performed after forming the read transistor 201, the first semiconductor film 214 in step S10210 can completely cover the top surface of the second signal line 205, which can be understood as the first semiconductor film 214 covering the second metal film 205a. Fig.13 shown.

[0082] In step S10211: a first gate insulating film 215 is formed on the first semiconductor film 214, and the first gate insulating film 215 completely covers the first semiconductor film 214. Fig.13 As shown. For example, the first gate insulating film 215 can be deposited by atomic layer deposition process, and the first gate insulating film 215 can be formed in accordance with the shape of the underlying structural layer. It should be understood that the portion of the first gate insulating film 215 located in the first receiving hole 213 belongs to the first gate insulating layer 2013 mentioned above.

[0083] In step S10212: a first conductive film 216 is formed on the first gate insulating film 215, and the first conductive film 216 completely covers the first gate insulating film 215. Fig.13 For example, the first conductive film 216 may be deposited by atomic layer deposition, and the first conductive film 216 may be formed in accordance with the shape of the underlying structural layer. It should be understood that the portion of the first conductive film 216 located in the first receiving hole 213 belongs to the first gate 2011.

[0084] In step S10213: a filling film layer 217 is formed on the first conductive film 216, the filling film layer 217 completely covers the first conductive film 216, and fills the first receiving hole 213. The filling film layer 217 may include an insulating dielectric film 217a and a sacrificial material film 217b formed on the insulating dielectric film 217a, and the insulating dielectric film 217a completely covers the first conductive film 216.

[0085] The portion of the insulating dielectric film 217a located at the gate groove belongs to the insulating dielectric portion 203. The insulating dielectric portion 203 may include an insulating dielectric sidewall 203a and an insulating dielectric bottom wall 203b, wherein the insulating dielectric sidewall 203a is horizontally arranged around the insulating dielectric bottom wall 203b and extends in a direction away from the substrate 1, and the insulating dielectric sidewall 203a and the insulating dielectric bottom wall 203b form an insulating dielectric groove; and the sacrificial material film 217b completely covers the insulating dielectric film 217a and fills the first receiving hole 213.

[0086] For example, after depositing the sacrificial material film 217b to completely cover the insulating dielectric film 217a and filling the first receiving hole 213, the sacrificial material film 217b can also be polished using a chemical mechanical polishing process to make the top surface of the sacrificial material film 217b a flat plane, which is beneficial to the accuracy of subsequent processes.

[0087] In some embodiments, the material of the insulating dielectric film 217a may be a low dielectric material, and the material of the sacrificial material film 217b may be a polysilicon material or a silicon dioxide material. It can also be understood that the insulating dielectric portion 203 may include a low dielectric material portion, and the sacrificial material portion may include a polysilicon material layer or a silicon dioxide material layer.

[0088] In step S10214: the portions of the filling film layer 217, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213 are completely removed to expose the second signal line 205, and at the same time, the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate 2011 are formed.

[0089] It should be noted that if step S102022 is performed after forming the read transistor 201 , the exposure of the second signal line 205 mentioned in step S10214 may be understood as exposing at least a portion of the second metal film 205 a used to form the second signal line 205 .

[0090] In some embodiments, the step of completely removing portions of the filling film layer 217, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213 may include: step S102140, step S102141, step S102142, step S102143, step S102144 and step S102145.

[0091] In step S102140: remove the portion of the filling film layer 217 that is higher than the top surface of the first conductive film 216 to expose the top surface of the first conductive film 216. Fig.14 shown.

[0092] In step S102141: continue to etch away the portion of the filling film layer 217 that is higher than the top surface of the second signal line 205, so that the top surface of the filling reserved portion retained in the filling film layer 217 is flush with the top surface of the second signal line 205, referring to Fig.15 shown.

[0093] It should be noted that if step S102022 is performed after forming the read transistor 201, the step S10214 mentioned in which the top surface of the filling reserved portion retained in the filling film layer 217 is made flush with the top surface of the second signal line 205 can be understood as making the top surface of the filling reserved portion retained in the filling film layer 217 flush with the top surface of the second metal film 205a.

[0094] Among them, reference Fig.15 As shown, the filling and retaining portion may include an insulating dielectric portion 203 and a sacrificial material portion 218 . The insulating dielectric portion 203 may be located at the gate groove of the first gate 2011 , and the sacrificial material portion 218 may fill the insulating dielectric groove of the insulating dielectric portion 203 .

[0095] For example, when the material of the insulating dielectric film 217a in the filling film layer 217 is a low dielectric material and the material of the sacrificial material film 217b is a polysilicon material, in step S102140 and step S102141, Cl2 (chlorine) and CHF3 (trifluoromethane) can be used to etch the filling film layer 217. It should be understood that during etching, attention should be paid to the flatness of the filling reserved portion retained in the filling film layer 217.

[0096] In step S102142: a protective film layer 219 is formed on the top surface of the first conductive film 216 and the top surface of the filling reserved portion, referring to Fig.16 As shown. The protective film layer 219 is used to protect the filling reserved portion during the subsequent etching process. It should be understood that the top surface of the formed protective film layer 219 can be understood as a horizontal plane, and this horizontal plane can be a plane parallel or approximately parallel to the substrate 1.

[0097] Wherein, under the same etching conditions, the etching rate of the protective film layer 219 is lower than the etching rates of the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214. For example, the protective film layer 219 of the present embodiment may be a carbon coating (Spin-On-Carbon, SOC for short), but is not limited thereto, as long as the etching rate of the protective film layer 219 can be lower than the etching rates of the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214.

[0098] In step S102143: the first etchant is used to etch away the portion of the protective film layer 219 that is higher than the top surface of the first conductive film 216, so that the remaining protective portion 2190 of the protective film layer 219 that is retained at the filling retention portion is flush with the top surface of the first conductive film 216, referring to Fig.17 In the embodiment of the present disclosure, the first etchant may be an etching gas; for example, when the protective film layer 219 is a carbon coating, the first etchant may include a mixed gas of CF4 (carbon tetrafluoride) and O2 (oxygen).

[0099] In step S102144: a second etchant is used to completely remove the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are higher than the top surface of the second signal line 205 to form a first semiconductor layer 2012, a first gate insulating layer 2013, and a first gate 2011. At the same time, a portion of the height of the remaining protection portion 2190 is etched away by the second etchant, and a portion of the remaining protection portion 2190 is left covering the filling reserved portion. Fig.18 shown.

[0100] In the embodiment of the present disclosure, the second etchant may be an etching gas; for example, the second etchant may include a mixed gas containing fluorine, chlorine and oxygen, such as: the second etchant may include a mixed gas of CF4, Cl2 (chlorine) and O2, which has a relatively low etching selectivity for the first conductive film material, the first gate insulating film material and the first semiconductor film material, and can improve the etching uniformity, so that the top surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate 2011 are flush.

[0101] In step S102145: a third etchant is used to completely remove the remaining portion of the remaining protection portion 2190 on the filling reserved portion, referring to Fig.19 As shown, the top surfaces of the first semiconductor layer 2012 , the first gate insulating layer 2013 , the first gate electrode 2011 and the filling reserved portion are flush with the top surface of the second signal line 205 , and the outside of the target range is a position outside the first receiving hole 213 .

[0102] It should be noted that if step S102022 is performed after forming the read transistor 201, the top surfaces of the first semiconductor layer 2012, the first gate insulation layer 2013, the first gate electrode 2011 and the filling retention portion mentioned in step S10215 are flush with the top surface of the second signal line 205, which can be understood as the top surfaces of the first semiconductor layer 2012, the first gate insulation layer 2013, the first gate electrode 2011 and the filling retention portion are flush with the top surface of the second metal film 205a.

[0103] In the embodiment of the present disclosure, an ash or wet cleaning method may be used to completely remove the remaining portion of the protective portion 2190 remaining on the filling film layer 217. When the ash method is used, the third etchant may be an Asher gas. For example, the Asher gas may include oxygen.

[0104] It should be noted that if the material of the insulating dielectric portion 203 is a low dielectric material, then in step S102145, it is important to select an Asher gas ratio to reduce oxidation of the low dielectric material, thereby reducing the formation of defects in the insulating dielectric portion 203.

[0105] In some other embodiments, the step of completely removing the portions of the filling film layer 217 , the first conductive film 216 , the first gate insulating film 215 and the first semiconductor film 214 that are outside the target range of the first receiving hole 213 may include: step S102146 and step S102147.

[0106] In step S102146: the portion of the sacrificial material film 217b that is higher than the top surface of the insulating dielectric film 217a is removed to expose the top surface of the insulating dielectric film 217a. The sacrificial material film 217b that remains inside the insulating dielectric groove is divided into a sacrificial material portion 218. The top surface of the sacrificial material portion 218 is flush with the top surface of the insulating dielectric film 217a. Fig. 20 shown.

[0107] In step S102147: the insulating dielectric film 217a, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 are etched away in a portion outside the target range of the first receiving hole 213 to form the insulating dielectric portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate electrode 2011. Fig.21 As shown. The outside of the target range is an area whose distance from the hole boundary of the first receiving hole 213 exceeds the target value, and the target value is greater than 0, so that the top of the first semiconductor layer 2012 is formed with a first semiconductor overlap portion 2012c extending horizontally outward, and the first semiconductor overlap portion 2012c is formed on the top surface of the second signal line 205, the top of the first gate insulation layer 2013 has a first gate insulation overlap portion 2013c extending horizontally outward, and the first gate insulation overlap portion 2013c is formed on the top surface of the first semiconductor overlap portion 2012c, the top of the gate sidewall 2011a has a gate overlap portion 2011c extending horizontally outward, and the gate overlap portion 2011c is formed on the top surface of the first gate insulation overlap portion 2013c, and the top of the insulating medium sidewall 203a has an insulating medium overlap portion 203c extending horizontally outward, and the insulating medium overlap portion 203c is formed on the top surface of the gate overlap portion 2011c.

[0108] It should be noted that if step S102022 is performed after forming the read transistor 201, the first semiconductor overlap portion 2012c mentioned in step S10214 is formed on the top surface of the second signal line 205, which can be understood as the first semiconductor overlap portion 2012c is formed on the top surface of the second metal film 205a.

[0109] For example, in step S102147: the insulating dielectric film 217a, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 that are located outside the target range of the first receiving hole 213 can be etched away by a photolithography process to form the insulating dielectric portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate electrode 2011; specifically, after step S102146, a BARC material layer and a photoresist layer covering the entire surface can be formed in sequence, and then, by using The BARC material layer and the photoresist layer are patterned by a mask so that the BARC material layer and the photoresist layer are formed into a mask structure with a target pattern, and then the mask structure is used for an etching process to etch away the portions of the insulating dielectric film 217a, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 that are outside the target range of the first accommodating hole 213, thereby forming an insulating dielectric portion 203, a first semiconductor layer 2012, a first gate insulating layer 2013 and a first gate electrode 2011.

[0110] Among them, the BARC (Bottom Anti-Reflection Coating) material layer is mainly used to reduce the amount of light reflected back to the photoresist layer during the exposure process to reduce the standing wave effect and help improve the accuracy of the photolithography process. The BARC material layer can be formed by spin coating, and its main components include cross-linkable resin, thermal acid generator, surfactant and solvent to reduce the interference of light.

[0111] It should be understood that after forming the insulating dielectric portion 203 , the first semiconductor layer 2012 , the first gate insulating layer 2013 and the first gate 2011 , the mask structure formed by the BARC material layer and the photoresist layer may be removed.

[0112] For example, step S102022 of this embodiment may be executed after step S102147.

[0113] In some embodiments of the present disclosure, the step of forming the write transistor 202 may include step S10220 , step S10221 , step S10222 , and step S10223 .

[0114] In step S10220: a second interlayer insulating layer 209 is formed on the top surfaces of the read transistor 201, the insulating dielectric portion 203 and the sacrificial material portion 218. It should be understood that the second interlayer insulating layer 209 may cover the entire structure layer located thereunder, and the top surface of the second interlayer insulating layer 209 may be a plane parallel or approximately parallel to the substrate 1 to ensure the flatness of subsequent film layer formation.

[0115] In step S10221: a write bit line 207 is formed on the side of the second interlayer insulating layer 209 away from the substrate 1, and the orthographic projection of the write bit line 207 on the substrate 1 completely covers the orthographic projection of the sacrificial material portion 218 on the substrate 1, referring to Fig. 22 As shown. For example, a third metal film covering the entire surface may be deposited on the top surface of the second interlayer insulating layer 209, and then the third metal film may be patterned to form a plurality of write bit lines 207 spaced apart in the second horizontal direction Y (or the first horizontal direction X). A second insulating isolation column may be provided between adjacent write bit lines 207, and the top surface of the second insulating isolation column may be flush with the top surface of the write bit line 207 to ensure the flatness of subsequent film formation.

[0116] In this embodiment, the second insulating isolation column may be formed before the write bit line 207, or the write bit line 207 may be formed before the second insulating isolation column, depending on the specific situation.

[0117] In step S10222: the sacrificial material portion 218 and the insulating dielectric bottom wall 203b of the insulating dielectric portion 203 are completely etched, and the second interlayer insulating layer 209 and the write bit line 207 are completely etched on the sacrificial material portion 218 to form a second receiving hole 220, and the second receiving hole 220 exposes a portion of the gate bottom wall 2011b. The insulating dielectric side wall 203a of the insulating dielectric portion 203 is retained. For example, the second receiving hole 220 can just extend to the inside of the gate bottom wall 2011b, so that the area at which the storage node is subsequently formed can be guaranteed, thereby ensuring the storage capacitor, but it is not limited to this, refer to Fig.23 As shown, the second receiving hole 220 may also just extend to the top surface of the grid bottom wall 2011b, or the second receiving hole 220 may also penetrate the grid bottom wall 2011b, depending on the specific situation. In addition, it should be understood that the second receiving hole 220 of this embodiment may have multiple, and arranged in an array in the first horizontal direction X and the second horizontal direction Y.

[0118] In step S10223: a second semiconductor layer 2022, a second gate insulating layer 2023 and a second gate electrode 2021 are formed in the second receiving hole 220, referring to Fig.24 For example, the second semiconductor layer 2022, the second gate insulating layer 2023 and the second gate 2021 may correspond to the manufacturing method of the first semiconductor layer 2012, the second gate insulating layer 2023 and the second gate 2021, which will not be described in detail herein.

[0119] It should be noted that after forming the write transistor 202, the step of forming the storage layer 2 may further include sequentially forming a third interlayer insulating layer 210 and a write word line 208, as shown in FIG. Figure 3 As shown, no further elaboration is given here.

[0120] Among them, if reference Figure 5 As shown in the figure, in two adjacent storage layers 2, the first signal line 204 of the top storage layer is not shared with the write word line 208 of the bottom storage layer. Therefore, before forming the first signal line 204 of the top storage layer, a first signal line 204 of the top storage layer is formed. Figure 5 The fourth interlayer insulating layer 211 shown in FIG. Figure 6 As shown in the figure, in two adjacent storage layers 2, the first signal line 204 of the top storage layer is shared with the write line 208 of the bottom storage layer, so the production of one insulating layer and the signal line can be omitted, that is, the step of producing the fourth interlayer insulating layer 211 and the first signal line 204 in the top storage layer is omitted, so as to reduce the production cost and improve the storage density.

[0121] In addition, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third", "fourth" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0122] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0123] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A memory device comprising a substrate and at least one storage layer, wherein the storage layer is formed on the substrate and comprises a storage unit, wherein: The storage unit comprises: A read transistor, comprising a first gate, a first semiconductor layer at least horizontally surrounding an outer peripheral side of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer, wherein the first gate comprises a gate bottom wall and a gate side wall, wherein the gate side wall horizontally surrounds the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall form a gate groove; A write transistor includes a second gate, a second semiconductor layer at least horizontally surrounding the outer peripheral side of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, wherein a portion of the second semiconductor layer is embedded in the gate groove and contacts with at least a portion of the gate groove.

2. The memory according to claim 1, characterized in that: The second semiconductor layer, the second gate and the second gate insulating layer all have an embedded portion embedded in the gate groove and an extending portion located on a side of the embedded portion away from the substrate, and the extending portion protrudes in a direction away from the substrate relative to the read transistor.

3. The memory according to claim 2, characterized in that: The memory cell further comprises an insulating dielectric sidewall, the insulating dielectric sidewall being embedded in the gate groove and horizontally surrounding an outer peripheral side of the embedded portion in the second semiconductor layer; The outer peripheral surface of the embedded portion in the second semiconductor layer is insulated from the gate sidewall by the insulating medium sidewall, and the bottom surface of the embedded portion in the second semiconductor layer is in contact with the gate bottom wall.

4. The memory according to claim 3, characterized in that: The insulating medium sidewall comprises a low dielectric material portion, and the low dielectric material portion horizontally surrounds the outer peripheral side of the embedded portion of the second semiconductor layer; and / or The insulating medium sidewall includes a silicon dioxide material layer, and the silicon dioxide material layer horizontally surrounds the outer peripheral side of the embedded portion of the second semiconductor layer.

5. The memory according to claim 3, characterized in that: The embedded portion of the second semiconductor layer includes a second semiconductor side wall and a second semiconductor bottom wall, the second semiconductor side wall is horizontally arranged around the second semiconductor bottom wall and extends in a direction away from the substrate, the second semiconductor side wall and the second semiconductor bottom wall form a second semiconductor groove, and the embedded portion of the second gate and the embedded portion of the second gate insulating layer are located in the second semiconductor groove; Wherein, the bottom surface of the second semiconductor bottom wall and the bottom surface of the second semiconductor side wall are both in contact with the bottom surface of the gate groove.

6. The memory according to claim 1, characterized in that: The storage layer also includes: A first signal line is formed on the substrate, the first signal line extends in a first horizontal direction and contacts a bottom surface of the first semiconductor layer and / or a bottom area of ​​an outer peripheral surface of the first semiconductor layer; a second signal line formed on a side of the first signal line away from the substrate, a first interlayer insulating layer formed between a layer where the second signal line is located and a layer where the first signal line is located, the second signal line extending in a second horizontal direction intersecting the first horizontal direction, the second signal line and the first interlayer insulating layer horizontally surrounding an outer peripheral side of the first semiconductor layer, and the second signal line contacting a top area of ​​an outer peripheral surface of the first semiconductor layer; Among them, one of the first signal line and the second signal line is a read bit line, and the other is a read word line.

7. The memory according to claim 6, characterized in that: The first semiconductor layer is formed on a side of the first signal line away from the substrate, the first semiconductor layer comprises a first semiconductor side wall and a first semiconductor bottom wall, the first semiconductor side wall is horizontally arranged around the first semiconductor bottom wall and extends in a direction away from the substrate, and the first semiconductor side wall and the first semiconductor bottom wall form a first semiconductor groove; The first gate insulating layer comprises a first gate insulating sidewall and a first gate insulating bottom wall, the first gate insulating bottom wall is located in the first semiconductor groove and contacts with the top surface of the first semiconductor bottom wall, the first gate insulating sidewall is at least located in the first semiconductor groove and horizontally surrounds the first gate insulating bottom wall, the first gate insulating sidewall extends in a direction away from the substrate and forms a first gate insulating groove with the first gate insulating bottom wall, and the outer peripheral surface of the first gate insulating sidewall contacts with the inner peripheral surface of the first semiconductor sidewall; The gate bottom wall is located in the first gate insulation groove and contacts the top surface of the first gate insulation bottom wall, the gate side wall is at least located in the first gate insulation groove, and the outer peripheral surface of the gate side wall contacts the inner peripheral surface of the first gate insulation side wall.

8. The memory according to claim 7, characterized in that: The top surface of the first semiconductor side wall, the top surface of the first gate insulating side wall and the top surface of the gate side wall are flush with the top surface of the second signal line; or The top of the first semiconductor side wall has a first semiconductor overlap portion extending horizontally outward, and the first semiconductor overlap portion is formed on the top surface of the second signal line. The top of the first gate insulation side wall has a first gate insulation overlap portion extending horizontally outward, and the first gate insulation overlap portion is formed on the top surface of the first semiconductor overlap portion. The top of the gate side wall has a gate overlap portion extending horizontally outward, and the gate overlap portion is formed on the top surface of the first gate insulation overlap portion.

9. The memory according to claim 6, characterized in that: The storage layer also includes: A write bit line is formed on a side of the second signal line away from the substrate, a second interlayer insulating layer is formed between a layer where the write bit line is located and a layer where the second signal line is located, the write bit line and the second interlayer insulating layer horizontally surround the outer peripheral side of the extension portion of the second semiconductor layer, and the write bit line contacts the outer peripheral surface of the first semiconductor layer; A write word line is formed on a side of the write bit line and the extension of the second gate away from the substrate, a third interlayer insulating layer is formed between the layer where the write word line is located and the layer where the write bit line is located, and the write word line is connected to the top surface of the extension of the second gate; One of the write bit line and the write word line extends in the first horizontal direction, and the other extends in the second horizontal direction.

10. The memory according to claim 9, characterized in that: The write bit lines extend in the first horizontal direction, and the write word lines extend in the second horizontal direction; and / or The top of the extension portion in the second semiconductor layer has a second semiconductor overlap portion extending horizontally outward, and the second semiconductor overlap portion is formed on the top surface of the write bit line. The top of the extension portion in the second gate insulation layer has a second gate insulation overlap portion extending horizontally outward, and the second gate insulation overlap portion is formed on the top surface of the second semiconductor overlap portion. The top surface of the extension portion in the second gate is flush with the top surface of the second gate insulation overlap portion, and the storage layer also includes a conductive contact pad, the bottom surface of the conductive contact pad is in contact with the top surface of the second gate insulation overlap portion and the top surface of the extension portion in the second gate, and the top surface of the conductive contact pad is in contact with the bottom surface of the write word line.

11. The memory according to claim 9, characterized in that: The number of the storage layers is multiple, and the multiple storage layers are stacked in a direction perpendicular to the substrate. The storage layer close to the substrate in two adjacent storage layers is defined as a bottom storage layer, and the storage layer far from the substrate is defined as a top storage layer, wherein: In at least two adjacent storage layers: a fourth interlayer insulating layer is formed between a layer where the first signal line of the top storage layer is located and a layer where the write word line of the bottom storage layer is located; and / or In at least two adjacent memory layers: the write word line of the bottom memory layer is shared as the first signal line of the top memory layer.

12. A method for manufacturing a memory, characterized in that: The manufacturing method comprises: providing a substrate; At least one storage layer is formed on the substrate, wherein the step of forming the storage layer comprises: A read transistor is formed on the substrate, the read transistor comprising a first gate, a first semiconductor layer at least horizontally surrounding an outer peripheral side of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer, the first gate comprising a gate bottom wall and a gate side wall, the gate side wall is horizontally arranged around the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall form a gate groove; A write transistor is formed at the gate groove to form a storage unit, the write transistor including a second gate, a second semiconductor layer at least horizontally surrounding the outer peripheral side of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, a portion of the second semiconductor layer is embedded in the gate groove and contacts with at least a portion of the gate groove.

13. The manufacturing method according to claim 12, characterized in that: Before the step of forming the read transistor, the step of forming the storage layer further includes: forming a first signal line on the substrate, wherein the first signal line extends in a first horizontal direction; forming a first interlayer insulating layer on a top surface of the first signal line; forming a second signal line on the top surface of the first interlayer insulating layer, the second signal line extending in a second horizontal direction, and an orthographic projection of the second signal line on the substrate and an orthographic projection of the first signal line on the substrate having a first overlapping region; A first receiving hole is formed, wherein the orthographic projection of the first receiving hole on the substrate is located within the first overlapping region, and the first receiving hole penetrates the second signal line and the first interlayer insulating layer and exposes the first signal line.

14. The manufacturing method according to claim 13, characterized in that: The steps of forming the read transistor include: The first semiconductor layer, the first gate insulating layer and the first gate are formed in the first receiving hole, the first semiconductor layer at least horizontally surrounds the outer peripheral side of the first gate, the first gate insulating layer is formed between the first gate and the first semiconductor layer, the first gate includes a gate bottom wall and a gate side wall, the gate side wall is horizontally arranged around the gate bottom wall and extends in a direction away from the substrate, and the gate side wall and the gate bottom wall form a gate groove; The first signal line contacts the bottom surface of the first semiconductor layer and / or the bottom area of ​​the peripheral surface of the first semiconductor layer, and the second signal line surrounds the peripheral side of the first semiconductor layer and contacts the top area of ​​the peripheral surface of the first semiconductor layer.

15. The manufacturing method according to claim 14, characterized in that: The step of forming the first semiconductor layer, the first gate insulating layer and the first gate electrode comprises: forming a first semiconductor film on the substrate, wherein the first semiconductor film completely covers the top surface of the second signal line, the hole wall surface of the first receiving hole, and the exposed surface of the first signal line exposed by the first receiving hole, wherein a portion of the first semiconductor film located in the first receiving hole belongs to the first semiconductor layer; forming a first gate insulating film on the first semiconductor film, wherein the first gate insulating film completely covers the first semiconductor film, wherein a portion of the first gate insulating film located in the first receiving hole belongs to the first gate insulating layer; forming a first conductive film on the first gate insulating film, wherein the first conductive film completely covers the first gate insulating film, wherein a portion of the first conductive film located in the first receiving hole belongs to the first gate; forming a filling film layer on the first conductive film, wherein the filling film layer completely covers the first conductive film and fills the first receiving hole; The portions of the filling film layer, the first conductive film, the first gate insulating film and the first semiconductor film that are outside the target range of the first accommodating hole are completely removed to expose the second signal line, and the first semiconductor layer, the first gate insulating layer and the first gate are formed at the same time.

16. The manufacturing method according to claim 15, characterized in that: The step of completely removing the portions of the filling film layer, the first conductive film, the first gate insulating film and the first semiconductor film that are outside the target range of the first receiving hole comprises: removing a portion of the filling film layer that is higher than the top surface of the first conductive film to expose the top surface of the first conductive film; Etching away a portion of the filling film layer that is higher than a top surface of the second signal line, so that a top surface of a filling reserved portion retained in the filling film layer is flush with a top surface of the second signal line; forming a protective film layer on the top surface of the first conductive film and the top surface of the filling reserved portion, wherein the top surface of the protective film layer is a horizontal surface, and under the same etching conditions, the etching rate of the protective film layer is lower than the etching rates of the first conductive film, the first gate insulating film and the first semiconductor film; Using a first etchant to etch away a portion of the protective film layer that is higher than the top surface of the first conductive film, so that a remaining protective portion of the protective film layer that is retained at the filling retention portion is flush with the top surface of the first conductive film; Using a second etchant to completely remove the first conductive film, the first gate insulating film, and the first semiconductor film that are higher than the top surface of the first signal line, so as to form the first semiconductor layer, the first gate insulating layer, and the first gate electrode, and at the same time, the remaining protection portion is etched away by a portion of its height under the action of the second etchant, and a portion of the remaining protection portion is left to cover the filling reserved portion; Using a third etchant to completely remove the portion of the remaining protection portion remaining on the filling retention portion; The top surfaces of the first semiconductor layer, the first gate insulating layer, the first gate electrode and the filling retention portion are flush with the top surface of the second signal line, and the outside of the target range is a position outside the first accommodating hole.

17. The manufacturing method according to claim 16, characterized in that: The filling and retaining portion comprises: an insulating dielectric portion, located at the gate groove of the first gate, the insulating dielectric portion comprising an insulating dielectric bottom wall and an insulating dielectric side wall, the insulating dielectric side wall being horizontally arranged around the insulating dielectric bottom wall and extending in a direction away from the substrate, the insulating dielectric side wall and the insulating dielectric bottom wall forming an insulating dielectric groove; The sacrificial material portion is filled in the insulating medium groove.

18. The manufacturing method according to claim 15, characterized in that: The filling film layer includes an insulating dielectric film and a sacrificial material film formed on the insulating dielectric film, the insulating dielectric film completely covers the first conductive film, and the portion of the insulating dielectric film located at the gate groove belongs to the insulating dielectric portion, the insulating dielectric portion includes an insulating dielectric bottom wall and an insulating dielectric side wall, the insulating dielectric side wall is horizontally arranged around the insulating dielectric bottom wall and extends in a direction away from the substrate, the insulating dielectric side wall and the insulating dielectric bottom wall form an insulating dielectric groove, the sacrificial material film completely covers the insulating dielectric film, and is filled at the first receiving hole; The step of completely removing the portions of the filling film layer, the first conductive film, the first gate insulating film and the first semiconductor film that are outside the target range of the first receiving hole comprises: Etching away a portion of the sacrificial material film that is higher than the top surface of the insulating dielectric film to expose the top surface of the insulating dielectric film, wherein the portion of the sacrificial material film that is retained inside the insulating dielectric groove is divided into a sacrificial material portion, and the top surface of the sacrificial material portion is flush with the top surface of the insulating dielectric film; Etching away the portions of the insulating dielectric film, the first conductive film, the first gate insulating film and the first semiconductor film that are outside the target range of the first receiving hole to form the insulating dielectric portion, the first semiconductor layer, the first gate insulating layer and the first gate electrode; Among them, the area outside the target range is the area where the distance from the hole boundary of the first accommodating hole exceeds the target value, and the target value is greater than 0, so that the top of the first semiconductor layer is formed with a first semiconductor overlap portion extending horizontally outward, and the first semiconductor overlap portion is formed on the top surface of the second signal line, the top of the first gate insulation layer has a first gate insulation overlap portion extending horizontally outward, and the first gate insulation overlap portion is formed on the top surface of the first semiconductor overlap portion, the top of the gate side wall has a gate overlap portion extending horizontally outward, and the gate overlap portion is formed on the top surface of the first gate insulation overlap portion, and the top of the insulating medium side wall has an insulating medium overlap portion extending horizontally outward, and the insulating overlap portion is formed on the top surface of the gate overlap portion.

19. The manufacturing method according to claim 17 or 18, characterized in that: The insulating medium sidewall includes a low dielectric material portion, and the sacrificial material portion includes a polysilicon material layer or a silicon dioxide material layer.

20. The manufacturing method according to claim 17 or 18, characterized in that: The steps of forming the write transistor include: forming a second interlayer insulating layer on top surfaces of the read transistor, the insulating dielectric portion, and the sacrificial material portion; forming a write bit line on a side of the second interlayer insulating layer away from the substrate, wherein the orthographic projection of the write bit line on the substrate completely covers the orthographic projection of the sacrificial material portion on the substrate; Completely etching the sacrificial material portion and the bottom wall of the insulating medium, and completely etching the second interlayer insulating layer and the portion of the write bit line located on the sacrificial material portion to form a second accommodating hole, wherein the second accommodating hole exposes a portion of the gate bottom wall; The second semiconductor layer, the second gate insulating layer, and the second gate electrode are formed in the second receiving hole.

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