Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the stacking structure is located on the substrate and comprises a plurality of semiconductor doping layers and a plurality of first isolation structures which are alternately stacked; the word line structure penetrates through the substrate from the stacking structure; the storage structure penetrates through the substrate from the stacking structure and surrounds the word line structure; the channel layer is located between the adjacent semiconductor doping layers, surrounds the storage structure and is surrounded by the first isolation structure; moreover, the first isolation structure comprises a first isolation part and a first conductive part, the first isolation part is located between the channel layer and the first conductive part and is located between the semiconductor doping layer and the first conductive part, and the first conductive part is used for accessing a preset power supply voltage. The embodiment of the invention can effectively improve the performance of the flash memory device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, flash memory devices have emerged. Flash memory devices are a type of non-volatile memory, which means that data will not be lost even if the power is turned off. They have advantages such as high read and write speed and low power consumption. In order to increase device integration density and reduce manufacturing costs, three-dimensional flash memory devices have emerged in related technologies.

[0003] However, the performance of existing flash memory devices still needs to be improved. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a semiconductor structure and a method for preparing the same to improve the performance of a flash memory device.

[0005] A semiconductor structure comprising:

[0006] substrate;

[0007] A stacked structure, located on the substrate, comprising a plurality of semiconductor doping layers and a plurality of first isolation structures alternately stacked;

[0008] A word line structure extending from the stacked structure to the substrate;

[0009] A storage structure, extending from the stacked structure to the substrate and surrounding the word line structure;

[0010] a channel layer, located between adjacent semiconductor doping layers, surrounding the storage structure, and surrounded by the first isolation structure;

[0011] Furthermore, the first isolation structure includes a first isolation portion and a first conductive portion, the first isolation portion is located between the channel layer and the first conductive portion, and between the semiconductor doping layer and the first conductive portion, and the first conductive portion is used to access a preset power supply voltage.

[0012] In one embodiment, the preset power supply voltage includes a ground voltage and / or a negative voltage.

[0013] In one embodiment, a plurality of the stacked structures arranged at intervals are provided on the substrate, and a second isolation structure is provided between adjacent stacked structures, the second isolation structure includes a second isolation portion and a second conductive portion, the second isolation portion is connected to the first isolation portion, the second conductive portion is connected to the first conductive portion, and the second isolation portion and the first isolation portion constitute an isolation dielectric layer, the second conductive portion and the first conductive portion constitute a conductive layer, and the conductive layer is located on a side of the isolation dielectric layer away from the semiconductor doping layer and the channel layer.

[0014] In one embodiment, the semiconductor structure further includes a first passivation layer, a word line interconnection structure and a conductive interconnection structure, wherein the first passivation layer covers the stacking structure, the storage structure, the word line structure and the second conductive portion, the word line interconnection structure penetrates the first passivation layer to electrically connect the word line, and the conductive interconnection structure penetrates the first passivation layer to electrically connect the second conductive portion.

[0015] In one embodiment, the stacked structure has a non-step region and a step region, the step region exposes a portion of the upper surface of each of the semiconductor doping layers to form a step plane, and the word line structure is provided in the non-step region;

[0016] The semiconductor structure further includes a second passivation layer, wherein the second passivation layer covers the stacked structure located in the step region.

[0017] In one embodiment,

[0018] The step region is provided with a dummy word line structure penetrating from the second passivation layer to the substrate and a dummy storage structure surrounding the dummy word line structure.

[0019] In one embodiment, the semiconductor structure further includes a first passivation layer, a bit line lead line and a selection line lead line, the first passivation layer covers the second passivation layer, the bit line lead line and the selection line lead line penetrate the first passivation layer and the second passivation layer, and are alternately distributed on the step planes of each layer.

[0020] A method for preparing a semiconductor structure, comprising:

[0021] Providing a substrate, and forming a stacked layer on the substrate, wherein the stacked layer includes a plurality of semiconductor doping layers and a plurality of semiconductor sacrificial layers formed alternately;

[0022] forming a word line hole in the stacked layer;

[0023] Carving back each layer of the semiconductor sacrificial layer through the word line hole to form a side hole surrounding the word line hole;

[0024] forming a channel layer in the side hole, and sequentially forming a storage structure and a word line structure in the word line hole;

[0025] The semiconductor sacrificial layer is removed, and a first isolation portion is formed on the surface of the channel layer and on the surfaces of the semiconductor doped layer on both sides of the channel layer, and a first conductive portion is formed in the first isolation portion, the first conductive portion is used to connect to a preset power supply voltage, the first isolation portion and the first conductive portion form a first isolation structure, and the first isolation structure and the semiconductor doped layer form a stacked structure.

[0026] In one embodiment, the preset power supply voltage includes a ground voltage and / or a negative voltage.

[0027] In one embodiment, the method further comprises:

[0028] The stacked layer is patterned to form a plurality of isolation trenches arranged at intervals.

[0029] In one embodiment, the removing of the semiconductor sacrificial layer, forming a first isolation portion on the surface of the channel layer and the surfaces of the semiconductor doping layers on both sides of the channel layer, and forming a first conductive portion in the first isolation portion, comprises:

[0030] Etching the semiconductor sacrificial layer remaining after the patterning process through the isolation trench to remove the semiconductor sacrificial layer;

[0031] An isolation dielectric layer is formed on the surface of the channel layer, the surfaces of the semiconductor doping layers on both sides of the channel layer, the sidewalls of the isolation trench and the bottom of the isolation trench, wherein the isolation dielectric layer includes the first isolation portion and the second isolation portion connected to each other, and the second isolation portion is located on the sidewalls and the bottom of the isolation trench;

[0032] A conductive layer is formed on the surface of the isolation dielectric layer, wherein the conductive layer includes the first conductive portion and the second conductive portion connected to each other, and the second conductive portion fills the isolation trench.

[0033] In one embodiment, after forming the conductive layer on the surface of the isolation dielectric layer, the method further comprises:

[0034] forming a first passivation layer covering the stacked layer, the storage structure, the word line structure and the second conductive portion;

[0035] forming a word line interconnection hole exposing the word line structure and a conductive interconnection hole exposing the second conductive portion in the first passivation layer;

[0036] Conductive material is filled in the word line interconnection hole and the conductive interconnection hole to form a word line interconnection structure and a conductive interconnection structure.

[0037] In one embodiment, the semiconductor structure has a non-step region and a step region, and the word line hole is formed in the non-step region.

[0038] Before forming the word line hole in the stacked layer, the method further includes:

[0039] Etching the stacked layers in the step region to form a step, wherein after etching, the step region exposes a portion of the upper surface of each of the remaining semiconductor doping layers to form a step plane;

[0040] A second passivation layer is formed to cover the step located in the step region.

[0041] In one embodiment, while forming the word line hole in the stacked layer in the non-step region, a dummy word line hole penetrating the second passivation layer and the stacked layer is also formed in the step region.

[0042] In one embodiment, after forming a channel layer in the side hole and sequentially forming a storage structure and a word line structure in the word line hole, the method further includes:

[0043] forming a first passivation layer covering the second passivation layer;

[0044] Etching the first passivation layer and the second passivation layer to form bit line contact holes and selection line contact holes which are alternately arranged and extend onto the semiconductor doping layer;

[0045] A bit line lead-out line is formed in the bit line contact hole, and a selection line is formed in the selection line contact hole.

[0046] In the above-mentioned semiconductor structure and its preparation method, the stacked structure includes a plurality of semiconductor doped layers and a plurality of first isolation structures that are alternately stacked. And the first isolation structure includes a first isolation portion and a first conductive portion. Therefore, the source electrodes (or drain electrodes) of adjacent layer storage units can be effectively isolated by the first isolation portion between the two, thereby effectively preventing crosstalk between adjacent storage units. At the same time, the first conductive portion in the first isolation portion can be connected to a preset power supply voltage, thereby improving device performance. For example, when the preset power supply voltage is a ground voltage, the first conductive portion can shield the coupling interference between the semiconductor doped layers, thereby shielding the coupling interference between the bit lines of each storage unit connected to the semiconductor doped layer. For another example, when the preset power supply voltage is a negative voltage, the first conductive portion can attract positively charged carriers, thereby preventing positively charged carriers from entering the unselected word line structure, thereby increasing the difficulty of opening the storage unit corresponding to the unselected word line structure, thereby effectively reducing leakage. Therefore, the embodiment of the present application can effectively improve the performance of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0049] Figures 2 to 11 Schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing a semiconductor structure provided in an embodiment, wherein: Figures 2 to 6 as well as Fig. 9 It is a schematic diagram of the cross-sectional structure taken along the same section line. Figure 7 as well as Figure 8 is a schematic diagram of the cross-sectional structure taken along another cross-sectional line. Fig.11 is a schematic diagram of a cross-sectional structure taken along another cross-sectional line;

[0050] Fig.12 FIG. 1 is a schematic top view of a partial structure of a semiconductor structure provided in an embodiment.

[0051] Description of reference numerals:

[0052] 100-substrate, 201-stacked layer, 210-semiconductor doped layer, 221-semiconductor sacrificial layer, 220a-first isolation portion, 220b-first conductive portion, 220-first isolation structure, 200-stacked structure, 300-channel layer, 410-storage structure, 411-tunneling layer, 412-charge trapping layer, 413-blocking layer, 420-pseudo storage structure, 510-word line structure, 511-high dielectric constant layer, 512-word line, 520-pseudo word line structure, 620a- Second isolation part, 620b second conductive part, 620-second isolation structure, 710-first passivation layer, 720-second passivation layer, 810-word line interconnection structure, 820-conductive interconnection structure, 830-bit line lead line, 840-selection line lead line, 900-metal silicide, 11-word line hole, 12-dummy word line hole, 20-side hole, 30-isolation groove, 40-hollow area, 51-word line interconnection hole, 52-conductive interconnection hole, 53-bit line contact hole, 54-selection line contact hole. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0055] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0056] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] In one embodiment, see Figure 1 , provides a method for preparing a semiconductor structure, which can be used to prepare a flash memory device. The flash memory device may include but is not limited to a NOR device. For example, the flash memory device may also be a NAND device.

[0059] The method comprises the following steps:

[0060] Step S10, see Figure 2 , providing a substrate 100, and forming a stacked layer 201 on the substrate 100, wherein the stacked layer 201 includes a plurality of semiconductor doping layers 210 and a plurality of semiconductor sacrificial layers 221 formed alternately;

[0061] Step S30, see Figure 4 , forming a word line hole 11 in the stack layer 201;

[0062] Step S40, please continue to refer to Figure 4 , etching back each semiconductor sacrificial layer 221 through the word line hole 11 to form a side hole 20 surrounding the word line hole 11;

[0063] Step S50, see Figure 5 as well as Figure 6 , forming a channel layer 300 in the side hole 20, and sequentially forming a storage structure 410 and a word line structure 510 in the word line hole 11;

[0064] Step S70, see Fig. 9 , remove the semiconductor sacrificial layer 221, form a first isolation portion 220a on the surface of the channel layer 300 and on the surfaces of the semiconductor doping layer 210 on both sides of the channel layer 300, and form a first conductive portion 220b in the first isolation portion 220a, the first conductive portion 220b is used to connect to a preset power supply voltage, the first isolation portion 220a and the first conductive portion 220b form a first isolation structure 220, and the first isolation structure 220 and the semiconductor doping layer 210 form a stacked structure 200.

[0065] In step S10, refer to Figure 2The base 100 may include a substrate (not shown). The substrate may be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator substrates.

[0066] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0067] When the stacked layer 201 is formed on the substrate 100 , the semiconductor doped layer 210 and the semiconductor sacrificial layer 221 may be repeatedly and alternately formed on the substrate 100 through a deposition process.

[0068] The deposition process may include but is not limited to one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0069] As an example, a single crystal silicon substrate or a germanium silicon substrate can be used as the substrate 100, and then a doped silicon layer is formed on the substrate 100 by an epitaxial process as the semiconductor doped layer 210, and then a germanium silicon layer is formed on the doped silicon layer by an epitaxial process as the semiconductor sacrificial layer 221. Afterwards, the steps of epitaxially growing the semiconductor sacrificial layer 221 to form the semiconductor doped layer 210 and epitaxially growing the semiconductor sacrificial layer 221 are repeated, thereby forming a stacked layer 201 including alternately stacked semiconductor doped layers 210 and semiconductor sacrificial layers 221.

[0070] As an example, both the top layer and the bottom layer of the stacked layer 201 may be the semiconductor doped layer 210 .

[0071] In step S30, refer to Figure 4, a first patterned photoresist may be first formed on the stacked layer 201. The first patterned photoresist has a first opening. The first opening may define the size and position of the word line hole 11. Then, based on the first patterned photoresist, the stacked layer 201 is dry-etched, etc., to form the word line hole 11. Thereafter, the first patterned photoresist may be removed.

[0072] In step S40, refer to Figure 4 The semiconductor sacrificial layers 221 between the semiconductor doping layers 210 can be etched back from the word line holes 11 by wet etching or the like, thereby forming side holes 20 surrounding the word line holes 11 .

[0073] In step S50, refer to Figure 5 , a channel layer 300 may be first formed in the side hole 20. The material of the channel layer 300 is a semiconductor material, which may be the same as the material of the semiconductor doping layer 210 or may be different.

[0074] As an example, the channel material layer can be formed by epitaxial growth of the semiconductor doping layer 210 (such as a doped silicon layer) and the semiconductor sacrificial layer 221 (such as a germanium silicon layer) at the same time. Then, the channel material layer outside the side hole 20 is removed to form the channel layer 300 .

[0075] At this time, if the semiconductor doping layer 210 and the semiconductor sacrificial layer 221 are formed by epitaxial growth based on a substrate such as single crystal silicon or single crystal silicon germanium, the channel layer 300 is epitaxially grown based on the semiconductor doping layer 210 and the semiconductor sacrificial layer 221, thereby facilitating the formation of a single crystal channel layer 300, thereby effectively improving the performance of the channel layer 300.

[0076] In other embodiments, the channel material layer may also be formed by chemical vapor deposition or atomic layer deposition, etc. Then, the channel material layer outside the side hole 20 is removed to form the channel layer 300 .

[0077] See also Figure 6 After forming the channel layer 300 in the side hole 20, the storage structure 410 and the gate word line structure 510 are formed in sequence.

[0078] When the channel layer 300 fills the side hole 20, the memory structure 410 and the word line structure 510 may be formed only in the word line hole 11. When the channel layer 300 does not fill the side hole 20, the memory structure 410 and the word line structure 510 may be formed in the word line hole 11 and extend into the side hole 20.

[0079] The storage structure 410 is located between the word line structure 510 and the channel layer 300, so that charge storage can be performed. The storage structure 410 includes a tunneling layer 411, a charge trapping layer 412, and a blocking layer 413 arranged in sequence from the channel layer 300 to the word line structure 510. The word line structure 510 may include a high dielectric constant layer 511 and a word line 512 arranged in sequence on the surface of the storage structure 410.

[0080] The material of the tunneling layer 411 may include but is not limited to oxide, the material of the charge trapping layer 412 may include but is not limited to nitride, the material of the blocking layer 413 may include but is not limited to oxide, the material of the high dielectric constant layer 511 may include but is not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3), etc. The material of the word line 512 may include but is not limited to cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al), etc.

[0081] The channel layer 300 can form a memory cell with the memory structure 410 and the word line structure 510 that are opposite thereto. At the same time, the semiconductor doping layers 210 on both sides of the channel layer 300 are connected to the channel layer 300, thereby forming the source and drain of the memory cell respectively. At this time, the adjacent memory cells in the stacking direction can share a source or a drain.

[0082] In step S70, refer to Fig. 9 , the semiconductor sacrificial layer 221 can be firstly removed by a wet etching process. Then the first isolation part 220a and the first conductive part 220b are sequentially formed. The first isolation part 220a and the first conductive part 220b can form a first isolation structure 220. The first isolation structure 220 and the semiconductor doping layer 210 are alternately stacked to form a stacked structure 200.

[0083] The first conductive portion 220b is used to access a preset power supply voltage. As an example, the preset power supply voltage includes a ground voltage and / or a negative voltage. The negative voltage may be, for example, -VCC. VCC may be a voltage for normal operation of the device, and its voltage value may be, for example, 1.2V, 2.5V, etc.

[0084] In this embodiment, the sources (or drains) of adjacent layers of memory cells can be effectively isolated by the first isolation portion 220a therebetween, thereby effectively preventing crosstalk between adjacent memory cells.

[0085] At the same time, the first conductive part 220b in the first isolation part 220a can be connected to a preset power supply voltage, thereby improving device performance. For example, when the preset power supply voltage is a ground voltage, the first conductive part 220b can shield the coupling interference between the semiconductor doping layers 210, thereby shielding the coupling interference between the bit lines of each storage unit connected to the semiconductor doping layer 210. For another example, when the preset power supply voltage is a negative voltage, the first conductive part 220b can attract positively charged carriers, thereby preventing positively charged carriers from entering the unselected word line structure 510, thereby increasing the difficulty of opening the storage unit corresponding to the unselected word line structure 510, thereby effectively reducing leakage.

[0086] In one embodiment, see Figure 7 , the method for preparing the semiconductor structure further comprises:

[0087] Step S60 , patterning the stacked layer 201 to form a plurality of isolation trenches 30 arranged at intervals.

[0088] The isolation trenches 30 may separate the plurality of stacked layers 201 into a plurality of mutually spaced portions, so that a plurality of mutually spaced stacked structures 200 may be formed after step S70 .

[0089] In one embodiment, step S60 may be performed before step S70. In this case, step S60 may include:

[0090] Step S61, see Figure 7 , etching the semiconductor sacrificial layer 221 remaining after the patterning process through the isolation trench 30 to remove the semiconductor sacrificial layer 221;

[0091] Step S62, see Figure 8 , forming an isolation dielectric layer on the surface of the channel layer 300, the surfaces of the semiconductor doping layer 210 on both sides of the channel layer 300, the sidewalls of the isolation trench 30 and the bottom of the isolation trench 30, wherein the isolation dielectric layer includes a first isolation portion 220a and a second isolation portion 620a connected to each other, and the second isolation portion 620a is located on the sidewalls and the bottom of the isolation trench 30;

[0092] Step S63, see Figure 8 A conductive layer is formed on the surface of the isolation dielectric layer. The conductive layer includes a first conductive portion 220 and a second conductive portion 620b connected to each other. The second conductive portion 620b fills the isolation trench.

[0093] In step S61, refer to Figure 7 , the wet etching solution can flow to the semiconductor sacrificial layer 221 through the isolation trench 30, thereby removing it.

[0094] In step S62, refer to Figure 8 , an isolation dielectric material layer can be formed on the surface of the structure obtained after removing the semiconductor sacrificial layer 221 through a deposition process. Then, the isolation dielectric material layer on the upper surface of the semiconductor doping layer 210 at the top layer can be removed through a dry etching process, etc. The retained isolation dielectric material layer forms an isolation dielectric layer.

[0095] The isolation dielectric layer includes a first isolation portion 220 a and a second isolation portion 620 a connected to each other. The second isolation portion 620 a is located on the sidewall and bottom of the isolation trench 30 .

[0096] It can be understood that after removing the semiconductor sacrificial layer 221, a hollow region 40 is formed between the semiconductor doping layers 210. At this time, the isolation trench 30 is connected to the hollow region 40, and the sidewall of the isolation trench 30 is disconnected by the hollow region 40. The second isolation portion 620a is located at the disconnected sidewall of the isolation trench 30 and the bottom of the isolation trench 30.

[0097] The material of the isolation dielectric layer may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON).

[0098] In step S63, refer to Figure 8 , a conductive material layer may be formed on the surface of the structure obtained after forming the isolation dielectric layer. The conductive material layer fills and exceeds the isolation trench 30. Then, the conductive material layer outside the isolation trench 30 may be removed by a chemical mechanical polishing (CMP) process, thereby forming a conductive layer.

[0099] The material of the conductive layer may include, but is not limited to, tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), and the like.

[0100] The conductive layer includes a first conductive portion 220 and a second conductive portion 620 b connected to each other. The second conductive portion 620 b and the second isolation portion 620 a can form a second isolation structure 620 .

[0101] Meanwhile, the second conductive portion 620 b fills the isolation trench 30 , and its upper surface may be exposed, so that the first conductive portion 220 may be connected to the preset power supply voltage by applying the preset power supply voltage to the second conductive portion 620 b .

[0102] As an example, see Fig.10 , after step S63, further comprising:

[0103] Step S641, forming a first passivation layer 710 covering the stacked layer 201, the memory structure 410, the word line structure 510 and the second conductive portion 620b;

[0104] Step S651, forming a word line interconnection hole exposing the word line structure 510 and a conductive interconnection hole exposing the second conductive portion 620b in the first passivation layer 710;

[0105] In step S661 , a conductive material is filled into the word line interconnection hole and the conductive interconnection hole to form a word line interconnection structure 810 and a conductive interconnection structure 820 .

[0106] The material of the first passivation layer 710 may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc. The material of the word line interconnect structure 810 and the conductive interconnect structure 820 may include but is not limited to tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) or aluminum (Al), etc.

[0107] The conductive interconnect structure 820 can supply power to the second conductive portion 620 b . Meanwhile, the word line interconnect hole can expose the word line 512 of the word line structure 510 , so that the word line interconnect structure 810 can supply power to the word line 512 .

[0108] Of course, in other embodiments, step S60 may also be performed after step S70. In this case, before performing step S70, an etching opening may be formed at a preset position, so that the semiconductor sacrificial layer is released by etching the opening. In this case, after the isolation trench 30 is formed, a second isolation structure 620 of an insulating material may be filled in the isolation trench 30.

[0109] In one embodiment, the semiconductor structure has a non-step region and a step region, and the word line hole is formed in the non-step region.

[0110] Before step S30, the method further includes:

[0111] Step S21, see Figure 3 , etching the stacked layer 201 in the step region to form a step, after etching, the step region exposes a portion of the upper surface of each remaining semiconductor doping layer 210 to form a step plane;

[0112] Step S22, see Figure 4 , forming a second passivation layer 720 covering the steps located in the step area.

[0113] In step S21 , the semiconductor doping layer 210 and the semiconductor sacrificial layer 221 located in the step region may be etched sequentially from top to bottom by a photolithography process, thereby forming a plurality of steps.

[0114] Each time a step is formed, a second patterned photoresist may be formed first; then, the semiconductor doping layer 210 is etched based on the second patterned photoresist. Afterwards, the semiconductor sacrificial layer 221 is etched based on the second patterned photoresist and the etched semiconductor doping layer 210, thereby forming a step. Then, the second patterned photoresist is removed.

[0115] When the bottom layer of the stacked layer is the semiconductor doping layer 210 , when the last step is formed, the bottommost step can be formed after the semiconductor doping layer 210 is etched.

[0116] It is understandable that, in the process of forming each step, when forming a step located at a non-top layer, the formed second patterned photoresist can cover the non-step area and the previously formed upper step, thereby protecting the upper step.

[0117] In step S22 , the upper surface of the second passivation layer 720 may be flush with the upper surface of the stacked layer 201 located in the non-step region.

[0118] The material of the second passivation layer 720 may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc. The material of the second passivation layer 720 may be the same as or different from the material of the first passivation layer 710.

[0119] At this time, the semiconductor doping layer 210 at each step plane of the step region can be effectively passivated by the second passivation layer 720 .

[0120] In one embodiment, in step 30, refer to Figure 5 While the word line hole 11 is formed in the stacked layer 201 in the non-step region, a dummy word line hole 12 penetrating the second passivation layer 720 and the stacked layer 201 is also formed in the step region.

[0121] Afterwards, see Figure 6 The pseudo word line hole 12 and the word line hole 11 undergo the same process steps, so that while the word line structure 510 is formed in the word line hole 11, a pseudo word line structure 520 and a pseudo storage structure 420 are formed in the pseudo word line hole 12. The pseudo word line structure 520 may have the same structural composition as the word line structure 510. The pseudo storage structure 420 may have the same structural composition as the storage structure 410.

[0122] In one embodiment, see Fig.11 , after step S50, further comprising:

[0123] Step S642, forming a first passivation layer 710 covering the second passivation layer 720;

[0124] Step S652, etching the first passivation layer 710 and the second passivation layer 720 to form bit line contact holes and select line contact holes that are alternately arranged and extend onto the semiconductor doping layer 210;

[0125] In step S662, a bit line lead-out line 830 is formed in the bit line contact hole, and a select line lead-out line 840 is formed in the select line contact hole.

[0126] As an example, step S642 may be performed simultaneously with step S641 in the above-mentioned embodiment. At this time, the first passivation layer 710 may be formed by a deposition process.

[0127] Step S652 can be performed simultaneously with step S651 in the aforementioned embodiment. At this time, a third patterned photoresist can be formed on the surface of the first passivation layer 710. The third patterned photoresist has a third opening. The third opening defines the position of the bit line contact hole, the select line contact hole, the word line interconnection hole, and the conductive interconnection hole. Then, based on the third patterned photoresist, the first passivation layer 710 is etched to form the bit line contact hole, the select line contact hole, the word line interconnection hole, and the conductive interconnection hole.

[0128] Step S662 can be performed simultaneously with step S661 in the above-mentioned embodiment. At this time, a conductive material layer can be formed on the upper surface of the bit line contact hole, the select line contact hole, the word line interconnection hole, the conductive interconnection hole and the first passivation layer 710 by processes such as magnetron sputtering, electroplating or chemical vapor deposition. Then, the conductive material layer located on the upper surface of the first passivation layer 710 can be removed by chemical mechanical polishing (CMP) and the like. The remaining conductive material layer located in the bit line contact hole forms the bit line lead 830, the conductive material layer located in the select line contact hole forms the select line lead 840, the conductive material layer located in the word line interconnection hole forms the word line interconnection structure 810, and the conductive material layer located in the conductive interconnection hole forms the conductive interconnection structure 820.

[0129] As an example, a metal silicide 900 may be formed on the surface of the semiconductor doped layer 210 located at the step plane. The bit line contact hole and the select line contact hole may extend to the surface of the metal silicide 900. At this time, the bit line lead 830 and the select line lead 840 may be connected to the semiconductor doped layer 210 through the metal silicide 900.

[0130] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0131] In one embodiment, see Fig.10 , Fig.11 as well as Fig.12 , a semiconductor structure is also provided, which includes a substrate 100, a stacked structure 200, a word line structure 510, a storage structure 410 and a channel layer 300.

[0132] The base 100 may include a substrate (not shown). The substrate may be made of a semiconductor material, an insulating material, a conductor material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include a substrate such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0133] Meanwhile, the substrate 100 may be a single-layer structure or a multi-layer structure. When the substrate 100 comprises a multi-layer structure, it may include a substrate and other structures or film layers formed on the substrate.

[0134] The stack structure 200 is located on the substrate 100. The stack structure 200 includes a plurality of semiconductor doping layers 210 and a plurality of first isolation structures 220 that are alternately stacked.

[0135] When the base 100 is a semiconductor substrate, the semiconductor doping layer 210 may have the same or similar lattice structure as the semiconductor substrate. For example, when the base 100 is a single crystal silicon substrate or a silicon germanium substrate, the semiconductor doping layer 210 may be a doped silicon layer or a doped silicon germanium layer.

[0136] The word line structure 510 and the memory structure 410 are both formed by the stacked structure 200 and penetrate the substrate 100 . The memory structure 410 surrounds the word line structure 510 . The channel layer 300 is located between adjacent semiconductor doping layers 210 , surrounds the memory structure 410 , and is surrounded by the first isolation structure 220 .

[0137] The storage structure 410 is located between the word line structure 510 and the channel layer 300, so that charge storage can be performed. The storage structure 410 includes a tunneling layer 411, a charge trapping layer 412, and a blocking layer 413 arranged in sequence from the channel layer 300 to the word line structure 510. The word line structure 510 may include a high dielectric constant layer 511 and a word line 512 arranged in sequence on the surface of the storage structure 410.

[0138] The material of the tunneling layer 411 may include but is not limited to oxide, the material of the charge trapping layer 412 may include but is not limited to nitride, the material of the blocking layer 413 may include but is not limited to oxide, the material of the high dielectric constant layer 511 may include but is not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3), etc. The material of the word line 512 may include but is not limited to cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) and aluminum (Al), etc.

[0139] When the base 100 is a semiconductor substrate, the channel layer 300 may have the same or similar lattice structure as the semiconductor substrate.

[0140] The channel layer 300 can form a memory cell with the memory structure 410 and the word line structure 510 that are opposite thereto. At the same time, the semiconductor doping layers 210 on both sides of the channel layer 300 are connected to the channel layer 300, thereby forming the source and drain of the memory cell respectively. At this time, the adjacent memory cells in the stacking direction can share a source or a drain.

[0141] Meanwhile, the first isolation structure 220 includes a first isolation portion 220 a and a first conductive portion 220 b .

[0142] The first isolation portion 220a is located between the channel layer 300 and the first conductive portion 220b, and between the semiconductor doped layer 220a and the first conductive portion 220b, and the first conductive portion 220b is used to access a preset power supply voltage.

[0143] As an example, the preset power supply voltage includes a ground voltage and / or a negative voltage. The negative voltage may be, for example, -VCC. VCC may be a voltage for a device to work normally, and its voltage value may be, for example, 1.2V, 2.5V, etc.

[0144] In this embodiment, the sources (or drains) of adjacent layers of memory cells can be effectively isolated by the first isolation portion 220a therebetween, thereby effectively preventing crosstalk between adjacent memory cells.

[0145] At the same time, the first conductive part 220b in the first isolation part 220a can be connected to a preset power supply voltage, thereby improving device performance. For example, when the preset power supply voltage is a ground voltage, the first conductive part 220b can shield the coupling interference between the semiconductor doping layers 210, thereby shielding the coupling interference between the bit lines of each storage unit connected to the semiconductor doping layer 210. For another example, when the preset power supply voltage is a negative voltage, the first conductive part 220b can attract positively charged carriers, thereby preventing positively charged carriers from entering the unselected word line structure 510, thereby increasing the difficulty of opening the storage unit corresponding to the unselected word line structure 510, thereby effectively reducing leakage.

[0146] In one embodiment, a plurality of stacked structures 200 are arranged at intervals on the substrate 100, and a second isolation structure 620 is disposed between adjacent stacked structures 200. The second isolation structure 620 includes a second isolation portion 620a and a second conductive portion 620b.

[0147] The second isolation part 620a is connected to the first isolation part 220a, and the second conductive part 620b is connected to the first conductive part 220b. The second isolation part 620a and the first isolation part 220a form an isolation dielectric layer, and the second conductive part 620b and the first conductive part 220b form a conductive layer.

[0148] The material of the isolation dielectric layer may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc. The material of the conductive layer may include but is not limited to tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) or aluminum (Al), etc.

[0149] The conductive layer is located on a side of the isolation dielectric layer away from the semiconductor doping layer 210 and the channel layer 300 , thereby effectively isolating the conductive layer from the memory cell.

[0150] In one embodiment, the semiconductor structure further includes a first passivation layer 710 , a word line interconnect structure 810 , and a conductive interconnect structure 820 .

[0151] The first passivation layer 710 covers the stacked structure 200, the memory structure 410, the word line structure 510 and the second conductive portion 620b. The word line interconnection structure 810 penetrates the first passivation layer 710 to electrically connect the word lines, and the conductive interconnection structure 820 penetrates the first passivation layer 710 to electrically connect the second conductive portion 620b.

[0152] The material of the first passivation layer 710 may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc. The material of the word line interconnect structure 810 and the conductive interconnect structure 820 may be the same, and the materials of the two may include but are not limited to tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu) or aluminum (Al), etc.

[0153] The second conductive portion 620 b may be powered. Meanwhile, the word line interconnect structure 810 may be powered for the word line 512 .

[0154] At this time, a preset power supply voltage may be applied to the second conductive portion 620 b through the conductive interconnect structure 820 , thereby connecting the first conductive portion 220 to the preset power supply voltage.

[0155] In one embodiment, the stacked structure 200 has a non-step region and a step region. The step region exposes a portion of the upper surface of each semiconductor doping layer to form a step plane. The word line structure 510 is disposed in the non-step region.

[0156] The semiconductor structure further includes a second passivation layer 710. The second passivation layer 720 covers the stacked structure 200 in the step region, thereby effectively passivating the semiconductor doped layer 210 at each step plane in the step region. The upper surface of the second passivation layer 720 may be flush with the upper surface of the stacked structure 200 in the non-step region.

[0157] The material of the second passivation layer 720 may include but is not limited to silicon oxide (SiO2), silicon nitride (Si3N4) or silicon oxynitride (SiON), etc. The material of the second passivation layer 720 may be the same as or different from the material of the first passivation layer 710.

[0158] In one embodiment, the step region is provided with a dummy word line structure 520 extending from the second passivation layer 720 to the substrate 100 and a dummy storage structure 420 surrounding the dummy word line structure 520. The dummy word line structure 520 may have the same structural composition as the word line structure 510. The dummy storage structure 420 may have the same structural composition as the storage structure 410.

[0159] In one embodiment, the semiconductor structure further includes a first passivation layer 710 , a bit line lead 830 , and a select line lead 840 .

[0160] The first passivation layer 710 covers the second passivation layer 720. As an example, the first passivation layer 710 may cover the stacked structure 200, the memory structure 410, the word line structure 510, the second conductive portion 620b, the first passivation layer 710, the dummy word line structure 520, and the dummy memory structure 420.

[0161] The bit line lead lines 830 and the select line lead lines 840 penetrate the first passivation layer 710 and the second passivation layer 720 and are alternately distributed on each step plane. The bit line lead lines 830 and the select line lead lines 840 can respectively connect the bit lines (not shown) and the select lines (not shown) of the wiring layer.

[0162] As an example, the materials of the bit line lead-out line 830 , the select line lead-out line 840 , the word line interconnect structure 810 , and the conductive interconnect structure 820 may be the same.

[0163] As an example, the semiconductor structure may further include metal silicide 900 on the surface of semiconductor doping layer 210 at the step plane. Bit line lead 830 and select line lead 840 may be connected to semiconductor doping layer 210 through metal silicide 900, thereby reducing contact resistance between the two and semiconductor doping layer 210.

[0164] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A stacked structure, located on the substrate, comprising a plurality of semiconductor doping layers and a plurality of first isolation structures alternately stacked; A word line structure extending from the stacked structure to the substrate; A storage structure, extending from the stacked structure to the substrate and surrounding the word line structure; a channel layer, located between adjacent semiconductor doping layers, surrounding the storage structure, and surrounded by the first isolation structure; Furthermore, the first isolation structure includes a first isolation portion and a first conductive portion, the first isolation portion is located between the channel layer and the first conductive portion, and between the semiconductor doping layer and the first conductive portion, and the first conductive portion is used to access a preset power supply voltage.

2. The semiconductor structure according to claim 1, characterized in that: The preset power supply voltage includes a ground voltage and / or a negative voltage.

3. The semiconductor structure according to claim 1, characterized in that: The substrate is provided with a plurality of stacked structures arranged at intervals, and a second isolation structure is provided between adjacent stacked structures, wherein the second isolation structure includes a second isolation portion and a second conductive portion, wherein the second isolation portion is connected to the first isolation portion, and the second conductive portion is connected to the first conductive portion. ， The second isolation part and the first isolation part constitute an isolation dielectric layer, the second conductive part and the first conductive part constitute a conductive layer, and the conductive layer is located on a side of the isolation dielectric layer away from the semiconductor doping layer and the channel layer.

4. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure also includes a first passivation layer, a word line interconnection structure and a conductive interconnection structure, the first passivation layer covers the stacking structure, the storage structure, the word line structure and the second conductive portion, the word line interconnection structure penetrates the first passivation layer to electrically connect the word line, and the conductive interconnection structure penetrates the first passivation layer to electrically connect the second conductive portion.

5. The semiconductor structure according to claim 1, characterized in that The stacked structure has a non-step region and a step region, the step region exposes a portion of the upper surface of each semiconductor doping layer to form a step plane, and the word line structure is arranged in the non-step region; The semiconductor structure further includes a second passivation layer, wherein the second passivation layer covers the stacked structure located in the step region.

6. The semiconductor structure according to claim 5, characterized in that: The step region is provided with a dummy word line structure penetrating from the second passivation layer to the substrate and a dummy storage structure surrounding the dummy word line structure.

7. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure also includes a first passivation layer, a bit line lead and a selection line lead. The first passivation layer covers the second passivation layer. The bit line lead and the selection line lead penetrate the first passivation layer and the second passivation layer and are alternately distributed on the step planes of each layer.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming a stacked layer on the substrate, wherein the stacked layer includes a plurality of semiconductor doping layers and a plurality of semiconductor sacrificial layers formed alternately; forming a word line hole in the stacked layer; Carving back each layer of the semiconductor sacrificial layer through the word line hole to form a side hole surrounding the word line hole; forming a channel layer in the side hole, and sequentially forming a storage structure and a word line structure in the word line hole; The semiconductor sacrificial layer is removed, and a first isolation portion is formed on the surface of the channel layer and on the surfaces of the semiconductor doped layer on both sides of the channel layer, and a first conductive portion is formed in the first isolation portion, the first conductive portion is used to connect to a preset power supply voltage, the first isolation portion and the first conductive portion form a first isolation structure, and the first isolation structure and the semiconductor doped layer form a stacked structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The preset power supply voltage includes a ground voltage and / or a negative voltage.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: The method further comprises: The stacked layer is patterned to form a plurality of isolation trenches arranged at intervals.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The step of removing the semiconductor sacrificial layer, forming a first isolation portion on the surface of the channel layer and the surfaces of the semiconductor doping layers on both sides of the channel layer, and forming a first conductive portion in the first isolation portion comprises: Etching the semiconductor sacrificial layer remaining after the patterning process through the isolation trench to remove the semiconductor sacrificial layer; An isolation dielectric layer is formed on the surface of the channel layer, the surfaces of the semiconductor doping layers on both sides of the channel layer, the sidewalls of the isolation trench and the bottom of the isolation trench, wherein the isolation dielectric layer includes the first isolation portion and the second isolation portion connected to each other, and the second isolation portion is located on the sidewalls and the bottom of the isolation trench; A conductive layer is formed on the surface of the isolation dielectric layer, wherein the conductive layer includes the first conductive portion and the second conductive portion connected to each other, and the second conductive portion fills the isolation trench.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: After forming the conductive layer on the surface of the isolation dielectric layer, the method further comprises: forming a first passivation layer covering the stacked layer, the storage structure, the word line structure and the second conductive portion; forming a word line interconnection hole exposing the word line structure and a conductive interconnection hole exposing the second conductive portion in the first passivation layer; Conductive material is filled in the word line interconnection hole and the conductive interconnection hole to form a word line interconnection structure and a conductive interconnection structure.

13. The method for preparing a semiconductor structure according to claim 8, characterized in that: The semiconductor structure has a non-step region and a step region, and the word line hole is formed in the non-step region. Before forming the word line hole in the stacked layer, the method further includes: Etching the stacked layers in the step region to form a step, wherein after etching, the step region exposes a portion of the upper surface of each of the remaining semiconductor doping layers to form a step plane; A second passivation layer is formed to cover the step located in the step region.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: While forming a word line hole in the stacked layer in the non-step region, a dummy word line hole penetrating the second passivation layer and the stacked layer is also formed in the step region.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that: After forming a channel layer in the side hole and sequentially forming a storage structure and a word line structure in the word line hole, the method further includes: forming a first passivation layer covering the second passivation layer; Etching the first passivation layer and the second passivation layer to form bit line contact holes and selection line contact holes which are alternately arranged and extend onto the semiconductor doping layer; A bit line lead-out line is formed in the bit line contact hole, and a selection line is formed in the selection line contact hole.

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