A thin-film resistive sputtering process with PN junction structure

Abstract

This invention proposes a thin-film resistor sputtering process with a PN junction structure, comprising the following steps: (1) sequentially depositing a Cap layer and an etching layer on a substrate, wherein the etching layer comprises, from bottom to top, a first InGaP layer, a first GaAs layer, a second InGaP layer, and a second GaAs layer stacked sequentially; (2) vapor-depositing to form a P-contact layer; (3) etching to form a first upper convex island and a second upper convex island; (4) etching to form a first lower island seat and a second lower island seat; (5) vapor-depositing to form an N-contact layer; (6) etching to form a sputtering cavity; and (7) thin-film resistor sputtering. This invention effectively solves the problem of edge lifting during thin-film resistor sputtering with a PN junction structure, improves appearance yield, and avoids the subsequent lead metal connection through the convex point position, which can easily cause device failure; furthermore, the process of this invention can utilize existing structures, without adding an additional photomask, and without increasing costs.

Description

Technical Field

[0001] This invention relates to the field of thin film resistive sputtering technology, and particularly to a thin film resistive sputtering process with a PN junction structure. Background Technology

[0002] Existing thin-film resistor sputtering processes, such as Figure 1 Specifically, the process involves photoresist coating, alignment, IR reversal, full exposure, development to form a trapezoidal morphology, and then thin-film resistor sputtering. During thin-film resistor sputtering, the bottom corners of this morphology connect with the bottom sputtered metal. Therefore, when the metal is lifted, the metal at the bottom edge is torn off, causing the sputtered metal edge to lift and affecting the appearance yield. In addition to the above problems, the thin-film resistor sputtering process with a PN junction structure also suffers from process complexity and low production efficiency. Summary of the Invention

[0003] To address the aforementioned problems, this invention proposes a thin-film resistive sputtering process with a PN junction structure.

[0004] The technical solution of this invention is implemented as follows:

[0005] A thin-film resistor sputtering process with a PN junction structure includes the following steps:

[0006] (1) A Cap layer and an etch layer are sequentially disposed on the substrate. The etch layer includes, from bottom to top, a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked sequentially.

[0007] (2) Coat the first photoresist on the second GaAs layer, expose and develop the first photoresist in the P-polar region of the PN junction to expose the second GaAs layer and form the P-polar window of the PN junction. Then perform the first metal evaporation to form a P-contact layer on the second GaAs layer at the bottom of the P-polar window. The thickness of the P-contact layer is less than the thickness of the first photoresist. Remove the excess metal from the first metal evaporation on the first photoresist and then remove the first photoresist.

[0008] (3) The second photoresist is coated on the P-contact layer of the second GaAs layer and its surrounding area, and the thin film resistor process area. The second GaAs layer and the second InGaP layer outside the second photoresist area are etched in sequence. Then the second photoresist is removed. The remaining second GaAs layer and the second InGaP layer at the bottom of the P-contact layer form the first upper convex island. The remaining second GaAs layer and the second InGaP layer in the thin film resistor process area form the second upper convex island.

[0009] (4) A third photoresist is applied to the first and second convex islands and their surrounding areas respectively. The first GaAs layer and the first InGaP layer outside the third photoresist are etched in sequence. Then the third photoresist is removed. The first GaAs layer and the first InGaP layer at the bottom of the first convex island form the first lower island base. The first GaAs layer and the first InGaP layer at the bottom of the second convex island form the second lower island base. The width of the first lower island base is greater than that of the first convex island.

[0010] (5) Coat the fourth photoresist on the Cap layer. The fourth photoresist covers all components on the Cap layer. Expose and develop the fourth photoresist to form an N-pole window that leads to the PN junction on the upper surface of the first lower island seat. Then perform a second metal evaporation to form an N-contact layer on the Cap layer at the bottom of the N-pole window. The thickness of the N-contact layer is less than the thickness of the fourth photoresist. Remove the excess metal from the second metal evaporation on the fourth photoresist and then remove the fourth photoresist.

[0011] (6) A fifth photoresist is coated on the Cap layer, covering all components on the Cap layer. The fifth photoresist is exposed and developed to form a sputtering window on the fifth photoresist that leads to the upper surface of the second upper convex island. The second convex island and the second lower island seat are etched through the sputtering window to etch away all the second convex island and the second lower island seat to form a sputtering cavity.

[0012] (7) Perform thin film resistance sputtering to form a thin film resistance layer at the bottom of the sputtering cavity. The thickness of the thin film resistance layer is less than the thickness of the sputtering cavity. Remove the sputtering residue on the fifth photoresist and finally remove the fifth photoresist.

[0013] Preferably, the P-pole window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom, the N-pole window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom, and the sputtering window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom.

[0014] Preferably, the width of the second lower island is equal to or greater than that of the second upper convex island.

[0015] Preferably, the width of the sputtering window is smaller than that of the second upper convex island.

[0016] Preferably, the first photoresist is a positive or negative photoresist, the second photoresist is a positive or negative photoresist, the third photoresist is a positive or negative photoresist, the fourth photoresist is a positive or negative photoresist, and the fifth photoresist is a positive or negative photoresist.

[0017] Preferably, the substrate is a single-crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate, or a silicon carbide substrate.

[0018] Preferably, the thin-film resistor is made of TaN.

[0019] The beneficial effects of this invention are as follows: The process of this invention effectively solves the problem of edge lifting during sputtering of thin film resistors with PN junction structures, improving the appearance yield and preventing subsequent lead metal connections from passing through the bump positions, which can easily cause device failure; furthermore, the process of this invention can utilize existing structures without adding additional photomasks, thus not increasing production costs; after evaporation, the P-contact layer and N-contact layer of the PN junction will not exhibit edge lifting during the removal of excess evaporated material and photoresist, further improving the appearance yield. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a process diagram of an existing metal sputtering process;

[0022] Figure 2 This is a structural diagram of step (1) of the present invention;

[0023] Figure 3 This is a process flow diagram of step (2) of the present invention;

[0024] Figure 4 This is a process flow diagram of step (3) of the present invention;

[0025] Figure 5 This is a process flow diagram of step (4) of the present invention;

[0026] Figure 6 This is a process flow diagram of step (5) of the present invention;

[0027] Figure 7 This is a process flow diagram of step (6) of the present invention;

[0028] Figure 8 This is a process flow diagram of step (7) of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The English terms mentioned in the text are explained as follows: P-contact is also called P-type contact layer or P electrode; N-contact is also called N-type contact layer or N electrode.

[0031] Reference Figure 2-8 A thin-film resistor sputtering process with a PN junction structure includes the following steps:

[0032] (1) A Cap layer and an etch layer are sequentially disposed on the substrate. The etch layer includes, from bottom to top, a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked sequentially.

[0033] (2) Coat the first photoresist on the second GaAs layer, expose and develop the first photoresist in the P-polar region of the PN junction to expose the second GaAs layer and form the P-polar window of the PN junction. Then perform the first metal evaporation to form a P-contact layer on the second GaAs layer at the bottom of the P-polar window. The thickness of the P-contact layer is less than the thickness of the first photoresist. Remove the excess metal from the first metal evaporation on the first photoresist and then remove the first photoresist.

[0034] (3) The second photoresist is coated on the P-contact layer of the second GaAs layer and its surrounding area, and the thin film resistor process area. The second GaAs layer and the second InGaP layer outside the second photoresist area are etched in sequence. Then the second photoresist is removed. The remaining second GaAs layer and the second InGaP layer at the bottom of the P-contact layer form the first upper convex island. The remaining second GaAs layer and the second InGaP layer in the thin film resistor process area form the second upper convex island.

[0035] (4) A third photoresist is applied to the first and second convex islands and their surrounding areas respectively. The first GaAs layer and the first InGaP layer outside the third photoresist are etched in sequence. Then the third photoresist is removed. The first GaAs layer and the first InGaP layer at the bottom of the first convex island form the first lower island base. The first GaAs layer and the first InGaP layer at the bottom of the second convex island form the second lower island base. The width of the first lower island base is greater than that of the first convex island.

[0036] (5) Coat the fourth photoresist on the Cap layer. The fourth photoresist covers all components on the Cap layer. Expose and develop the fourth photoresist to form an N-pole window that leads to the PN junction on the upper surface of the first lower island seat. Then perform a second metal evaporation to form an N-contact layer on the Cap layer at the bottom of the N-pole window. The thickness of the N-contact layer is less than the thickness of the fourth photoresist. Remove the excess metal from the second metal evaporation on the fourth photoresist and then remove the fourth photoresist.

[0037] (6) A fifth photoresist is coated on the Cap layer, covering all components on the Cap layer. The fifth photoresist is exposed and developed to form a sputtering window on the fifth photoresist that leads to the upper surface of the second upper convex island. The second convex island and the second lower island seat are etched through the sputtering window to etch away all the second convex island and the second lower island seat to form a sputtering cavity.

[0038] (7) Perform thin film resistance sputtering to form a thin film resistance layer at the bottom of the sputtering cavity. The thickness of the thin film resistance layer is less than the thickness of the sputtering cavity. Remove the sputtering residue on the fifth photoresist and finally remove the fifth photoresist.

[0039] In a preferred embodiment, the P-pole window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom, the N-pole window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom, and the sputtering window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom.

[0040] In a preferred embodiment, the width of the second lower island is equal to or greater than that of the second upper convex island.

[0041] In a preferred embodiment, the width of the sputtering window is smaller than that of the second upper convex island.

[0042] In a preferred embodiment, the first photoresist is a positive or negative photoresist, the second photoresist is a positive or negative photoresist, the third photoresist is a positive or negative photoresist, the fourth photoresist is a positive or negative photoresist, and the fifth photoresist is a positive or negative photoresist.

[0043] The substrate is a single-crystal silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, an indium phosphide substrate, or a silicon carbide substrate.

[0044] The thin-film resistor is made of TaN. The materials used for the P-contact layer and N-contact layer are existing technologies, therefore the materials used for vapor deposition are also existing technologies and will not be specifically described.

[0045] The process of this invention effectively solves the problem of edge lifting during sputtering of thin film resistors with PN junction structures, improving appearance yield and preventing subsequent lead metal connections that could easily cause device failure. Furthermore, the process of this invention can utilize existing structures without adding additional photomasks, thus not increasing production costs. After evaporation, the P-contact and N-contact layers of the PN junction will not exhibit edge lifting during the removal of excess evaporated material and photoresist, further improving appearance yield.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A thin-film resistive sputtering process with a PN junction structure, characterized in that: Includes the following steps: (1) A Cap layer and an etch layer are sequentially disposed on the substrate. The etch layer includes, from bottom to top, a first InGaP layer, a first GaAs layer, a second InGaP layer and a second GaAs layer stacked sequentially. (2) Coating the first photoresist on the second GaAs layer, exposing and developing the first photoresist in the P-polar region of the PN junction to expose the second GaAs layer and form the P-polar window of the PN junction. Then, performing the first metal evaporation, forming a P-contact layer on the second GaAs layer at the bottom of the P-polar window. The thickness of the P-contact layer is less than the thickness of the first photoresist. Removing the excess metal from the first metal evaporation on the first photoresist, and then removing the first photoresist. (3) The second photoresist is coated on the P-contact layer of the second GaAs layer and its surrounding area, and the thin film resistor process area. The second GaAs layer and the second InGaP layer outside the second photoresist area are etched in sequence. Then the second photoresist is removed. The remaining second GaAs layer and the second InGaP layer at the bottom of the P-contact layer form the first upper convex island. The remaining second GaAs layer and the second InGaP layer in the thin film resistor process area form the second upper convex island. (4) Coat the first upper convex island and the second upper convex island and their surrounding areas with the third photoresist respectively, etch the first GaAs layer and the first InGaP layer outside the third photoresist in sequence, and then remove the third photoresist. The first GaAs layer and the first InGaP layer at the bottom of the first upper convex island form the first lower island seat, and the first GaAs layer and the first InGaP layer at the bottom of the second upper convex island form the second lower island seat. The width of the first lower island seat is greater than that of the first upper convex island. (5) Coat the fourth photoresist on the Cap layer. The fourth photoresist covers all components on the Cap layer. Expose and develop the fourth photoresist to form an N-pole window that leads to the PN junction on the upper surface of the first lower island seat. Then perform a second metal evaporation to form an N-contact layer on the Cap layer at the bottom of the N-pole window. The thickness of the N-contact layer is less than the thickness of the fourth photoresist. Remove the excess metal from the second metal evaporation on the fourth photoresist and then remove the fourth photoresist. (6) Coat the fifth photoresist on the Cap layer. The fifth photoresist covers all components on the Cap layer. Expose and develop the fifth photoresist to form a sputtering window on the fifth photoresist that leads to the upper surface of the second upper convex island. Etch the second convex island and the second lower island seat through the sputtering window to etch away all the second convex island and the second lower island seat to form a sputtering cavity. (7) Perform thin film resistance sputtering to form a thin film resistance layer at the bottom of the sputtering cavity. The thickness of the thin film resistance layer is less than the thickness of the sputtering cavity. Remove the sputtering residue on the fifth photoresist and finally remove the fifth photoresist.

2. The thin-film resistive sputtering process with a PN junction structure as described in claim 1, characterized in that: The P-pole window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom; the N-pole window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom; and the sputtering window is a rectangular window or a trapezoidal window that is smaller at the top and larger at the bottom.

3. The thin-film resistive sputtering process with a PN junction structure as described in claim 1, characterized in that: The width of the second lower island is equal to or greater than the width of the second upper convex island.

4. The thin-film resistor sputtering process with a PN junction structure as described in claim 1, characterized in that: The width of the sputtering window is smaller than the width of the second upper convex island.

5. The thin-film resistive sputtering process with a PN junction structure as described in claim 1, characterized in that: The first photoresist is a positive or negative photoresist, the second photoresist is a positive or negative photoresist, the third photoresist is a positive or negative photoresist, the fourth photoresist is a positive or negative photoresist, and the fifth photoresist is a positive or negative photoresist.

6. The thin-film resistive sputtering process with a PN junction structure as described in claim 1, characterized in that: The substrate is a single-crystal silicon substrate, gallium arsenide substrate, gallium nitride substrate, indium phosphide substrate, or silicon carbide substrate.

7. The thin-film resistive sputtering process with a PN junction structure as described in claim 1, characterized in that: The thin-film resistor is made of TaN.

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