Radiation-resistant depletion GaN HEMT with high threshold voltage stability and manufacturing method of radiation-resistant depletion GaN HEMT

Abstract

The invention provides an anti-radiation depletion type GaN HEMT with high threshold voltage stability and a manufacturing method thereof, and belongs to the technical field of semiconductors, the anti-radiation depletion type GaN HEMT comprises a substrate layer and a gallium nitride layer which are arranged from bottom to top, an active region gallium nitride layer, a barrier layer, a first dielectric layer and a second dielectric layer are sequentially arranged in an active region on the upper surface of the gallium nitride layer from bottom to top, a strip-shaped gate metal layer is arranged on the upper surface of the second dielectric layer; a plurality of etching holes with different depths are formed in the gate metal layer, different Schottky metal layers are arranged in the etching holes with different depths, the Schottky metal layers with deeper etching holes are interconnected with the gate metal layer, and the Schottky metal layers with shallower etching holes are connected above the gate metal layer. Not only can interface state charges induced by irradiation be extracted out of the transistor through the Schottky metal layer in the shallow etching hole, but also carriers accumulated at the grid can flow out through the Schottky metal layer in the deep etching hole, and the anti-irradiation capability and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a radiation-resistant depletion-type GaN HEMT with high threshold voltage stability and a manufacturing method thereof. Background Art

[0002] GaN-based metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs) have the advantages of wide gate swing, low gate leakage current, high output power density and compatibility with Si-based MOSFET drivers by inserting a high-quality insulating dielectric layer between the gate metal and the AlGaN / GaN epitaxial structure. They are widely used in high-frequency and high-power fields such as mobile phone chargers, portable power supplies, adapters and data centers. In particular, the excellent material and device properties of GaN HEMT devices enable them to have a certain ability to resist radiation displacement damage, and are expected to be used in aerospace and various radiation environments, such as low-Earth orbit satellites and nuclear power plants for outer space communications. However, the radiation effects caused by solar activity, high-energy cosmic rays, and some high-energy protons, heavy ions and gamma rays in the Van Allen radiation belt will induce a large number of interface state traps and electron-hole pairs in the device body. Among them, the interface state traps will capture channel electrons to form fixed negative charges, which seriously affect the stability of the device threshold voltage; and these induced holes will accumulate in the sensitive area near the gate of the device, causing device degradation or even failure, which will threaten the safe operation of the entire system in severe cases. Therefore, in order to ensure the safe and reliable operation of the power system, the device needs to have high threshold voltage stability and radiation resistance. It must not only be able to safely discharge radiation-induced carriers but also be able to promptly extract electrons captured by interface states.

[0003] In the related art, a large number of carriers and interface states are generated in the transistor under irradiation conditions, among which the interface states between the dielectric layer and the barrier layer will capture channel electrons, causing the threshold voltage to drift. The dielectric layer in the MIS structure will block the movement of carriers, making it impossible for carriers to dissipate from the device body through the gate dielectric layer to the outside, causing carriers to accumulate in the area near the MIS gate, affecting the normal operation of the transistor, and in severe cases causing radiation damage to the transistor or even device burnout. Summary of the invention

[0004] In view of the above problems, the present invention provides a radiation-resistant depletion-type GaN HEMT with high threshold voltage stability and a manufacturing method thereof, so that the captured negative charges and carriers can be efficiently extracted to the outside of the transistor, avoiding the accumulation of more interface-state captured electrons and induced carriers in the gate region of the MISHEMT device after irradiation, improving the radiation resistance and reliability of the device, and can be applied in irradiation scenarios; and fully considering the high threshold voltage capability of the depletion-type device, avoiding the increase of leakage and power consumption due to low threshold voltage. The specific requirements for the technical solution are as follows: In a first aspect, the present invention provides a radiation-resistant depletion-type GaN HEMT with high threshold voltage stability, comprising a substrate layer and a gallium nitride layer arranged from bottom to top, wherein an active region gallium nitride layer, a barrier layer, a first dielectric layer and a second dielectric layer are arranged in sequence from bottom to top in an active region on an upper surface of the gallium nitride layer, a plurality of strip-shaped gate metal layers are arranged on an upper surface of the second dielectric layer, and the gate metal layer and the first dielectric layer and the second dielectric layer located directly therebelow form a gate of a MIS-type GaN HEMT; The gate metal layer is arranged with a plurality of first etching holes along its length direction, and a Schottky metal layer is arranged in the first etching holes; the Schottky metal layer includes a first Schottky metal layer and a second Schottky metal layer; the bottom of the first Schottky metal layer contacts the barrier layer, the side wall contacts the first dielectric layer and the second dielectric layer, and the top is interconnected with the gate metal layer; the bottom of the second Schottky metal layer contacts the top of the first dielectric layer, and the top contacts the Schottky metal interconnection layer.

[0005] In the gate structure of the MIS-type GaN HEMT, a plurality of etched holes of different depths are arranged at intervals in the gate metal layer, and different Schottky metal layers are arranged in the etched holes of different depths, wherein the Schottky metal layer with deeper etched holes is interconnected with the gate metal layer, and the Schottky metal layers with shallower etched holes are all connected above the gate metal layer, so that not only the interface state charges induced by radiation can be extracted from the transistor through the Schottky metal layer in the shallower etched holes, but also the carriers accumulated in the gate can flow out through the Schottky metal layer in the deeper etched holes; at the same time, the Schottky metal layer in the deeper etched holes and the barrier layer constitute a Schottky metal gate, which will be used as a composite gate of the device with the original MIS gate to coordinately regulate the threshold voltage of the device.

[0006] Since the gate metal layer and the first dielectric layer and the second dielectric layer are continuous in the length direction of the gate metal layer, the device has a normal gate function.

[0007] Optionally, the width of the gate metal layer is 2~5μm, and the length is 30~1500μm; the spacing between two adjacent first etching holes on the gate metal layer is 2~15μm, and the length of the first etching hole is 2~150μm; the minimum thickness from the side wall of the first etching hole to the outer wall of the gate metal layer is 0.4~1.2μm, and the minimum spacing between the side walls of the first etching holes located at both ends of the gate metal layer and the corresponding end faces of the gate metal layer is 1~10μm.

[0008] Optionally, the first Schottky metal layer and the second Schottky metal layer are alternately filled in the first etching hole along the length direction of the gate metal layer, and the second Schottky metal layer is located in the middle of the corresponding etching hole, with a length of 1.2~140μm and a width of 0.4~1.4μm; the second Schottky metal layer is not in contact with the gate metal layer, and the distance between its side wall and the side wall of the corresponding etching hole is 0.4~0.6μm.

[0009] Optionally, the top of the second Schottky metal layer is led out of the active area through a Schottky metal interconnection layer to form a Schottky metal pad area. The Schottky metal interconnection layer is strip-shaped and has a thickness of 0.7-2.5 μm.

[0010] Optionally, both sides of the gate are provided with ohmic metal layers with unequal spacing and the ohmic metal layers are in contact with the barrier layer, wherein the ohmic metal layer closer to the gate and the first metal interconnection layer located on the top thereof form a source electrode, and the ohmic metal layer farther from the gate and the second metal interconnection layer located on the top thereof form a drain electrode; the source electrode and the drain electrode are respectively led out of the active area through the corresponding metal interconnection layers to form a source pad area and a drain pad area; The second Schottky metal layer passes upward through the through hole on the first metal interconnection layer to connect with the Schottky metal interconnection layer, and the second Schottky metal layer and the first metal interconnection layer are not in contact; a gap is formed between the second Schottky metal layer and the first metal interconnection layer, and between the first metal interconnection layer and the Schottky metal interconnection layer, and a third dielectric layer is filled between the gaps; A third Schottky metal layer and a top metal layer are disposed above the interconnect metal layers in the source pad region and the drain pad region, and the top metal layer and the third Schottky metal layer are disposed one above the other; The gate metal layer leads out of the active area and converges to form a gate pad area, in which a third Schottky metal layer and a top metal layer are sequentially arranged above the gate metal layer; Except for the top surfaces of the drain pad region, the source pad region, the gate pad region and the Schottky metal pad region, the upper surface of the gallium nitride layer is filled with a third dielectric layer.

[0011] Here, the GaN HEMT device is a gallium nitride high electron mobility transistor, which effectively solves the problem of traditional low threshold voltage devices in which the interface state captured electrons induced by radiation affect the stability of the threshold voltage and the accumulation of induced carriers at the gate.

[0012] In the MIS-type GaN HEMT, except for the top surfaces of the drain pad region, the gate pad region, and the Schottky metal pad region, the active region layer and the surrounding areas are filled with materials to form a third dielectric layer for electrical isolation.

[0013] Optionally, a second etching hole arranged at intervals along the length direction of the gate metal layer is provided between the ohmic metal layer of the source and the gate metal layer, and a fourth Schottky metal layer is provided in the second etching hole; the bottom of the fourth Schottky metal layer is in contact with the barrier layer, a gap is formed between the side wall and the corresponding side wall of the etching hole, the top passes upward through the through hole on the first metal interconnection layer to be connected to the Schottky metal interconnection layer, and the fourth Schottky metal layer is not in contact with the first metal interconnection layer; a gap is formed between the fourth Schottky metal layer and the first metal interconnection layer, and a third dielectric layer is filled between the gaps.

[0014] By adopting the above technical solution, the Schottky metal layer between the gate and the source can serve as an electron discharge channel between the gate and the source in the off state, thereby preventing electrons from being injected from the source into the drain and increasing the off-state leakage.

[0015] Optionally, the spacing between the second etching hole and the side wall of the ohmic metal layer of the source electrode and the side wall of the gate metal layer is 0.4-0.8 μm; the spacing between two adjacent second etching holes is 6 μm-200 μm, and the spacing between the side walls of the two second etching holes located at both ends of the length direction of the gate metal layer and the corresponding edge of the active area is 3 μm-100 μm; The length of the second etching hole along the length direction of the gate metal layer is 4 μm to 300 μm, the width along the direction perpendicular to the length direction of the gate metal layer is 1.6 to 2.5 μm, and the distance between the fourth Schottky metal layer and the side wall of the second etching hole is 0.3 to 0.5 μm.

[0016] Optionally, the material of the first dielectric layer is any one of aluminum oxide and hafnium dioxide, with a thickness of 2-6 nm; the material of the second dielectric layer is one of silicon nitride and silicon dioxide, with a thickness of 15-20 nm.

[0017] Here, the reason for using the description of "first dielectric layer" is that the first ultra-thin high dielectric constant dielectric layer under the gate metal layer has the function of extracting the interface state charge between the first dielectric layer and the barrier layer, greatly improving the threshold voltage stability of the device; the reason for the description of "second dielectric layer" is that the thicker second dielectric layer under the gate metal layer has the ability to suppress gate leakage and increase the gate voltage swing and threshold voltage; and the third dielectric layer is mainly used for electrical isolation, and the second dielectric layer and the third dielectric layer can be made of the same material.

[0018] Local etched holes of different depths are prepared between the gate and source of the GaN HEMT with a double dielectric layer gate MIS structure and below the gate, and filled with Schottky metal layers. Not only can the electrons between the gate and source and the interface state charges induced by radiation flow out of the transistor from the Schottky metal layer in the off state, but also the carriers accumulated in the gate can be discharged to avoid the increase of leakage and threshold voltage drift caused by carrier accumulation. The lower end of the Schottky metal layer between the gate and the source contacts the top surface of the barrier layer. Part of the Schottky metal layer in the gate etched hole contacts the barrier layer and the gate; the lower end of the other part of the Schottky metal layer contacts the first ultra-thin gate dielectric layer, and the upper end connects the Schottky metal layer in all the gate metal layer etched holes and the Schottky metal layer between the gate and the source through a strip Schottky metal interconnect layer to form an independent pad area outside the active area, which is used to discharge carriers alone.

[0019] Here, the device performance of high threshold voltage is also fully considered, and a dual-dielectric layer MIS gate and Schottky metal gate composite structure design is proposed, and a device with normal electrical working capability is realized. The manufacturing method is simple and compatible with existing processes, which improves the overall device's radiation resistance.

[0020] In a second aspect, the present invention further provides a method for manufacturing a radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability, which is used to manufacture the above-mentioned radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability, comprising: Step 1: growing the substrate layer, the gallium nitride layer, the barrier layer, the first dielectric layer and the second dielectric layer on the epitaxial wafer from bottom to top, and etching away the first dielectric layer, the second dielectric layer, the barrier layer and part of the gallium nitride layer around the active area, wherein the thickness of the etched barrier layer is 5-10 nm, and the second dielectric layer contacts the barrier layer to form an ohmic contact with low resistance characteristics; Step 2: growing a third dielectric layer on the entire epitaxial wafer, etching the third dielectric layer, the first dielectric layer, the second dielectric layer and part of the barrier layer in the source and drain regions, and depositing an ohmic metal layer; Then, a third dielectric layer is grown on the entire epitaxial wafer, the third dielectric layer grown in the gate region and the gate pad region is removed by etching, and a gate metal layer is deposited; Step 3, etching the gate metal layer and the second dielectric layer in the pattern area to form an etching hole in the gate metal layer and depositing a second Schottky metal layer; Etching the gate metal layer and the first dielectric layer in the patterned area to form an etching hole in the gate metal layer; Growing a third dielectric layer on the entire sheet, etching the grown third dielectric layer in the etching hole of the gate metal layer and in the Schottky metal pad area, and then depositing the first Schottky metal layer; The second Schottky metal layer is in contact with the first dielectric layer and is not in contact with the gate metal layer; the second Schottky metal layer is not in contact with the first metal interconnection layer; when etching the third dielectric layer in the etching hole filling the second Schottky metal layer, a portion of the edge of the third dielectric layer is retained to ensure that the space between the second Schottky metal layer and the gate metal layer is filled with the third dielectric layer; Step 4, growing a third dielectric layer on the entire sheet, etching the ohmic metal layer of the drain, the ohmic metal layer of the source and the third dielectric layer grown on the gate metal layer, as well as the third dielectric layer grown on the source pad area, the drain pad area, and the gate pad area, and depositing the first metal interconnection layer and the second metal interconnection layer; Etching the first metal interconnection layer and the third dielectric layer above the gate metal layer pattern area, etching the third dielectric layer above the source pad area and the drain pad area, and etching the third dielectric layer in the Schottky metal pad area and depositing a strip-shaped Schottky metal interconnection layer and a third Schottky metal layer; Step 5: grow the third dielectric layer on the whole piece, etch the third dielectric layer in the upper part of the four pad areas: source pad area, drain pad area, gate pad area, and Schottky metal pad area, deposit the top metal layer, and complete the production of the GaN HEMT device.

[0021] Optionally, after the first Schottky metal layer is deposited in step 3, the third dielectric layer, the first dielectric layer and the second dielectric layer in the graphic area between the gate metal layer and the ohmic metal layer of the source are etched to form an etching hole for the fourth Schottky metal layer; Growing a third dielectric layer on the entire sheet, etching holes for the fourth Schottky metal layer and the third dielectric layer already grown in the Schottky metal pad region, and then depositing a fourth Schottky metal layer; The fourth Schottky metal layer is in contact with the barrier layer and is not in contact with the surrounding first dielectric layer and second dielectric layer; the fourth Schottky metal layer is not in contact with the first metal interconnection layer; when etching the third dielectric layer in the etching hole filling the fourth Schottky metal layer, a portion of the edge third dielectric layer is retained to ensure that the third dielectric layer is filled between the fourth Schottky metal layer and the first and second dielectric layers; When depositing the strip-shaped Schottky metal interconnection layer and the second metal interconnection layer in step four, the first metal interconnection layer and the third dielectric layer above the fourth Schottky metal layer and the gate metal layer graphic area are etched, and the third dielectric layer in the Schottky metal pad area is etched and the strip-shaped Schottky metal interconnection layer and the third Schottky metal layer are deposited at the same time.

[0022] The strip-shaped Schottky metal interconnection layer is not in contact with the source interconnection metal layer, but is in contact with the Schottky metal layer and the Schottky metal layer in the gate metal layer; the strip-shaped Schottky metal interconnection layer, the Schottky metal layer, and the space between the Schottky metal layer and the interconnection metal are all filled with a third dielectric layer; The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: (1) Local etched holes of different depths are prepared between the gate and source and below the gate of a GaN HEMT with a dual dielectric layer gate MIS structure, and filled with a Schottky metal layer, which not only allows the electrons between the gate and source and the interface state charges induced by radiation to flow out of the transistor from the Schottky metal layer in the off state, but also discharges the carriers accumulated in the gate to avoid the increase of leakage and threshold voltage drift caused by carrier accumulation. The lower end of the Schottky metal layer between the gate and the source contacts the top surface of the barrier layer, and part of the Schottky metal layer in the gate etched hole contacts the barrier layer and the gate; the lower end of the other part of the Schottky metal layer contacts the first ultra-thin gate dielectric layer, and the upper end connects the Schottky metal layer in all the gate metal layer etched holes with the Schottky metal layer between the gate and the source through a strip Schottky metal interconnect layer to form an independent pad area outside the active area, which is used solely for discharging carriers.

[0023] (2) The gate has a composite dielectric layer of an ultra-thin first dielectric layer with a high dielectric constant and a second dielectric layer. At the same time, holes of different depths are etched in the gate metal layer and filled with Schottky metal layers. This not only allows the interface state charges induced by radiation to be extracted from the transistor through the Schottky metal layer in the shallower etched holes, but also allows the carriers accumulated in the gate to flow out through the Schottky metal layer in the deeper etched holes. At the same time, the Schottky metal layer in the deeper etched holes and the barrier layer constitute a Schottky metal gate, which will serve as a composite gate of the device with the original MIS gate to coordinately control the threshold voltage of the device.

[0024] (3) Since the gate metal layer and the first dielectric layer and the second dielectric layer are continuous in the length direction of the gate metal layer, the device has normal gate function. In addition, the Schottky metal layer between the gate and the source can serve as an electron discharge channel between the gate and the source in the off state, preventing electrons from being injected from the source into the drain and increasing the off-state leakage. The device manufacturing method is simple and compatible with existing processes. It has the ability to efficiently extract radiation-induced interface state charges and carriers without affecting the normal operation of the transistor.

[0025] (4) The device performance with high threshold voltage is fully considered, and a dual-dielectric layer MIS gate and Schottky metal gate composite structure design is proposed to realize a device with normal electrical working capability. The manufacturing method is simple and compatible with existing processes, which improves the overall device's radiation resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a schematic diagram of the structure of a conventional MIS HEMT device in the related art; Figure 2 is a schematic diagram of the three-dimensional structure of the active region of the GaN HEMT device in an embodiment of the present invention; Figure 3 The three-dimensional structure of the GaN HEMT device in the embodiment of the present invention Figure 1 ; Figure 4 The three-dimensional structure of the GaN HEMT device in the embodiment of the present invention Figure 2 ; Figure 5 is a top view of a GaN HEMT device according to an embodiment of the present invention; Figure 6 is a process flow chart of manufacturing a GaN HEMT device according to an embodiment of the present invention; Figure 7 is a schematic diagram of a structure in which an active area is etched in an embodiment of the present invention; Figure 8 is a schematic diagram of the structure of etching and depositing an ohmic metal layer in an embodiment of the present invention; Fig. 9 It is a schematic diagram of the structure of depositing a gate metal layer, etching a shallow etched hole, and depositing a Schottky metal layer in an embodiment of the present invention; Fig.10 is a schematic diagram of a structure in which a relatively deep gate metal layer etching hole is formed and a Schottky metal layer is deposited in an embodiment of the present invention; Fig.11 is a schematic diagram of the structure of etching and depositing a Schottky metal layer between a gate and a source in an embodiment of the present invention; Fig.12 is a schematic diagram of a structure in which a first metal interconnection layer and a second metal interconnection layer are etched and deposited in an embodiment of the present invention; Fig.13 is a schematic diagram of the structure of etching and depositing a Schottky metal interconnection layer in an embodiment of the present invention; Fig.14 It is a schematic diagram of the structure for etching and depositing the top metal layer in an embodiment of the present invention.

[0028] In the figure: 1-substrate layer; 2-gallium nitride layer; 3-barrier layer; 4-first dielectric layer; 5-second dielectric layer; 6-third dielectric layer; 7-ohmic metal layer; 8-gate metal layer; 9-first Schottky metal layer; 10-second Schottky metal layer; 11-fourth Schottky metal layer; 12-first metal interconnection layer; 13-second metal interconnection layer; 14-third Schottky metal layer; 15-top metal layer; 16-Schottky metal interconnection layer. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0030] Figure 1 FIG. 1 is a schematic diagram of a conventional MIS HEMT device in the prior art provided by an embodiment of the present invention. In the related art, the existing MIS HEMT device is as follows: Figure 1 As shown, it includes a substrate layer 1 and a gallium nitride layer 2 arranged from bottom to top, and the active area on the upper surface of the gallium nitride layer 2 is sequentially arranged with an active area gallium nitride layer 2, a barrier layer 3, and a first dielectric layer 4 from bottom to top, and a plurality of strip-shaped gate metal layers 8 are arranged on the upper surface of the first dielectric layer, and both sides of the gate are provided with ohmic metal layers 7 with different spacings and the ohmic metal layers 7 are in contact with the barrier layer 3, wherein the ohmic metal layer 7 closer to the gate forms a source with the first metal interconnection layer 12 located on the top thereof, and the ohmic metal layer 7 farther from the gate forms a source with the metal interconnection layer located on the top thereof, and a third dielectric layer 6 is filled above the first dielectric layer 4. A large number of carriers and interface states will be generated in the transistor body under irradiation conditions, wherein the interface state between the dielectric layer and the barrier layer will capture channel electrons, resulting in a threshold voltage drift. The dielectric layer in the MIS structure blocks the movement of carriers, making it impossible for carriers to dissipate from the device body to the outside through the gate dielectric layer, causing carriers to accumulate in the area near the MIS gate, affecting the normal operation of the transistor. In severe cases, it can cause radiation damage to the transistor or even device burnout.

[0031] Therefore, in order to apply GaN-based MIS HEMT devices in irradiation scenarios, it is urgent to solve the problem of more interface state captured electrons and induced carriers accumulating in the gate region of MIS HEMT devices after irradiation, so that the captured negative charges and carriers can be efficiently extracted to the outside of the transistor, improving the device's radiation resistance and reliability. At the same time, it is necessary to fully consider the high threshold voltage capability of depletion-type devices to avoid low threshold voltages that increase leakage and power consumption.

[0032] Figure 2 is a schematic diagram of the three-dimensional structure of the active region of the GaN HEMT device in an embodiment of the present invention; Figure 3-Figure 5Schematic diagrams of the structure of a GaN HEMT device at three different viewing angles according to an embodiment of the present invention; Figure 6-Figure 13 The schematic diagrams are respectively the structural diagrams of different states in the manufacturing process of GaN HEMT devices. Based on the above defects, the embodiment of the present invention provides a radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability, such as Figure 2-Figure 5 As shown, it includes a substrate layer 1 and a gallium nitride layer 2 arranged from bottom to top, and the active area on the upper surface of the gallium nitride layer 2 is sequentially arranged with the active area gallium nitride layer 2, the barrier layer 3, the first dielectric layer 4 and the second dielectric layer 5 from bottom to top, and a plurality of strip-shaped gate metal layers 8 are arranged on the upper surface of the second dielectric layer 5, and the gate metal layer 8 and the first dielectric layer 4 and the second dielectric layer 5 located directly below it form the gate of the MIS-type GaN HEMT; The gate metal layer 8 is arranged with a plurality of first etching holes along its length direction, and a Schottky metal layer is arranged in the first etching holes; the Schottky metal layer includes a first Schottky metal layer 9 and a second Schottky metal layer 10; the bottom of the first Schottky metal layer 9 contacts the barrier layer 3, the side wall contacts the first dielectric layer 4 and the second dielectric layer 5, and the top is interconnected with the gate metal layer 8; the bottom of the second Schottky metal layer 10 contacts the top of the first dielectric layer 4, and the top contacts the Schottky metal interconnection layer 16.

[0033] At the gate structure of the MIS-type GaN HEMT, a plurality of etched holes of different depths arranged at intervals are provided in the gate metal layer, and different Schottky metal layers are provided in the etched holes of different depths, wherein the Schottky metal layer with a deeper etched hole (i.e., the first Schottky metal layer 9) is interconnected with the gate metal layer, and the Schottky metal layer with a shallower etched hole (i.e., the second Schottky metal layer 10) is connected above the gate metal layer, so that not only the interface state charges induced by radiation can be extracted from the transistor through the Schottky metal layer in the shallower etched hole, but also the carriers accumulated in the gate can flow out through the Schottky metal layer in the deeper etched hole; at the same time, the Schottky metal layer in the deeper etched hole and the barrier layer constitute a Schottky metal gate, which will serve as a composite gate of the device with the original MIS gate to coordinately regulate the threshold voltage of the device.

[0034] Since the gate metal layer and the first dielectric layer and the second dielectric layer are continuous in the length direction of the gate metal layer, the device has a normal gate function.

[0035] Exemplarily, the width of the gate metal layer 8 is 2~5μm, and the length is 30~1500μm; the spacing between two adjacent first etching holes on the gate metal layer 8 is 2~15μm, and the length of the first etching hole is 2~150μm; the minimum thickness from the side wall of the first etching hole to the outer wall of the gate metal layer 8 is 0.4~1.2μm, and the minimum spacing between the side walls of the first etching holes located at both ends of the gate metal layer 8 and the corresponding end faces of the gate metal layer 8 is 1~10μm.

[0036] More specifically, the cross-section of the first etched hole is circular, elliptical, polygonal or other irregularly shaped shapes; in the etched hole, the cross-sections of the first Schottky metal layer 9 and the second Schottky metal layer 10 are circular, elliptical, polygonal or other irregularly shaped shapes.

[0037] Optionally, the first Schottky metal layer 9 and the second Schottky metal layer 10 are alternately filled in the first etching hole along the length direction of the gate metal layer 8, and the second Schottky metal layer 10 is located in the middle of the corresponding etching hole, with a length of 1.2~140μm and a width of 0.4~1.4μm; the second Schottky metal layer 10 is not in contact with the gate metal layer 8, and the distance between its side wall and the side wall of the corresponding etching hole is 0.4~0.6μm.

[0038] Optionally, the top of the second Schottky metal layer 10 is led out of the active area through a Schottky metal interconnection layer 16 to form a Schottky metal pad area. The Schottky metal interconnection layer 16 is strip-shaped and has a thickness of 0.7-2.5 μm.

[0039] Optionally, both sides of the gate are provided with ohmic metal layers 7 with unequal spacing, and the ohmic metal layers 7 are in contact with the barrier layer 3, wherein the ohmic metal layer 7 closer to the gate and the first metal interconnection layer 12 located on the top thereof form a source electrode, and the ohmic metal layer 7 farther from the gate and the second metal interconnection layer 13 located on the top thereof form a drain electrode; the source electrode and the drain electrode are respectively led out of the active area through the corresponding metal interconnection layers to form a source pad area and a drain pad area; The second Schottky metal layer 10 passes upward through the through hole on the first metal interconnection layer 12 to connect with the Schottky metal interconnection layer 16, and the second Schottky metal layer 10 and the first metal interconnection layer 12 are not in contact with each other; there is a gap between the second Schottky metal layer 10 and the first metal interconnection layer 12, and between the first metal interconnection layer 12 and the Schottky metal interconnection layer 16, and the gap is filled with a third dielectric layer 6. Exemplarily, the gap between the first metal interconnection layer 12 and the Schottky metal interconnection layer 16 is 0.8-1 μm; the fourth Schottky metal layer 11 is 2-3 μm thick, and the distance between the fourth Schottky metal layer 11 and the side wall of the through hole on the first metal interconnection layer 12 is 0.8-1 μm.

[0040] A third Schottky metal layer 14 and a top metal layer 15 are disposed above the interconnection metal layers in the source pad region and the drain pad region, and the top metal layer 15 and the third Schottky metal layer 14 are disposed one above the other; The gate metal layer 8 leads out of the active area and converges to form a gate pad area. In the gate pad area, a third Schottky metal layer 14 and a top metal layer 15 are sequentially arranged above the gate metal layer 8; Here, each gate and the adjacent source and drain electrodes on both sides form a fork finger, and the gate electrodes of all the fork fingers are led out of the active area of ​​the MIS-type GaN HEMT through the gate metal layer 8 to form a gate pad area; the source electrodes and drain electrodes of all the fork fingers are led out of the active area of ​​the HEMT device through the interconnect metal layer to form a source pad area and a drain pad area respectively; Except for the top surfaces of the drain pad region, the source pad region, the gate pad region and the Schottky metal pad region, the upper surface of the gallium nitride layer 2 is filled with a third dielectric layer 6 .

[0041] Exemplarily, in the active area, the distance between the gate metal layer 8 and the ohmic metal layer 7 of the source is 2.4-4.1 μm, and the distance between the gate metal layer 8 and the ohmic metal layer of the drain is 5-20 μm; the width of the ohmic metal layer of the source and the ohmic metal layer of the drain is 1.5-3.5 μm; the first metal interconnection layer 12 exceeds the drain side of the gate metal layer 8 by 1.5-10 μm; the second metal interconnection layer 13 of the drain exceeds both sides of the ohmic metal layer of the drain by 1.5-5 μm; the spacing between the first metal interconnection layer 12 of the source and the second metal interconnection layer 13 of the drain is 2-5 μm; The ohmic metal layer 7 of the source and the ohmic metal layer 7 of the drain are both in contact with the top surface of the barrier layer 3, and have a thickness of 0.3~1.2μm; the thickness of the first metal interconnection layer 12 and the second metal interconnection layer 13 is 1.2~2μm; the thickness of the gate metal layer 8 is 0.4~0.8μm; the thickness of the first Schottky metal layer 9 is 0.4~0.8μm; the thickness of the second Schottky metal layer 10 is 1~1.5μm; the spacing between the upper strip-shaped Schottky metal interconnection layer 16 and the gate metal layer 8 is 2~5μm.

[0042] Optionally, a second etching hole arranged at intervals along the length direction of the gate metal layer 8 is provided between the ohmic metal layer 7 of the source and the gate metal layer 8, and a fourth Schottky metal layer 11 is provided in the second etching hole; the bottom of the fourth Schottky metal layer 11 is in contact with the barrier layer 3, a gap is formed between the side wall and the corresponding side wall of the etching hole, the top passes upward through the through hole on the first metal interconnection layer 12 to be connected to the Schottky metal interconnection layer 16, and the fourth Schottky metal layer 11 is not in contact with the first metal interconnection layer 12; a gap is formed between the fourth Schottky metal layer 11 and the first metal interconnection layer 12, and the gap is filled with a third dielectric layer 6.

[0043] Here, the Schottky metal layer between the gate and the source can serve as an electron discharge channel between the gate and the source in the off state, thereby preventing electrons from being injected from the source into the drain and increasing the off-state leakage.

[0044] Exemplarily, the spacing between the second etching hole and the side wall of the ohmic metal layer 7 of the source and the side wall of the gate metal layer 8 is 0.4-0.8 μm; the spacing between two adjacent second etching holes is 6 μm-200 μm, and the spacing between the side walls of the two second etching holes located at both ends of the length direction of the gate metal layer 8 and the corresponding edge of the active area is 3 μm-100 μm; The length of the second etching hole along the length direction of the gate metal layer 8 is 4 μm-300 μm, the width along the direction perpendicular to the length direction of the gate metal layer 8 is 1.6-2.5 μm, and the distance between the fourth Schottky metal layer 11 and the side wall of the second etching hole is 0.3-0.5 μm.

[0045] Optionally, the cross-section of the second etched hole is circular, elliptical, polygonal or other irregularly shaped shapes; in the etched hole, the cross-section of the fourth Schottky metal layer 11 is circular, elliptical, polygonal or other irregularly shaped shapes.

[0046] Exemplarily, the bottom surface of the fourth Schottky metal layer 11 is located in the middle of the second etching hole and the length of the fourth Schottky metal layer 11 is 3~250μm. It is interconnected with the Schottky metal interconnection layer 16 located above the gate metal layer 8, and the Schottky metal interconnection layer 16 has a thickness of 0.7~2.5μm and a width of 4~8.3μm.

[0047] Optionally, the material of the first dielectric layer is any one of aluminum oxide and hafnium dioxide, with a thickness of 2-6 nm; the material of the second dielectric layer is one of silicon nitride and silicon dioxide, with a thickness of 15-20 nm.

[0048] Here, the reason for using the description of "first dielectric layer" is that the first ultra-thin high dielectric constant dielectric layer under the gate metal layer has the function of extracting the interface state charge between the first dielectric layer and the barrier layer, greatly improving the threshold voltage stability of the device; the reason for the description of "second dielectric layer" is that the thicker second dielectric layer under the gate metal layer has the ability to suppress gate leakage and increase the gate voltage swing and threshold voltage; and the third dielectric layer is mainly used for electrical isolation, and its material can be any one of silicon dioxide, silicon nitride or polyimide or a combination of more than two; and the second dielectric layer and the third dielectric layer can be made of the same material.

[0049] It is easy to understand that the side wall of the second Schottky metal layer 10 in the etched hole of the gate metal layer 8 is completely and tightly wrapped by the third dielectric layer 6; the second Schottky metal layer 10 and the third dielectric layer 6 are completely and tightly wrapped by the gate metal layer 8 and the second dielectric layer 5; the first Schottky metal layer 9 is completely and tightly wrapped by the gate metal layer 8, the first dielectric layer 4 and the second dielectric layer 5; the fourth Schottky metal layer 11 and the third dielectric layer 6 are completely and tightly wrapped by the first dielectric layer 4 and the second dielectric layer 5.

[0050] Exemplarily, in the active area, the distance between the edges of the first dielectric layer and the second dielectric layer and the ohmic metal layer 7 / gate metal layer 8 is 3~6μm; the number of cross fingers in the active area is 1~900; the minimum width of the metal leads of the gate metal layer 8, the Schottky metal interconnection layer 16, the first metal interconnection layer 12 and the second metal interconnection layer 13 outside the active area is 2~8μm; the gate pad area, the source pad area, the drain pad area and the Schottky metal pad area outside the active area are 10~20μm away from the active area; the width of the four pad areas is 100~700μm, and the length is 100~2000μm; the thickness of the top metal layer in the four pad areas is 2.5~6μm.

[0051] Local etched holes of different depths are prepared between the gate and source of the GaN HEMT with a double dielectric layer gate MIS structure and below the gate, and filled with Schottky metal layers. Not only can the electrons between the gate and source and the interface state charges induced by radiation flow out of the transistor from the Schottky metal layer in the off state, but also the carriers accumulated in the gate can be discharged to avoid the increase of leakage and threshold voltage drift caused by carrier accumulation. The lower end of the Schottky metal layer between the gate and the source contacts the top surface of the barrier layer. Part of the Schottky metal layer in the gate etched hole contacts the barrier layer and the gate; the lower end of the other part of the Schottky metal layer contacts the first ultra-thin gate dielectric layer, and the upper end connects the Schottky metal layer in all the gate metal layer etched holes and the Schottky metal layer between the gate and the source through a strip Schottky metal interconnect layer to form an independent pad area outside the active area, which is used to discharge carriers alone.

[0052] The device performance with high threshold voltage is also fully considered here, and a dual-dielectric layer MIS gate and Schottky metal gate composite structure design is proposed, and a device with normal electrical working capability is realized. The manufacturing method is simple, compatible with existing processes, and improves the overall device's radiation resistance.

[0053] In a second aspect, the present invention also provides a method for manufacturing a radiation-resistant depletion-type GaN HEMT with high threshold voltage stability, which is used to manufacture the above-mentioned radiation-resistant depletion-type GaN HEMT with high threshold voltage stability, see Figure 6 ,include: Step S1, see Figure 7 , the substrate layer 1, the gallium nitride layer 2, the barrier layer 3, the first dielectric layer 4 and the second dielectric layer 5 are sequentially grown on the epitaxial wafer from bottom to top, and the first dielectric layer 4, the second dielectric layer 5, the barrier layer 3 and part of the gallium nitride layer 2 around the active area are removed by inductively coupled plasma dry etching, wherein the thickness of the etched barrier layer 3 is 5-10 nm, and the second dielectric layer 5 is in contact with the barrier layer 3 to form an ohmic contact with low resistance characteristics; Step S2, growing a third dielectric layer on the entire epitaxial wafer by plasma enhanced chemical vapor deposition, etching the third dielectric layer, the first dielectric layer 4, the second dielectric layer 5 and part of the barrier layer 3 in the source and drain regions by inductively coupled plasma dry etching, and depositing an ohmic metal layer 7, see Figure 8 ; Then grow a third dielectric layer on the entire epitaxial wafer, etch away the gate region and the gate pad region to form the third dielectric layer, and deposit a gate metal layer 8; Step S3, etching the gate metal layer 8 and the second dielectric layer 5 in the pattern area by inductively coupled plasma dry etching to form an etching hole in the gate metal layer 8 and depositing a second Schottky metal layer 10, see Fig. 9; The gate metal layer 8 and the first dielectric layer 4 in the pattern area are etched by inductively coupled plasma dry etching to form an etching hole of the gate metal layer 8; The third dielectric layer is grown on the whole sheet, the third dielectric layer grown in the etching hole of the gate metal layer 8 and the Schottky metal pad area is etched, and then the first Schottky metal layer 9 is deposited. The first Schottky metal layer 9 is in contact with the barrier layer 3 and the gate metal layer 8. Fig.10 ; The second Schottky metal layer 10 is in contact with the first dielectric layer 4 and is not in contact with the gate metal layer 8; the second Schottky metal layer 10 is not in contact with the first metal interconnect layer 12; when etching the third dielectric layer in the etching hole filling the second Schottky metal layer 10, a portion of the edge of the third dielectric layer is retained to ensure that the space between the second Schottky metal layer 10 and the gate metal layer 8 is filled with the third dielectric layer; Step S4, growing the third dielectric layer on the whole sheet, etching the drain ohmic metal layer 7, the source ohmic metal layer 7 and the gate metal layer 8, and the source pad area, the drain pad area, and the gate pad area. The third dielectric layer is deposited on the first metal interconnection layer 12 and the second metal interconnection layer 13, see Fig.12 ; The first metal interconnection layer 12 and the third dielectric layer above the pattern area of ​​the gate metal layer 8 are etched by inductively coupled plasma dry etching, the third dielectric layer above the source pad area and the drain pad area is etched, and the third dielectric layer in the Schottky metal pad area is etched and a strip-shaped Schottky metal interconnection layer 16 and a third Schottky metal layer 14 are deposited. Fig.13 ; Step S5, growing the third dielectric layer in the whole piece, etching the third dielectric layer in the upper part of the four pad areas, namely the source pad area, the drain pad area, the gate pad area and the Schottky metal pad area, and depositing the top metal layer 15, see Fig.14 , completing the fabrication of GaN HEMT devices.

[0054] Optionally, after the first Schottky metal layer 9 is deposited in step S3, the third dielectric layer, the first dielectric layer 4 and the second dielectric layer 5 in the graphic area between the gate metal layer 8 and the ohmic metal layer 7 of the source are etched by inductively coupled plasma dry etching to form an etching hole for the fourth Schottky metal layer 11; The third dielectric layer is grown on the whole sheet, the etching hole of the fourth Schottky metal layer 11 and the third dielectric layer grown in the Schottky metal pad area are etched, and then the fourth Schottky metal layer 11 is deposited, see Fig.11 ; The fourth Schottky metal layer 11 is in contact with the barrier layer 3, and is not in contact with the surrounding first dielectric layer 4 and second dielectric layer 5; the fourth Schottky metal layer 11 is not in contact with the first metal interconnect layer 12; when etching the third dielectric layer in the etching hole filling the fourth Schottky metal layer 11, a portion of the edge third dielectric layer is retained to ensure that the third dielectric layer is filled between the fourth Schottky metal layer 11 and the first and second dielectric layers; When depositing the strip-shaped Schottky metal interconnection layer 16 in step S4, the first metal interconnection layer 12 and the third dielectric layer above the fourth Schottky metal layer 11 and the gate metal layer 8 graphic area are etched, and the third dielectric layer in the Schottky metal pad area is etched and the strip-shaped Schottky metal interconnection layer 16 and the second metal interconnection layer 13 are deposited at the same time.

[0055] The strip-shaped Schottky metal interconnection layer 16 is not in contact with the first interconnection metal layer 12, but is in contact with the second Schottky metal layer 10 and the fourth Schottky metal layer 11; a third dielectric layer is filled between the strip-shaped Schottky metal interconnection layer 16, the second Schottky metal layer 10, the fourth Schottky metal layer 11 and the first metal interconnection layer 12; The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability manufactured by the above manufacturing method is different from the mainstream MIS junction HEMT device. The Schottky metal layer and the barrier layer in the deeper etched hole form a Schottky metal gate, which is used as a composite gate of the device with the original double-dielectric layer MIS gate to coordinately control the device threshold voltage and increase the gate threshold voltage swing capability. Since the gate metal layer and the first dielectric layer and the second dielectric layer are uninterrupted in the length direction of the gate metal layer, the device has normal gate function.

[0056] The present invention also fully considers the influence of radiation-induced interface state charge on the stability of device threshold voltage, the increase of leakage current by source carrier injection, the influence of carrier accumulation under the gate on device stability, and the influence of low threshold voltage on power consumption and leakage, and proposes a radiation-resistant GaN-based HEMT device with high threshold voltage stability having a double dielectric layer gate and a composite gate. The manufacturing method is simple and compatible with existing processes, and a solution is proposed for improving the low threshold voltage stability and radiation resistance of depletion-type devices.

[0057] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words "first", "second" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0058] The above descriptions are merely optional embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability, characterized in that: The invention comprises a substrate layer (1) and a gallium nitride layer (2) arranged from bottom to top, wherein an active region on the upper surface of the gallium nitride layer (2) is provided with an active region gallium nitride layer (2), a barrier layer (3), a first dielectric layer (4) and a second dielectric layer (5) in sequence from bottom to top, and a plurality of strip-shaped gate metal layers (8) are provided on the upper surface of the second dielectric layer (5), and the gate metal layer (8) and the first dielectric layer (4) and the second dielectric layer (5) located directly below the gate metal layer (8) form a gate of a MIS-type GaN HEMT; The gate metal layer (8) is provided with a plurality of first etching holes arranged along its length direction, and a Schottky metal layer is provided in each of the first etching holes; the Schottky metal layer comprises a first Schottky metal layer (9) and a second Schottky metal layer (10); the first Schottky metal layer (9) is in contact with the barrier layer (3) at the bottom, in contact with the first dielectric layer (4) and the second dielectric layer (5) at the sidewall, and interconnected with the gate metal layer (8) at the top; the second Schottky metal layer (10) is in contact with the top of the first dielectric layer (4) at the bottom, and in contact with the Schottky metal interconnection layer (16) at the top.

2. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 1, characterized in that: The gate metal layer (8) has a width of 2 to 5 μm and a length of 30 to 1500 μm; the spacing between two adjacent first etching holes on the gate metal layer (8) is 2 to 15 μm, and the length of the first etching hole is 2 to 150 μm; the minimum thickness from the side wall of the first etching hole to the outer side wall of the gate metal layer (8) is 0.4 to 1.2 μm, and the minimum spacing between the side walls of the first etching holes located at both ends of the gate metal layer (8) and the corresponding end faces of the gate metal layer (8) is 1 to 10 μm.

3. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 1, characterized in that: The first Schottky metal layer (9) and the second Schottky metal layer (10) are alternately filled in the first etched hole along the length direction of the gate metal layer (8), and the second Schottky metal layer (10) is located in the middle of the corresponding etched hole, with a length of 1.2 to 140 μm and a width of 0.4 to 1.4 μm; the second Schottky metal layer (10) is not in contact with the gate metal layer (8), and the spacing between its side wall and the side wall of the corresponding etched hole is 0.4 to 0.6 μm.

4. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 1, characterized in that: The top of the second Schottky metal layer (10) is led out of the active area through a Schottky metal interconnect layer (16) to form a Schottky metal pad area; the Schottky metal interconnect layer (16) is strip-shaped and has a thickness of 0.7 to 2.5 μm.

5. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 4, characterized in that: Both sides of the gate are provided with ohmic metal layers (7) with different spacings, and the ohmic metal layers (7) are in contact with the barrier layer (3), wherein the ohmic metal layer (7) closer to the gate and the first metal interconnection layer (12) located on the top thereof form a source electrode, and the ohmic metal layer (7) farther from the gate and the second metal interconnection layer (13) located on the top thereof form a drain electrode; the source electrode and the drain electrode are respectively led out of the active area through the corresponding metal interconnection layers to form a source pad area and a drain pad area; The second Schottky metal layer (10) passes upward through the through hole on the first metal interconnection layer (12) to be connected to the Schottky metal interconnection layer (16), and the second Schottky metal layer (10) and the first metal interconnection layer (12) are not in contact with each other; a gap is formed between the second Schottky metal layer (10) and the first metal interconnection layer (12), and between the first metal interconnection layer (12) and the Schottky metal interconnection layer (16), and a third dielectric layer (6) is filled between the gaps; A third Schottky metal layer (14) and a top metal layer (15) are provided above the interconnection metal layers of the source pad region and the drain pad region, and the top metal layer (15) and the third Schottky metal layer (14) are arranged one above the other; The gate metal layer (8) leads out of the active area and converges to form a gate pad area, in which a third Schottky metal layer (14) and a top metal layer (15) are sequentially arranged above the gate metal layer (8); Except for the top surfaces of the drain pad region, the source pad region, the gate pad region and the Schottky metal pad region, the upper surface of the gallium nitride layer (2) is filled with a third dielectric layer (6).

6. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 5, characterized in that: A second etching hole arranged at intervals along the length direction of the gate metal layer (8) is provided between the ohmic metal layer (7) of the source electrode and the gate metal layer (8), and a fourth Schottky metal layer (11) is provided in the second etching hole; the bottom of the fourth Schottky metal layer (11) is in contact with the barrier layer (3), a gap is formed between the side wall and the corresponding side wall of the etching hole, the top passes upward through the through hole on the first metal interconnection layer (12) to be connected to the Schottky metal interconnection layer (16), and the fourth Schottky metal layer (11) is not in contact with the first metal interconnection layer (12); a gap is formed between the fourth Schottky metal layer (11) and the first metal interconnection layer (12), and the gap is filled with a third dielectric layer (6).

7. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 6, characterized in that: The spacing between the second etching hole and the side wall of the ohmic metal layer (7) of the source electrode and the side wall of the gate metal layer (8) is 0.4 to 0.8 μm; the spacing between two adjacent second etching holes is 6 to 200 μm, and the spacing between the side walls of the two second etching holes located at the two ends of the gate metal layer (8) in the length direction and the corresponding edge of the active area is 3 to 100 μm; The length of the second etching hole along the length direction of the gate metal layer (8) is 4 μm to 300 μm, the width along the direction perpendicular to the length of the gate metal layer (8) is 1.6 to 2.5 μm, and the spacing between the fourth Schottky metal layer (11) and the side wall of the second etching hole is 0.3 to 0.5 μm.

8. The radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to any one of claims 1 to 7, characterized in that: The material of the first dielectric layer is any one of aluminum oxide and hafnium dioxide, and the thickness is 2-6 nm; the material of the second dielectric layer is one of silicon nitride and silicon dioxide, and the thickness is 15-20 nm.

9. A method for manufacturing a radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability, for manufacturing the radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability as claimed in any one of claims 1 to 7, characterized in that: include: Step 1: growing the substrate layer (1), the gallium nitride layer (2), the barrier layer (3), the first dielectric layer (4) and the second dielectric layer (5) on the epitaxial wafer in order from bottom to top, and etching away the first dielectric layer (4), the second dielectric layer (5), the barrier layer (3) and part of the gallium nitride layer (2) around the active area; Step 2: growing a third dielectric layer on the entire epitaxial wafer, etching the third dielectric layer, the first dielectric layer (4), the second dielectric layer (5) and part of the barrier layer (3) in the source and drain regions, and depositing an ohmic metal layer (7); Then, a third dielectric layer is grown on the entire epitaxial wafer, the third dielectric layer grown in the gate region and the gate pad region is removed by etching, and a gate metal layer (8) is deposited; Step three, etching the gate metal layer (8) and the second dielectric layer (5) in the patterned area to form an etching hole in the gate metal layer (8) and depositing a second Schottky metal layer (10); Etching the gate metal layer (8) and the first dielectric layer (4) in the patterned area to form an etching hole in the gate metal layer (8); Growing a third dielectric layer in its entirety, etching the grown third dielectric layer in the etching hole of the gate metal layer (8) and in the Schottky metal pad region, and then depositing a first Schottky metal layer (9); Step 4, growing a third dielectric layer on the entire sheet, etching the drain ohmic metal layer (7), the source ohmic metal layer (7) and the third dielectric layer grown above the gate metal layer (8), as well as the third dielectric layer grown above the source pad region, the drain pad region and the gate pad region, and depositing a first metal interconnection layer (12) and a second metal interconnection layer (13); Etching the first metal interconnection layer (12) and the third dielectric layer above the patterned area of ​​the gate metal layer (8), etching the third dielectric layer above the source pad area and the drain pad area, and etching the third dielectric layer in the Schottky metal pad area and depositing a strip-shaped Schottky metal interconnection layer (16) and a third Schottky metal layer (14); Step 5: growing a third dielectric layer on the entire surface, etching the third dielectric layer in the upper part of the four pad areas, namely, the source pad area, the drain pad area, the gate pad area, and the Schottky metal pad area, and depositing a top metal layer (15), thereby completing the manufacturing of the GaN HEMT device.

10. The method for manufacturing the radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability according to claim 9, characterized in that: After the deposition of the first Schottky metal layer (9) is completed in step three, the third dielectric layer, the first dielectric layer (4) and the second dielectric layer (5) in the graphic area between the gate metal layer (8) and the ohmic metal layer (7) of the source are etched to form an etching hole for the fourth Schottky metal layer (11); Growing a third dielectric layer in its entirety, etching holes for the fourth Schottky metal layer (11) and the third dielectric layer already grown in the Schottky metal pad region, and then depositing the fourth Schottky metal layer (11); When depositing the strip-shaped Schottky metal interconnection layer (16) and the third Schottky metal layer (14) in step 4, the first metal interconnection layer (12) and the third dielectric layer above the fourth Schottky metal layer (11) and the gate metal layer (8) graphic region are etched, and the third dielectric layer in the Schottky metal pad region is etched and the strip-shaped Schottky metal interconnection layer (16) and the third Schottky metal layer (14) are deposited simultaneously.

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