Integrated circuit device

Abstract

An integrated circuit device includes: a substrate having a front surface and a back surface opposite the front surface, and including a fin-type active region in the front surface and a substrate recess in the back surface; an isolation film in the substrate defining a fin-type active region; a source / drain region on the fin-type active region; a contact plug over the substrate; a backside power rail at least partially filling the substrate recess; and a via power rail electrically connected to the contact plug, the via power rail extending into the isolation membrane and connected to the back power rail. A side surface of the back power rail and a side surface of the via power rail form an obtuse angle at a portion where the back power rail is connected to the via power rail.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0098889 filed in the Korean Intellectual Property Office on July 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates generally to integrated circuit devices, and more particularly, to integrated circuit devices having a power delivery network (PDN). Background Art

[0004] With the development of electronic technology, the miniaturization of integrated circuit devices is progressing rapidly. In order to efficiently transmit power to integrated circuit devices with high integration density, integrated circuit devices with PDN are being introduced. Summary of the invention

[0005] The inventive concept provides an integrated circuit device having a power delivery network therein capable of reliably transmitting power to its highly integrated components.

[0006] According to one aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a front side and a back side opposite to the front side, and including a fin type active region in the front side and a substrate recess in the back side; an isolation film in the substrate defining the fin type active region; a source / drain region on the fin type active region; a contact plug over the substrate; a back side power rail at least partially filling the substrate recess; and a via power rail electrically connected to the contact plug, the via power rail passing through the isolation film and connected to the back side power rail. A side surface of the back side power rail and a side surface of the via power rail form an obtuse angle at a portion where the back side power rail is connected to the via power rail.

[0007] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a front side and a back side opposite to the front side, and including a fin type active region in the front side and a substrate recess in the back side; an isolation film in the substrate, defining the fin type active region; a source / drain region on the fin type active region; an inter-gate insulating layer on the substrate and surrounding the source / drain region (i.e., extending around the source / drain region); a contact plug passing through at least a portion of the inter-gate insulating layer and connected to the source / drain region; a back side power rail at least partially filling the substrate recess; a via power rail passing through a portion of the inter-gate insulating layer and the isolation film and connected to the back side power rail; and a via contact on the contact plug and the via power rail and connecting the contact plug to the via power rail. The side surface of the back side power rail and the side surface of the via power rail form an obtuse angle at the portion where the back side power rail is connected to the via power rail, and the back side power rail contacts the lower side surface and bottom surface of the via power rail.

[0008] According to another aspect of the inventive concept, an integrated circuit device is provided, comprising: a substrate having a front side and a back side opposite to the front side, and comprising a fin-type active region in the front side and a substrate recess in the back side, the fin-type active region extending in a first horizontal direction parallel to the front side of the substrate; an isolation film in the substrate, defining the fin-type active region; a back side power rail, at least partially filling the substrate recess and comprising a rounded side surface protruding toward the substrate and the isolation film; a plurality of gate electrodes, on the fin-type active region, and extending parallel to each other in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction; a cross (i.e., intersecting); a source / drain region on the fin-type active area and between a pair of gate electrodes adjacent to each other in a first horizontal direction among a plurality of gate electrodes; an inter-gate insulating layer at least partially filling a space between the plurality of gate electrodes and surrounding the source / drain region; a contact plug passing through at least a portion of the inter-gate insulating layer and connected to the source / drain region; a via power rail passing through a portion of the inter-gate insulating layer and an isolation film and connected to a back power rail; a cover insulating layer surrounding the via power rail; and a via contact on the contact plug and the via power rail and connecting the contact plug to the via power rail. A side surface of the back power rail and a side surface of the via power rail form an obtuse angle at a portion where the back power rail is connected to the via power rail, and the back power rail includes a wedge-shaped portion extending between the via power rail and the cover insulating layer, and has a symmetrical structure in a horizontal direction relative to a center of a bottom surface of the via power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals (when used) designate corresponding elements throughout the several drawings, in which:

[0010] Figures 1A to 13is a cross-sectional view of an intermediate process stage in an example method of manufacturing an integrated circuit device according to one or more embodiments;

[0011] Fig.14A and Fig. 14B is a cross-sectional view of an integrated circuit device according to an embodiment;

[0012] Figures 15 to 17 is a cross-sectional view illustrating an example method of manufacturing an integrated circuit device according to one or more embodiments;

[0013] Fig.18 is a cross-sectional view illustrating an example method of manufacturing an integrated circuit device according to one or more embodiments; and

[0014] Fig.19A and Fig.19B is a cross-sectional view of an integrated circuit device according to an embodiment. DETAILED DESCRIPTION

[0015] Figures 1A to 13 is a cross-sectional view of an intermediate process stage in an exemplary method of manufacturing an integrated circuit device according to one or more embodiments. Figure 1B and Figure 1C Along Figure 1A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figure 2B and Figure 2C Along Figure 2A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figure 3B and Figure 3C Along Figure 3A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figure 4B and Figure 4C Along Figure 4A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figure 5B and Figure 5C Along Figure 5A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figure 6B and Figure 6C Along Fig. 6A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figure 7B and Figure 7C Along Fig. 7A The cross-sectional view taken along the line BB' and the line CC' in FIG. Figures 8 to 13 is to be with Fig. 7A The corresponding position of line B-B' in the figure is rotated 180 degrees and then along Fig. 7A A cross-sectional view taken along line BB' in FIG.

[0016] refer to Figures 1A to 1C, a plurality of sacrificial semiconductor layers 106S and a plurality of nanosheet semiconductor layers are alternately stacked on the substrate 110 in a vertical direction (i.e., Z direction) perpendicular to the upper portion of the substrate 100. The sacrificial semiconductor layer 106S may include a semiconductor material different from that of the nanosheet semiconductor layer. In some embodiments, the nanosheet semiconductor layer may be composed of a single material. In some embodiments, the nanosheet semiconductor layer may include the same material as the substrate 110. In some embodiments, the sacrificial semiconductor layer 106S may include silicon germanium (SiGe), and the nanosheet semiconductor layer may include silicon (Si). However, embodiments are not limited thereto.

[0017] The sacrificial semiconductor layers 106S may have the same cross-sectional thickness as each other (in the Z direction), but the embodiment is not limited thereto. In some embodiments, the thickness of the sacrificial semiconductor layer 106S closest to the substrate 110 among the sacrificial semiconductor layers 106S in the z direction may be greater than the thickness of any other sacrificial semiconductor layer 106S.

[0018] The substrate 110 may include a semiconductor material (e.g., Si or germanium (Ge)), a compound semiconductor material (e.g., SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). In some embodiments, the substrate 110 may include at least one of a III-V group material and a IV group material. The III-V group material may include a binary, ternary, or quaternary compound containing at least one group III element and at least one group V element. In some embodiments, when an n-type metal oxide semiconductor (NMOS) transistor is formed on a portion of the substrate 110, the portion of the substrate 110 may include one of the above-mentioned III-V group materials. In some embodiments, when a p-type MOS (PMOS) transistor is formed on a portion of the substrate 110, the portion of the substrate 110 may include Ge. Alternatively, the substrate 110 may have a semiconductor on insulator (SOI) structure. The substrate 110 may include a conductive region (e.g., an impurity-doped well, or an impurity-doped structure).

[0019] A plurality of fin-type active areas FA may be formed on the substrate 110 by partially etching the stacked structure of the sacrificial semiconductor layer 106S and the nanosheet semiconductor layer and the substrate 110. The fin-type active area FA may protrude upward from the main surface of the substrate 110 in the vertical direction (z direction). In some embodiments, the fin-type active area FA may extend in a first horizontal direction (X direction) parallel to the upper surface of the substrate 110. In some embodiments, the fin-type active area FA may have the same width as each other in a second horizontal direction (Y direction) perpendicular to the Z direction and intersecting the first horizontal direction (X direction). It should be understood that relational terms such as "above", "below", "upward", "downward", "top", "bottom", "horizontal", "vertical", etc., as may be used throughout the specific embodiments, are intended to be defined relative to a reference system (such as, but not limited to, a substrate).

[0020] The surface of the substrate 110 in which the fin type active area FA is formed may be referred to as a front surface. Here, the top surface and the bottom surface of the substrate 110 or each other element are referred to as Figures 1A to 19B The upward facing surface and the downward facing surface in the substrate 110, and the front side and the back side thereof refer to the active surface (i.e., the surface of the substrate 110 in which the fin type active area FA is formed), and the inactive surface of the substrate 110 opposite to the active surface of the substrate 110, respectively. Figures 1A to 7C , Fig.14A , Fig. 14B , Fig.19A and Fig.19B In the embodiment, the top surface and the bottom surface of the substrate 110 may be the front side and the back side of the substrate 110, respectively. Figures 8 to 13 ,as well as Figures 15 to 18 , the top surface and the bottom surface of the substrate 110 may be the backside and the frontside of the substrate 110 , respectively.

[0021] A stack structure NSS of a sacrificial semiconductor layer 106S and a plurality of nanosheets N1, N2, and N3 may be formed on each fin type active region FA. The stack structure NSS of the nanosheets N1, N2, and N3 may be formed by partially etching the nanosheet semiconductor layer. Figures 1A to 1C Three nanosheets N1, N2, and N3 are shown in FIG. 1 , but embodiments of the inventive concept are not limited thereto.

[0022] The isolation film 120 may be formed to fill at least a portion of the space between the fin-type active regions FA. The term "fill" (or "filled with," "filled," or similar terms) as may be used herein is intended to broadly refer to completely filling a defined space (e.g., the space between the fin-type active regions FA), or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled, or have gaps or other spaces everywhere. In some embodiments, the isolation film 120 may be formed to fill the lower portion of the space between the fin-type active regions FA. The fin-type active region FA may protrude from the top surface of the isolation film 120 in the vertical direction (Z direction). For example, the isolation film 120 may be composed of a material including at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0023] refer to FIG. 2A to FIG. 2C , a plurality of dummy gate structures DGS may be formed above each fin-type active region FA on which the stack structure NSS of nanosheets N1, N2, and N3 and the sacrificial semiconductor layer 106S are formed to intersect at least a portion of each fin-type active region FA. Each dummy gate structure DGS may include a dummy insulating film D145 and a dummy gate electrode D150. The dummy gate structures DGS may extend in the second horizontal direction (Y direction) and may be parallel to each other.

[0024] A dummy insulating film D145 and a dummy gate electrode D150 may be sequentially formed to cover the exposed surface of the stacked structure NSS of nanosheets N1, N2 and N3 and the sacrificial semiconductor layer 106S (wherein the stacked structure NSS of nanosheets N1, N2 and N3 and the sacrificial semiconductor layer 106S cover the fin-type active area FA), the exposed surface of the fin-type active area FA, and the top surface of the isolation film 120, and then patterning may be performed to form a dummy gate structure DGS. A gate spacer 155 may be formed to cover the side surface of each dummy gate structure DGS. In some embodiments, the dummy insulating film D145 may include an oxide, and the dummy gate electrode D150 may include a semiconductor material. However, the embodiment is not limited thereto. In some embodiments, the dummy insulating film D145 may include silicon oxide, and the dummy gate electrode D150 may include polysilicon. The gate spacer 155 may include, but is not limited to, silicon nitride. The gate spacer 155 may be composed of a single layer or a stacked structure of at least two layers.

[0025] refer to FIG. 3A to FIG. 3C, the stacked structure NSS of the nanosheets N1, N2, and N3 and the sacrificial semiconductor layer 106S may be partially removed to form a plurality of source / drain recesses 160RS each exposing a plurality of fin-type active regions FA between two dummy gate structures DGS adjacent to each other along the first horizontal direction (X direction). In some embodiments, in the process of forming the source / drain recesses 160RS, the upper portion of each fin-type active region FA may also be removed.

[0026] refer to FIG. 4A to FIG. 4C , a plurality of source / drain regions 160 respectively filling the source / drain recesses 160RS may be formed, for example, by epitaxially growing a semiconductor material on the exposed opposite side surfaces of the nanosheets N1, N2, and N3 and the exposed surface of the fin type active region FA. In some embodiments, when the upper portion of the fin type active region FA is removed in the process of forming the source / drain recess 160RS, the source / drain region 160 may extend through the top surface of each fin type active region FA into the interior thereof.

[0027] In some embodiments, some source / drain regions 160 may include a material different from other source / drain regions 160; that is, not all source / drain regions 160 may be formed of the same material. Some source / drain regions 160 and other source / drain regions 160 including materials different from each other may be formed by performing a separate epitaxial growth process. For example, some source / drain regions 160 may include Ge. In some embodiments, some source / drain regions 160 may have a multilayer structure of a semiconductor material including Si and a semiconductor material including Ge. For example, other source / drain regions 160 may include Si but not Ge. In some embodiments, other source / drain regions 160 may have a multilayer structure of a semiconductor material including Si and a semiconductor material such as Si or a compound semiconductor material such as SiC.

[0028] In some embodiments, the source / drain region 160 in the case of forming an NMOS transistor and the source / drain region 160 in the case of forming a PMOS transistor may include different materials from each other and may be formed by performing separate epitaxial growth processes.

[0029] After forming the source / drain regions 160, an inter-gate insulating layer 180 may be formed to cover the source / drain regions 160 and fill the space between the dummy gate structures DGS. As may be used herein, the term "covering" (or "covered with" or similar terms) is intended to broadly refer to an element, structure, or layer that is directly or via one or more other intermediate elements, structures, or layers on or above another element, structure, or layer. The inter-gate insulating layer 180 may fill the space between the dummy gate structures DGS and surround the source / drain regions 160 (i.e., extend around the source / drain regions 160). As may be used herein, the term "surrounding" (or "surrounding" or similar terms) is intended to broadly refer to an element, structure, or layer that surrounds, envelops, surrounds, or encloses another element, structure, or layer on all sides, although there may also be breaks or gaps. Thus, for example, a material layer having a void or gap therein may still "surround" another layer that it surrounds. The inter-gate insulating layer 180 may include a silicon oxide film. In some embodiments, the inter-gate insulating layer 180 may have a stack structure of at least two layers including a first layer composed of silicon nitride and a second layer composed of silicon oxide, but the embodiment is not limited thereto.

[0030] refer to FIG. 4A to FIG. 4C as well as FIG. 5A to FIG. 5C , a plurality of removal spaces RS (i.e., openings) may be formed by removing the dummy gate electrode D150 and the dummy insulating film D145 and removing the sacrificial semiconductor layer 106S remaining on the fin-type active area FA. When the dummy gate electrode D150 and the dummy insulating film D145 are removed, the sacrificial semiconductor layer 106S on the fin-type active area FA and arranged between the nanosheets N1, N2, and N3 may be exposed through the space generated by removing the dummy gate electrode D150 and the dummy insulating film D145, and thus removed. The removal space RS may be formed by removing the dummy gate electrode D150, the dummy insulating film D145, and the sacrificial semiconductor layer 106S.

[0031] refer to FIG. 6A to FIG. 6C A plurality of gate insulating films 145 may be formed on the exposed surface in the removal space RS, and a plurality of gate electrodes 150 may be formed on the gate insulating films 145 to fill at least a portion of the removal space RS. The gate electrodes 150 may extend in the second horizontal direction (Y direction) and may be parallel to each other.

[0032] Each gate insulating film 145 may include, for example, silicon oxide, a high dielectric constant (high-k) dielectric material, or a combination thereof. For example, each gate insulating film 145 may have a stacked structure of an interface layer and a high-k dielectric film. In some embodiments, the interface layer may include a low-k dielectric layer (e.g., a silicon oxide layer, a silicon oxynitride layer, or a combination thereof) having a dielectric constant of about 9 or less. In some embodiments, the interface layer may be omitted. The high-k dielectric film may include a material having a higher dielectric constant than silicon oxide. The high-k dielectric film may include a metal oxide or a metal oxynitride. For example, the high-k dielectric film may have a dielectric constant of about 10 to about 25.

[0033] The high-k dielectric film may include hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. However, the material of the high-k dielectric film is not limited to the above materials. The high-k dielectric film may be formed by using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The high-k dielectric film may have a thickness of about 10 angstroms. to about The thickness may be, but not limited to, .

[0034] Each gate electrode 150 may include a work function metal layer and a gap filling metal layer on the work function metal layer, wherein the gap filling metal layer fills the removal space RS. The work function metal layer may include at least one metal selected from the group consisting of titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er) and palladium (Pd). In some embodiments, each gate electrode 150 may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer and a gap filling metal film are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from the group consisting of Ti, tantalum (Ta), W, Ru, Nb, Mo and Hf. The gap filling metal film may include a tungsten (W) film or an aluminum (Al) film. In some embodiments, the gate electrode 150 may have a stack structure of titanium aluminum carbide (TiAlC) / titanium nitride (TiN) / W, a stack structure of TiN / tantalum nitride (TaN) / TiAlC / TiN / W, or a stack structure of TiN / TaN / TiN / TiAlC / TiN / W, but is not limited thereto.

[0035] The gate electrode 150 may include a plurality of sub-gate portions 150S formed in the space between the fin-type active area FA and the nanosheets N1, N2, and N3, and a main gate portion 150M connected to the sub-gate portions 150S and covering the nanosheet stack structure NSS including the nanosheets N1, N2, and N3. As may be used herein, the term "connected" (or "connected with," "in contact with," "in contact with," or similar terms) is intended to refer to a physical and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In some embodiments, an insulating spacer (not shown) may be formed on each opposite end of each sub-gate portion 150S, with the gate insulating film 145 between the insulating spacer and each opposite end thereof.

[0036] A plurality of gate capping layers 175 may be formed on the plurality of gate electrodes 150, respectively. The gate capping layers 175 may cover the gate electrodes 150, respectively. The gate capping layers 175 may include nitrides. In some embodiments, the top surface of each gate capping layer 175 and the top surface of the gate inter-insulating layer 180 may be at the same level as each other in the vertical direction (Z direction), and therefore coplanar with each other. For example, the gate insulating film 145, the gate electrode 150, and the gate capping layer 175 may completely fill the removal space RS. For example, the gate insulating film 145 may be formed on the surface exposed by the removal space RS. Thereafter, the gate electrode 150 may be formed to fill the removal space RS and cover the gate insulating film 145. Thereafter, the portions of the upper portion of the gate insulating film 145 and the gate electrode 150 filling the removal space RS may be removed, and then, the gate capping layer 175 may be formed to fill the upper portion of the removal space RS. A plurality of gate electrodes 150 , gate capping layers 175 , gate insulating films 145 , and gate spacers 155 , respectively corresponding to one another, may form a plurality of gate structures.

[0037] refer to 7A to 7C , a first contact plug CA may be formed to contact and electrically connect to the source / drain region 160 through at least a portion of the inter-gate insulating layer 180. A second contact plug CB may be formed to contact and electrically connect to the gate electrode 150 through the gate capping layer 175. A via power rail VPR may be formed to vertically extend into the substrate 110 through the isolation film 120. The via power rail VPR may extend into the substrate 110 through a portion of the inter-gate insulating layer 180 and the isolation film 120. A via contact VA may be formed on the via power rail VPR and electrically connected to the via power rail VPR. The via contact VA may pass through at least a portion of the inter-gate insulating layer 180.

[0038] In some embodiments, the via power rail VPR may extend into a portion of the substrate 110 where the isolation film 120 is not formed, and thus be separated from the isolation film 120. For example, the via power rail VPR may extend from the via contact VA into the substrate 110 through the inter-gate insulating layer 180 but not through the isolation film 120.

[0039] In some embodiments, each of at least some of the first contact plug CA, the second contact plug CB, the via power rail VPR, and the via contact VA may include a conductive barrier layer, and a conductive core layer covering the conductive barrier layer. The conductive barrier layer may include Ti, Ta, TiN, TaN, or a combination thereof. The conductive core layer may include Co, W, copper (Cu), Ru, Ir, Mo, or a combination thereof. However, embodiments are not limited to any specific material forming the conductive barrier layer and / or the conductive core layer.

[0040] A covering insulating layer 190 may be formed to surround the first contact plug CA, the via contact VA, and the via power rail VPR. For example, the covering insulating layer 190 may be between the first contact plug CA and the inter-gate insulating layer 180, and between the via contact VA and the inter-gate insulating layer 180. The covering insulating layer 190 may be between the via power rail VPR and each of the inter-gate insulating layer 180, the isolation film 120, and the substrate 110. In some embodiments, the covering insulating layer 190 may be formed to cover the conductive barrier layer (i.e., on or over the conductive barrier layer). For example, the conductive barrier layer may be between the conductive core layer and the covering insulating layer 190. The covering insulating layer 190 may include a nitride. For example, the covering insulating layer 190 may include silicon nitride. Although in Figure 7C , it is shown that the cover insulating layer 190 is not formed around the contact plug CB, but this is only an example, and the embodiment is not limited thereto. In some embodiments, when the gate capping layer 175 through which the second contact plug CB passes includes a material that is the same as or similar to that of the cover insulating layer 190 (e.g., nitride), the cover insulating layer 190 may not be arranged around the second contact plug CB. In some embodiments, when the gate capping layer 175 through which the second contact plug CB passes includes a material that is different from that of the cover insulating layer 190 (e.g., oxide), the cover insulating layer 190 may be formed between the second contact plug CB and the gate capping layer 175. In some embodiments, the cover insulating layer 190 may be omitted so that the first contact plug CA and the via contact VA may contact the inter-gate insulating layer 180, and the via power rail VPR may contact the inter-gate insulating layer 180, the isolation film 120, and the substrate 110.

[0041] Despite 7A to 7C, it is shown that the via contact VA is formed on the first contact plug CA and is electrically connected to the first contact plug CA, but this is only an example, and the embodiment is not limited thereto. The via contact VA may be formed on the second contact plug CB and is electrically connected to the second contact plug CB. For example, a plurality of via contacts VA may be formed so that some of the via contacts VA may be electrically connected to the first contact plug CA, and other via contacts VA may be electrically connected to the second contact plug CB. The first contact plug CA may be electrically connected to the via power rail VPR through the via contact VA. In some embodiments, the second contact plug CB may also be electrically connected to the via power rail VPR through the via contact VA. Although the following describes Fig. 7A and Figure 7B The case where the first contact plug CA is electrically connected to the via power rail VPR through the via contact portion VA is described above, but the description thereof may also be applied to the case where the second contact plug CB is electrically connected to the via power rail VPR through the via contact portion VA.

[0042] The via contact VA may be formed to extend from the top surface of the first contact plug CA to the top surface of the via power rail VPR in the second horizontal direction (Y direction). In some embodiments, at least two of the first contact plug CA, the via contact VA, and the via power rail VPR may be formed integrally. For example, the first contact plug CA may be formed integrally with the via contact VA. For example, the via contact VA may be formed integrally with the via power rail VPR. For example, the first contact plug CA, the via contact VA, and the via power rail VPR may be formed integrally.

[0043] refer to Figure 8 , you can 7A to 7C The resulting structure is rotated 180 degrees so that the substrate 110 faces upward and the via contact VA faces downward. The via contact VA and the inter-gate insulating layer 180 may be attached to a supporting substrate (not shown).

[0044] refer to Figure 8 and Fig. 9 , the upper portion of the substrate 110 may be removed. For example, the upper portion of the substrate 110 may be removed so that the via power rail VPR and the cover insulating layer 190 are not exposed. Accordingly, the cross-sectional thickness of the substrate 110 in the vertical direction (z direction) may be configured so that a portion of the substrate 110 may remain above the upper end of the via power rail VPR. In some embodiments, when the portion of the substrate 110 above the upper end of the via power rail VPR is relatively thin, the process of removing the upper portion of the substrate 110 may be skipped.

[0045] refer to Fig.10, a buffer insulating layer 210 may be formed on the top surface of the substrate 110, and a mask pattern 220 may be formed on the buffer insulating layer 210. The buffer insulating layer 210 may include an oxide, but the embodiment is not limited thereto. For example, the buffer insulating layer 210 may include silicon oxide. For example, the mask pattern 220 may include a photoresist.

[0046] The mask pattern 220 may include a mask opening PRO. The mask opening PRO may be formed above the via power rail VPR. For example, at least a portion of the mask opening PRO may overlap with at least a portion of the via power rail VPR in the vertical direction (z direction). As used herein, the term "overlap" (or "overlapping with" or similar terms) is intended to broadly refer to a first element that intersects at least a portion of a second element in the vertical direction (z direction), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first horizontal direction X and / or the second horizontal direction Y).

[0047] The mask pattern 220 may be formed such that the center CPRO of the mask opening PRO according to the top plan view is aligned with the center CVPR of the top surface of the via power rail VPR according to the top view in the vertical direction (Z direction). However, when misalignment occurs in the process of forming the mask pattern 220, the center CPRO of the mask opening PRO may be misaligned with the center CVPR of the top surface of the via power rail VPR in the vertical direction (Z direction).

[0048] refer to Fig.11 , the buffer opening 2100 may be formed by etching a portion of the buffer insulating layer 210 using the mask pattern 220 as an etching mask. The substrate 110 may be exposed at the bottom of the buffer opening 2100. For example, the buffer opening 2100 may be formed by removing a portion of the buffer insulating layer 210 through a wet etching process or a dry etching process.

[0049] In the process of forming the buffer opening 2100, a heat source HSC may be provided below the via contact VA and the inter-gate insulating layer 180. In some embodiments, the heat source HSC may include a laser or an infrared heater. For example, the heat source HSC may correspond to a laser that generates a laser having a wavelength of about 200 nanometers (nm) to about 1200nm, or an infrared heater that generates infrared light having a wavelength of about 750nm to about 1200nm. In some embodiments, the heat source HSC may correspond to a laser that generates a laser having a wavelength of about 200nm to about 800nm. The heat (e.g., laser or infrared light) generated by the heat source HSC may be absorbed by the conductive material, so that heat transfer HT may occur in the conductive material. However, the heat may not be absorbed by the insulating material but reflected by the insulating material, so that the insulating material may undergo heat reflection HR instead of heat transfer HT. For example, heat transfer HT may occur in the via contact VA including the conductive material, but may not occur in the inter-gate insulating layer 180 including the insulating material. On the contrary, heat reflection HR may occur from the inter-gate insulating layer 180. The heat transferred to the via contact VA may be transferred to the via power rail VPR connected to (ie, contacting) the via contact VA.

[0050] The heat transferred to the via power rail VPR may cause heat conduction HC in a portion of the substrate 110 adjacent to the top end of the via power rail VPR and a portion of the buffer insulating layer 210 on the portion of the substrate 110. Due to the heat conducted to the portion of the buffer insulating layer 210 adjacent to the top end of the via power rail VPR, the portion of the buffer insulating layer 210 may have a higher etching rate than other portions of the buffer insulating layer 210. Accordingly, even when the center CPRO of the mask opening PRO does not coincide with the center CVPR of the top surface of the via power rail VPR in a top plan view (i.e., is not vertically aligned) due at least in part to misalignment occurring in a process of forming the mask pattern 220, the buffer opening 2100 may be formed such that the center of the buffer opening 2100 in a top plan view is closer to the center CVPR of the top surface of the via power rail VPR than to the center CPRO of the mask opening PRO.

[0051] refer to Fig.12 , a portion of the substrate 110 may be etched through the buffer opening 2100 using the buffer insulating layer 210 as an etching mask to form a substrate recess 110BO. An upper portion of the via power rail VPR and a portion of the cap insulating layer 190 surrounding the via power rail VPR may be exposed by the substrate recess 110BO. A portion of the isolation film 120 surrounding the via power rail VPR may be exposed at the bottom of the substrate recess 110BO. For example, the substrate recess 110BO may be formed by removing a portion of the substrate 110 through a wet etching process or a dry etching process.

[0052] In the process of forming the substrate recess 110BO, a heat source HSC may be disposed below the via contact VA and the inter-gate insulating layer 180. The heat transferred to the via contact VA may be transferred to the via power rail VPR connected to the via contact VA. The heat transferred to the via power rail VPR may cause heat conduction HC in a portion of the substrate 110 adjacent to the top end of the via power rail VPR. Due to the heat conducted from the via power rail VPR to the portion of the substrate 110 adjacent to the top end of the via power rail VPR, the portion of the substrate 110 may have a higher etching rate than other portions of the substrate 110. Accordingly, even when the center CPRO of the mask opening PRO does not coincide with the center CVPR of the top surface of the via power rail VPR in a top plan view due to misalignment occurring in the process of forming the mask pattern 220, the substrate recess 110BO may be formed such that the center of the substrate recess 110BO is vertically aligned with the center CVPR of the top surface of the via power rail VPR according to the top plan view. Accordingly, the substrate recess 110BO may be formed to have a symmetrical structure in a horizontal direction (ie, X direction and / or Y direction) with respect to a center CVPR of a top surface of the via power rail VPR.

[0053] refer to Fig.13 , a portion of the cover insulating layer 190 and a portion of the isolation film 120 may be etched through the substrate recess 110BO to expose the upper portion of the via power rail VPR. A portion of the cover insulating layer 190 and a portion of the isolation film 120 may be removed through a wet etching process or a dry etching process. The substrate recess 110BO may be expanded to a space generated by the removal of a portion of the cover insulating layer 190 and a portion of the isolation film 120.

[0054] In the process of removing a portion of the cover insulating layer 190 and a portion of the isolation film 120, heat transferred to the via power rail VPR through the via contact VA may cause heat conduction HC in a portion of the cover insulating layer 190 and a portion of the isolation film 120 adjacent to the top end of the via power rail VPR. Due to the heat conducted from the via power rail VPR to a portion of the cover insulating layer 190 and a portion of the isolation film 120, each of a portion of the cover insulating layer 190 and a portion of the isolation film 120 adjacent to the top end of the via power rail VPR may have a higher etching rate than other portions. Accordingly, the substrate recess 110BO expanded by removing a portion of the cover insulating layer 190 and a portion of the isolation film 120 may be formed to have a symmetrical structure in a horizontal direction with respect to the center CVPR of the top surface of the via power rail VPR.

[0055] In some embodiments, when the via power rail VPR is formed to be separated from the isolation film 120, Fig.13The isolation film 120 through which the via power rail VPR passes can be replaced by a portion of the substrate 110, and the shape of the extended substrate recess 110BO can be similar to that of the substrate 110. Fig.13 The shapes shown in are basically the same.

[0056] Fig.14A and Fig. 14B is a cross-sectional view of an example integrated circuit device according to one or more embodiments. In detail, Fig.14A is along with Fig. 7A A cross-sectional view taken at a position corresponding to the line BB' in FIG. Fig. 14B yes Fig.14A Magnified view of region XIVB.

[0057] refer to Figures 13 to 14B , a back power rail 250 may be formed to fill the substrate recess 110BO. For example, after removing the mask pattern 220, a power rail conductive layer may be formed to fill the substrate recess 110BO and the buffer opening 2100. Thereafter, the substrate 110 may be exposed by removing a portion of the power rail conductive layer and the buffer insulating layer 210, and a back power rail 250 may be formed to fill the substrate recess 110BO. In some embodiments, the bottom surface of the back power rail 250 may be coplanar with the bottom surface of the substrate 110 at the same vertical level.

[0058] The back power rail 250 may include a back conductive barrier layer 252 and a back conductive core layer 254, the back conductive barrier layer 252 covers the exposed surface of the substrate 110 in the substrate recess 110BO and the exposed surface of the upper portion of the via power rail VPR, and the back conductive core layer 254 covers the back conductive barrier layer 252 and fills the substrate recess 110BO. In some embodiments, the back conductive barrier layer 252 may be formed to conformally cover the exposed surface of the substrate 110 in the substrate recess 110BO and the exposed surface of the upper portion of the via power rail VPR. The back conductive barrier layer 252 may include, for example, Ti, Ta, TiN, TaN, or a combination thereof, and the back conductive core layer 254 may include, for example, Co, W, Cu, Ru, iridium (Ir), Mo, or a combination thereof, although the embodiment is not limited thereto.

[0059] Thereafter, a backside wiring layer (not shown) may be formed on the substrate 110 and the backside power rail 250. The resulting structure including the backside wiring layer may be rotated 180 degrees so that the substrate 110 and the backside power rail 250 face downward, and the via contact VA and the inter-gate insulating layer 180 face upward, as shown in FIG. Fig.14A Thereafter, a front wiring layer (not shown) may be formed on the via contact VA and the inter-gate insulating layer 180 , so that the integrated circuit device 1 may be formed.

[0060] The integrated circuit device 1 may correspond to a logic semiconductor chip. For example, the integrated circuit device 1 may correspond to a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0061] Here, the logic semiconductor chip refers to a semiconductor chip that is not a memory semiconductor chip and performs a logic operation. For example, the logic semiconductor chip may include a logic unit. In some embodiments, the logic semiconductor chip may include a logic unit and a storage unit. The logic unit may be configured differently to have multiple circuit elements (e.g., transistors and registers). As an example only and not a limitation, the logic unit may constitute, for example, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delayer (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND / inverter (OAI) gate, an AND / OR (AO) gate, an AND / OR / inverter (AOI) gate, a D flip-flop, a reset flip-flop, a master-slave flip-flop or a latch. The logic unit may constitute a standard unit (e.g., a counter) that performs a desired logic function.

[0062] refer to Fig.14A and Fig. 14B as well as Fig. 7A and Figure 7C , the integrated circuit device 1 may include a substrate 110, and a plurality of gate electrodes 150 on the substrate 110. The substrate 110 may include a plurality of fin-type active regions FA on its front side. The fin-type active regions FA protrude in a vertical direction (z direction) and extend in a first horizontal direction (X direction) to be parallel to each other. The gate electrodes 150 extend in a second horizontal direction (Y direction) that crosses (i.e., intersects) the first horizontal direction (X direction) and are parallel to each other.

[0063] In some embodiments, the integrated circuit device 1 may further include a plurality of nanosheet stack structures NSS facing the top surface of the fin-type active region FA and separated from the top surface of the fin-type active region FA. For example, the integrated circuit device 1 may include a multi-gate metal oxide semiconductor field effect transistor (MOSFET) composed of the fin-type active region FA and the nanosheet stack structure NSS. The fin-type active region FA and the nanosheet stack structure NSS may be collectively referred to as a channel region. The channel region may extend in a first horizontal direction (X direction). A plurality of gate insulating films 145 may be between the channel region and the gate electrode 150.

[0064] Here, it is described Fig.14A and Fig. 14B Integrated circuit device 1 or Fig.19A and Fig.19B The integrated circuit device 1a includes a multi-gate MOSFET. However, the present invention is not limited thereto. For example, according to the teachings given herein, it will be apparent to those skilled in the art that: Fig.14A and Fig. 14B Integrated circuit device 1 or Fig.19A and Fig.19B The integrated circuit device 1a may include a single-gate MOSFET composed of a fin-type active region FA, rather than a multi-gate MOSFET composed of a fin-type active region FA and a nanosheet stack structure NSS. Fig.14A and Fig. 14B Integrated circuit device 1 or Fig.19A and Fig.19B When the integrated circuit device 1a includes a single-gate MOSFET composed of a fin-type active area FA, rather than a multi-gate MOSFET composed of a fin-type active area FA and a nanosheet stack structure NSS, the fin-type active area FA can be referred to as a channel area.

[0065] A plurality of fin-type active regions FA may be defined by an isolation film 120. The isolation film 120 may fill at least a portion of the space between the fin-type active regions FA. In some embodiments, the isolation film 120 may fill the lower portion of the space between the fin-type active regions FA so that the fin-type active regions FA may protrude from the top surface of the isolation film 120 in the vertical direction (Z direction). For example, the isolation film 120 may include at least one material selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The isolation film 120 may include a single layer including one type of insulating film, a double layer including two types of insulating films, or a multilayer including at least three types of insulating films. For example, the isolation film 120 may be composed of two different types of insulating films. For example, the isolation film 120 may be composed of a silicon oxide film and a silicon nitride film. For example, the isolation film 120 may be composed of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0066] The fin-type active region FA may include a semiconductor (e.g., Si or Ge), or a compound semiconductor (e.g., SiGe, SiC, GaAs, InAs, or InP). In some embodiments, the fin-type active region FA may include at least one material selected from the group consisting of group III-V materials and group IV materials. Group III-V materials may include binary, ternary, or quaternary compounds containing at least one group III element and at least one group V element. In some embodiments, when an NMOS transistor is formed, a plurality of fin-type active regions FA may include one of the above-mentioned group III-V materials. In some embodiments, when a PMOS transistor is formed, the fin-type active region FA may include Ge.

[0067] The plurality of nanosheet stack structures NSS may be separated from the top surface of the fin type active area FA in a vertical direction (z direction). The nanosheet stack structure NSS may include a plurality of nanosheets N1, N2, and N3 extending parallel to the top surface of the fin type active area FA.

[0068] The nanosheets N1, N2, and N3 constituting the nanosheet stacking structure NSS may be stacked in sequence in the vertical direction above the top surface of the fin-type active area FA. Although a single nanosheet stacking structure NSS is shown in the present embodiment to include three nanosheets N1, N2, and N3, the inventive concept is not limited thereto. For example, the nanosheets N1, N2, and N3 may be composed of a single material. In some embodiments, the nanosheets N1, N2, and N3 may be composed of the same material as the fin-type active area FA.

[0069] The plurality of gate electrodes 150 may be parallel to each other on the fin type active area FA and may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). The gate electrode 150 may at least partially overlap the fin type active area FA and the nanosheet stack structure NSS in a vertical direction (Z direction).

[0070] Each gate electrode 150 may cover the nanosheet stack structure NSS and surround at least some of the nanosheets N1, N2, and N3. Each gate electrode 150 may include a main gate portion 150M and a plurality of sub-gate portions 150S, the main gate portion 150M being on the top surface of the fin-type active region FA and the nanosheet stack structure NSS and the side surface of the nanosheet stack structure NSS, the plurality of sub-gate portions 150S being connected to the main gate portion 150M and being formed in the space between the fin-type active region FA and the nanosheets N1, N2, and N3 (i.e., respectively under the nanosheets N1, N2, and N3). A gate insulating film 145 may be formed between the fin-type active region FA and the gate electrode 150, between the nanosheet stack structure NSS and the gate electrode 150, and between the source / drain region 160 and the gate electrode 150. A plurality of gate capping layers 175 may be on the plurality of gate electrodes 150, respectively. The gate capping layers 175 may cover the gate electrodes 150, respectively.

[0071] A plurality of gate spacers 155 may be on the side surface of the gate electrode 150. In some embodiments, each gate spacer 155 may cover the side surface of the gate electrode 150, with the gate insulating film 145 between each gate spacer 155 and the gate electrode 150. In some embodiments, a plurality of gate spacers 155 may be on the side surfaces of the plurality of gate electrodes 150 and the side surfaces of the plurality of gate capping layers 175. Although it is shown that the topmost end of the gate electrode 150 is at the same vertical level (i.e., coplanar) as the topmost end of the gate insulating film 145, the embodiment is not limited thereto. In some embodiments, the topmost end of the gate insulating film 145 may be at a vertical level higher than the topmost end of the gate electrode 150, and may be at a vertical level that is the same as the vertical level of the topmost end of the gate capping layer 175, or at a vertical level that is lower than the vertical level of the topmost end of the gate capping layer 175.

[0072] In some embodiments, the gate spacer 155 may be on opposite side surfaces of the gate electrode 150 in the first horizontal direction (X direction) and on opposite side surfaces in the second horizontal direction (Y direction), and may completely surround the gate electrode 150 according to a top plan view. The gate electrode 150, the gate capping layer 175, the gate insulating film 145, and the gate spacer 155 may constitute a gate structure.

[0073] The gate electrode 150 may be formed by using a replacement metal gate (RMG) process. For example, a dummy insulating film D145 ( Figure 2A and Figure 2C ) and the dummy gate electrode D150 ( Figure 2A and Figure 2C After that, a gate spacer 155 may be formed to surround the dummy insulating film D145 and the dummy gate electrode D150. Thereafter, the dummy insulating film D145 and the dummy gate electrode D150 may be removed, and the gate insulating film 145 and the gate electrode 150 may be formed in the space surrounded by the gate spacer 155.

[0074] A plurality of source / drain regions 160 may be formed on the plurality of fin-type active regions FA, respectively. Each source / drain region 160 may be connected to an end of each of the nanosheets N1, N2, and N3 adjacent thereto. Each source / drain region 160 may be formed on a portion of one fin-type active region FA among the plurality of fin-type active regions FA between a pair of gate electrodes 150 adjacent to each other along the first horizontal direction (X direction). In some embodiments, each source / drain region 160 may extend through the top surface of the fin-type active region FA to the inside thereof. In some embodiments, the source / drain region 160 may extend through the top surface of the fin-type active region FA to the inside thereof, but does not extend to the bottom surface of the substrate 110.

[0075] The inter-gate insulating layer 180 may fill the spaces between the plurality of gate structures. In some embodiments, the inter-gate insulating layer 180 may fill the spaces between the gate structures and surround the plurality of source / drain regions 160 .

[0076] The first contact plug CA may be electrically connected to the source / drain region 160 through at least a portion of the inter-gate insulating layer 180. The second contact plug CB may be electrically connected to the gate electrode 150 through the gate capping layer 175. The via contact VA may be electrically connected to the first contact plug CA through at least a portion of the inter-gate insulating layer 180. The via power rail VPR may extend from the via contact VA through a portion of the inter-gate insulating layer 180 and the isolation film 120, and may be electrically connected to the back power rail 250. In some embodiments, when the via power rail VPR is arranged to be spaced apart from the isolation film 120, the via power rail VPR may extend vertically (i.e., in the Z direction) from the via contact VA through at least a portion of the inter-gate insulating layer 180 and the substrate 110, and may be electrically connected to the back power rail 250. The via power rail VPR may protrude from the space defined by the capping insulating layer 190 and partially extend into the back power rail 250. For example, the side surface and the bottom surface of the lower portion of the via power rail VPR may be in contact with the back power rail 250. The capping insulating layer 190 may surround the first contact plug CA, the via contact VA, and the via power rail VPR. The back power rail 250 may extend from the back side of the substrate 110 into the substrate 110 to be electrically connected to the via power rail VPR. In some embodiments, the back power rail 250 may extend from the bottom surface of the substrate 110 through the substrate 110 into the isolation film 120. In some embodiments, the bottom surface of the back power rail 250 and the back side of the substrate 110 may be at the same vertical level and coplanar with each other.

[0077] In some embodiments, the first contact plug CA and the second contact plug CB ( Figure 7C ) may have a tapered shape whose horizontal width decreases as the first contact plug CA and the second contact plug CB extend downward in the vertical direction (Z direction) toward the substrate 110; that is, the first contact plug CA and the second contact plug CB may be configured to have sidewalls inclined inwardly. In some embodiments, the via power rail VPR may have a tapered shape whose horizontal width decreases downward in the vertical direction (z direction). In some embodiments, the back power rail 250 may have a tapered shape whose horizontal width increases downward in the vertical direction (z direction). The back power rail 250 may have a rounded (i.e., curved or non-linear) side that protrudes outward toward the substrate 110 and the isolation film 120.

[0078] The cover insulating layer 190 may include an insulating protrusion 190P extending at the lower end of the cover insulating layer 190 and spaced apart from the via power rail VPR. The insulating protrusion 190P may have a tapered shape whose horizontal width decreases downward in the vertical direction (z direction). For example, the cover insulating layer 190 may also extend toward the bottom surface of the substrate 110 at a side of the cover insulating layer 190 opposite to the via power rail VPR (rather than the other side of the cover insulating layer 190 in contact with the via power rail VPR) so as to have an insulating protrusion 190P spaced apart from the via power rail VPR.

[0079] Since the capping insulating layer 190 is spaced apart from the via power rail VPR, the back power rail 250 may include a wedge-shaped portion 250W ( 250W ) filling a space defined between the via power rail VPR and the insulating protrusion 190P. Fig. 14B ). The tapered portion 250W of the back power rail 250 may have a tapered shape whose horizontal width decreases upward in the vertical direction (z direction).

[0080] An outer surface of the back power rail 250 (e.g., an outer surface of the tapered portion 250W of the back power rail 250) may have a first angle θ1 relative to a side surface of the via power rail VPR, and a second angle θ2 relative to an inner surface of the tapered portion 250W of the back power rail 250. The first angle θ1 may be an obtuse angle, and the second angle θ2 may be an acute angle. In some embodiments, the sum of the first angle θ1 and the second angle θ2 may be 180 degrees.

[0081] The back power rail 250 may have a symmetrical structure in a horizontal direction with respect to the center CVPR of the bottom surface of the via power rail VPR. Fig. 14B 2 shows that the back power rail 250 has a symmetrical structure in the second horizontal direction (Y direction) relative to the center CVPR of the bottom surface of the via power rail VPR, but it will be obvious to those skilled in the art based on the teachings herein that the back power rail 250 may also have a symmetrical structure in the first horizontal direction (X direction) and in a diagonal (i.e., intersecting) direction relative to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0082] According to the inventive concept, the back power rail 250 of the integrated circuit device 1 can have a symmetrical structure in the horizontal direction with respect to the center CVPR of the bottom surface of the via power rail VPR, and accordingly, the reliability of the electrical connection between the back power rail 250 and the via power rail VPR can be increased. Because the back power rail 250 of the integrated circuit device 1 includes the wedge-shaped portion 250W, the back power rail 250 can be electrically connected to the lower side surface of the via power rail VPR and the bottom surface of the via power rail VPR. Accordingly, the reliability of the electrical connection between the back power rail 250 and the via power rail VPR can be increased.

[0083] Figures 15 to 17 is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to an embodiment. Figures 15 to 17 is to be with Fig. 7A The line B-B' in the figure is rotated 180 degrees and then along Fig. 7A A cross-sectional view taken along line BB' in FIG.

[0084] refer to Fig.15 , when the heat source HSC is set to Fig. 9 While the via contact VA and the inter-gate insulating layer 180 in the resulting structure of the substrate 110 are being removed, an etching process may be performed to remove a portion of the substrate 110. The heat transferred from the heat source HSC to the via contact VA may be transferred to the via power rail VPR connected to the via contact VA. The heat transferred to the via power rail VPR may cause heat conduction HC in a portion of the substrate 110 adjacent to the top end of the via power rail VPR. Due to the heat conducted to the portion of the substrate 110 adjacent to the top end of the via power rail VPR, the portion of the substrate 110 may have a higher etching rate than other portions of the substrate 110, and thus may be removed first.

[0085] refer to Fig.16 Due to the heat conducted to the portion of the substrate 110 adjacent to the top end of the via power rail VPR, the portion of the substrate 110 may be removed so that a substrate recess 110BO may be formed. The upper portion of the via power rail VPR and a portion of the cover insulating layer 190 surrounding the via power rail VPR may be exposed by the substrate recess 110BO. The isolation film 120 may be exposed at the bottom of the substrate recess 110BO. For example, the substrate recess 110BO may be formed by removing a portion of the substrate 110 through a wet etching process or a dry etching process.

[0086] refer to Fig.17, a portion of the cover insulating layer 190 and a portion of the isolation film 120 may be etched through the substrate recess 110BO to expose the upper portion of the via power rail VPR. A portion of the cover insulating layer 190 and a portion of the isolation film 120 may be removed through a wet etching process or a dry etching process. The substrate recess 110BO may be expanded to a space generated by the removal of a portion of the cover insulating layer 190 and a portion of the isolation film 120. The substrate recess 110BO expanded by removing a portion of the cover insulating layer 190 and a portion of the isolation film 120 may be formed to have a symmetrical structure in a horizontal direction with respect to the center CVPR of the top surface of the via power rail VPR.

[0087] Afterwards, if Fig.14A and Fig. 14B As shown in , a backside power rail 250 may be formed to fill the substrate recess 110BO, so that the integrated circuit device 1 may be formed.

[0088] Fig.18 is a cross-sectional view illustrating an example method of fabricating an integrated circuit device according to one or more embodiments. Fig.18 is to be with Fig. 7A The line B-B' in the figure is rotated 180 degrees and then along Fig. 7A A cross-sectional view taken along line BB' in FIG.

[0089] refer to Fig.18 , can be Fig.13 The substrate recess 110BO in the resulting structure of the via power rail VPR is removed to remove the upper portion of the via power rail VPR. After removing the upper portion of the via power rail VPR, the top end of the via power rail VPR may be at a lower vertical level than the top end of the cover insulating layer 190; that is, the top end of the via power rail VPR may be recessed relative to the top. The substrate recess 110BO may be extended to the space created by removing the upper portion of the via power rail VPR. The extended substrate recess 110BO may include the space defined by the cover insulating layer 190.

[0090] Fig.19A and Fig.19B is a cross-sectional view of an integrated circuit device according to an embodiment. In detail, Fig.19A is along with Fig. 7A A cross-sectional view taken at a position corresponding to the line BB' in FIG. Fig.19B yes Fig.19A Magnified view of region XIXB.

[0091] refer to Figures 18 to 19B, a back power rail 250a may be formed to fill the substrate recess 110BO. For example, after removing the mask pattern 220, a power rail conductive layer may be formed to fill the substrate recess 110BO and the buffer opening 2100. Thereafter, the substrate 110 may be exposed by removing a portion of the power rail conductive layer and the buffer insulating layer 210, and a back power rail 250a may be formed to fill the substrate recess 110BO. The back power rail 250a may extend to a space defined by the cover insulating layer 190 and may be electrically connected to the via power rail VPR. The back power rail 250a may include a back conductive barrier layer 252a and a back conductive core layer 254a, the back conductive barrier layer 252a covering the exposed surface of the substrate 110 in the substrate recess 110BO and the exposed surface of the upper portion of the via power rail VPR, the back conductive core layer 254a covering the back conductive barrier layer 252a and filling the substrate recess 110BO.

[0092] Thereafter, a backside wiring layer (not shown) may be formed on the substrate 110 and the backside power rail 250a. The resulting structure including the backside wiring layer may be rotated 180 degrees so that the substrate 110 and the backside power rail 250a face downward, and the via contact VA and the inter-gate insulating layer 180 face upward. Thereafter, a frontside wiring layer (not shown) may be formed on the via contact VA and the inter-gate insulating layer 180, so that the integrated circuit device 1a may be formed.

[0093] The cover insulating layer 190 may have an insulating protrusion 190P that further extends toward the bottom surface of the substrate 110 at a side of the cover insulating layer 190 opposite to the via power rail VPR (rather than the other side of the cover insulating layer 190 that contacts the via power rail VPR). The outer surface of the back power rail 250a that contacts the insulating protrusion 190P may have a first angle θ1 relative to the side surface of the via power rail VPR. The first angle θ1 may be an obtuse angle. The back power rail 250a may have a first width W1 in the second horizontal direction (Y direction), which is the minimum width in the space defined by the cover insulating layer 190, and the back power rail 250a may have a second width W2 in the second horizontal direction (Y direction) at its topmost end, wherein the second width W2 is greater than the first width W1. In other words, the back power rail 250a may have a back concave portion 250D at a lower vertical level than the topmost end of the back power rail 250a and having a first width W1 that is a minimum width in a space defined by the capping insulating layer 190. In some embodiments, in the integrated circuit device 1a, a bottom surface of the back power rail 250a and a bottom surface of the substrate 110 may be at the same vertical level and coplanar with each other.

[0094] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: A substrate having a front side and a back side opposite to the front side and including a fin-type active area in the front side and a substrate recess in the back side; The isolation film in the substrate defines the fin-type active area; A source / drain region on the fin-type active area; a contact plug over the substrate; a backside power rail at least partially filling the substrate recess; as well as a via power rail connected to the contact plug, the via power rail extending into the isolation film and connected to the backside power rail, Wherein, a side surface of the back power rail and a side surface of the via power rail form an obtuse angle at a portion where the back power rail is connected to the via power rail.

2. The integrated circuit device according to claim 1, wherein: The back side power rail has a symmetrical structure in a horizontal direction parallel to the front side of the substrate with respect to a center of a bottom surface of the via power rail.

3. The integrated circuit device according to claim 1, wherein: The back power rail includes a curved side surface that is convex toward the substrate and the isolation film.

4. The integrated circuit device according to claim 1, wherein: The contact plug is connected to the source / drain region. 5 . The integrated circuit device of claim 1 , further comprising a via contact on the contact plug and the via power rail, the via contact connecting the contact plug to the via power rail.

6. The integrated circuit device according to claim 1, further comprising: A covering insulating layer extends around the via power rail, The covering insulating layer includes an insulating protrusion at a bottom end thereof, and the insulating protrusion is spaced apart from the via power rail.

7. The integrated circuit device according to claim 6, wherein: The back power rail includes a tapered portion that at least partially fills a space defined between the via power rail and the insulating protrusion of the cover insulating layer.

8. The integrated circuit device according to claim 7, wherein: The insulating protrusion of the cover insulating layer has a tapered shape whose horizontal width decreases as the insulating protrusion of the cover insulating layer extends vertically toward the substrate perpendicular to the front surface of the substrate, and The tapered portion of the back power rail has a tapered shape whose horizontal width decreases as the tapered portion of the back power rail extends vertically upward away from the substrate.

9. The integrated circuit device according to claim 6, wherein: The via power rail extends from a space defined by the cover insulating layer and into the back side power rail.

10. The integrated circuit device according to claim 6, wherein: The backside power rail extends into a space defined by the cover insulating layer and is connected to the via power rail.

11. An integrated circuit device comprising: A substrate having a front side and a back side opposite to the front side and including a fin-type active area in the front side and a substrate recess in the back side; The isolation film in the substrate defines the fin-type active area; A source / drain region on the fin-type active area; an inter-gate insulating layer, on the substrate and extending around the source / drain region; a contact plug extending into at least a portion of the inter-gate insulating layer and connected to the source / drain region; a backside power rail at least partially filling the substrate recess; a via power rail extending into a portion of the inter-gate insulating layer and the isolation film and connected to the backside power rail; as well as a via contact portion, on the contact plug and the via power rail, connecting the contact plug to the via power rail, wherein a side surface of the back power rail and a side surface of the via power rail form an obtuse angle at a portion where the back power rail is connected to the via power rail, and The backside power rail contacts the underside surface and the bottom surface of the via power rail.

12. The integrated circuit device according to claim 11, further comprising: A covering insulating layer extends around the via power rail, The via power rail protrudes from a space defined by the cover insulating layer and extends into the back power rail.

13. The integrated circuit device according to claim 12, wherein: The cover insulating layer includes an insulating protrusion at a bottom end thereof, the insulating protrusion being spaced apart from the via power rail and having a tapered shape having a width that decreases as the insulating protrusion extends toward the substrate in a direction parallel to the front surface of the substrate.

14. The integrated circuit device according to claim 13, wherein: The backside power rail includes a tapered portion at least partially filling a space defined between the via power rail and the insulating protrusion of the cover insulating layer, the tapered portion being configured to have a tapered shape whose horizontal width decreases as the tapered portion extends upward away from the substrate.

15. The integrated circuit device according to claim 11, wherein: The via power rail has a tapered shape whose horizontal width decreases as the via power rail extends downward toward the substrate, and the back power rail has a tapered shape whose horizontal width increases as the back power rail extends downward toward the substrate.

16. The integrated circuit device according to claim 11, wherein: The back side power rail has a symmetrical structure in a horizontal direction with respect to a center of a bottom surface of the via power rail, and includes a curved side surface convex toward the substrate and the isolation film.

17. The integrated circuit device according to claim 11, wherein: The back side of the substrate and a bottom surface of the back side power rail are coplanar with each other in a vertical direction.

18. An integrated circuit device comprising: a substrate having a front side and a back side opposite to the front side, and comprising a fin-type active region in the front side and a substrate recess in the back side, the fin-type active region extending in a first horizontal direction parallel to the front side of the substrate; The isolation film in the substrate defines the fin-type active area; a backside power rail at least partially filling the substrate recess and including a rounded side surface convex toward the substrate and the isolation membrane; a plurality of gate electrodes on the fin-type active region and extending parallel to each other in a second horizontal direction, wherein the second horizontal direction is parallel to the front surface of the substrate and intersects the first horizontal direction; a source / drain region on the fin-type active region and between a pair of gate electrodes adjacent to each other in the first horizontal direction among the plurality of gate electrodes; an inter-gate insulating layer, at least partially filling the spaces between the plurality of gate electrodes and extending around the source / drain regions; a contact plug extending into at least a portion of the inter-gate insulating layer and connected to the source / drain region; a via power rail extending into a portion of the inter-gate insulating layer and the isolation film and connected to the backside power rail; a covering insulating layer extending around the via power rail; as well as a via contact portion on the contact plug and the via power rail and connecting the contact plug to the via power rail, wherein a side surface of the back power rail and a side surface of the via power rail form an obtuse angle at a portion where the back power rail is connected to the via power rail, and The back side power rail includes a tapered portion extending between the via power rail and the cover insulating layer, and has a symmetrical structure in the first horizontal direction and / or the second horizontal direction with respect to a center of a bottom surface of the via power rail.

19. The integrated circuit device according to claim 18, wherein: The via power rail protrudes from a space defined by the cover insulating layer and extends into the back power rail, and The backside power rail contacts the lower side surface and the bottom surface of the via power rail.

20. The integrated circuit device according to claim 18, wherein: The cover insulating layer includes an insulating protrusion at a bottom end thereof, the insulating protrusion being spaced apart from the via power rail and having a tapered shape whose horizontal width decreases as the insulating protrusion extends downward toward the substrate, and The tapered portion at least partially fills a space defined between the via power rail and the insulating protrusion of the cover insulating layer, and has a tapered shape whose horizontal width decreases as the tapered portion extends upward away from the substrate.

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