Method for manufacturing semiconductor device and vertically stacked semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device, which can be applied to the technical field of semiconductors. The manufacturing method includes: disposing a lower field effect transistor and an upper field effect transistor on a substrate, the lower field effect transistor and the upper field effect transistor being stacked in a vertical direction; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer; forming a full silicide layer on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer; patterning the full silicide layer to form an opening which exposes the lower surface of the lowermost gate stack in the lower field effect transistor, and forming silicide layer patterns which are arranged on the two sides of the opening in the first direction and are connected with the lower surface of a source / drain layer in the lower field effect transistor at the same time; filling a dielectric material in the opening so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; a contact hole is provided in contact with the silicification layer pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a vertically stacked semiconductor device. Background Art

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FET (Nano-SheetGate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at 3 nm and below nodes. Furthermore, three-dimensional stacked transistors will become the main technical route after the 1nm node. Among them, three-dimensional stacked transistors include three-dimensional stacked integrated transistors and VFET (Vertical Field-Effect Transistor, vertical channel field effect transistor). Among them, the three-dimensional stacked integrated transistor is 3DS FET, or CFET (Complementary FieldEffect Transistor).

[0003] The main process methods for realizing 3DS FET include two categories: one is sequential integration, and the other is self-aligned same-time (or single-time) integration. The former process method is simple, but it is limited by performance and resources; the latter process method has high integration and superior performance, but this method is complex and has many process technology challenges. Summary of the invention

[0004] In view of this, the present disclosure provides a method of manufacturing a semiconductor device and a vertically stacked semiconductor device.

[0005] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: arranging a lower field effect transistor and an upper field effect transistor stacked in a vertical direction on a substrate, and a device isolation layer between the lower field effect transistor and the upper field effect transistor, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked and spaced apart from each other in the vertical direction; a source / drain layer connected to the channel layers on both sides of the plurality of channel layers in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; the upper surface of the substrate is connected to the lower surface of the lowest gate stack in the lower field effect transistor and the lower surface of the source / drain layer; etching the substrate , thereby exposing the lower surface of the lowest gate stack and the lower surface of the source / drain layer in the lower field effect transistor; forming a fully silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor; composing the fully silicide layer to remove the fully silicide layer located on the lower surface of the lowest gate stack in the lower field effect transistor, thereby forming an opening exposing the lower surface of the lowest gate stack in the lower field effect transistor, and at the same time forming a silicide layer pattern connected to the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in the first direction; filling the opening with a dielectric material, thereby using the dielectric material filled in the opening as a lower isolation layer of the gate stack; and providing a contact hole connected to the silicide layer pattern.

[0006] According to an embodiment of the present disclosure, a full silicide layer is formed on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor, including: inverting the lower field effect transistor and the upper field effect transistor so that the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor face upward; depositing a silicon layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor facing upward; and utilizing a metal to perform a silicidation reaction on the silicon layer to form a full silicide layer.

[0007] According to an embodiment of the present disclosure, the metal includes at least one of Ti, Ni, Co, W, Pt, Al, Cu, and Ru.

[0008] According to an embodiment of the present disclosure, patterning the full silicide layer includes etching the full silicide layer along a second direction according to the width of the gate stack surrounding the channel layer in a first direction to form an opening and silicide patterns distributed on both sides of the opening.

[0009] According to an embodiment of the present disclosure, the above-mentioned method for manufacturing a semiconductor device also includes: forming a dielectric layer surrounding a lower field effect transistor and an upper field effect transistor; etching the dielectric layer from above to form a source / drain layer opening exposing the upper surface of the source / drain layer of the upper field effect transistor, wherein the projection surface of the source / drain layer opening in the vertical direction protrudes in a second direction from the projection surface of the source / drain layer of the upper field effect transistor in the vertical direction; filling the source / drain layer opening with a conductive material, and sealing the filled source / drain layer opening with a dielectric material; etching the dielectric layer from below according to the portion of the projection surface of the source / drain layer opening protruding from the projection surface of the source / drain layer of the upper field effect transistor to form an opening exposing the lower surface of the conductive material; filling the opening exposing the lower surface of the conductive material with a conductive material, thereby forming a contact hole connected to the source / drain layer of the upper field effect transistor.

[0010] According to an embodiment of the present disclosure, the contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to the ground terminal; or the contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to the bit line terminal.

[0011] According to an embodiment of the present disclosure, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction are arranged on a substrate, and an inter-device isolation layer between the lower field effect transistor and the upper field effect transistor, comprising: sequentially arranging a lower stacked structure, an intermediate layer, and an upper stacked structure on the substrate, wherein the upper stacked structure and the lower stacked structure each include an alternately arranged channel layer and a sacrificial layer; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure together with the upper portion of the substrate to form a fin extending in a first direction; forming a sacrificial layer extending in a second direction on the substrate so as to intersect with the fin; The invention relates to a method for manufacturing a sacrificial gate; forming a gate sidewall on the sidewall of the sacrificial gate; using the sacrificial gate and the gate sidewall as masks, patterning the lower stacked structure, the middle layer and the upper stacked structure, so that the patterned lower stacked structure, the middle layer and the upper stacked structure have side surfaces exposed in a first direction; replacing the middle layer with an isolation layer between devices; forming a source / drain layer of a lower field effect transistor connected to the exposed side surface of the channel layer in the lower stacked structure and a source / drain layer of an upper field effect transistor connected to the exposed side surface of the channel layer in the upper stacked structure; and replacing the sacrificial gate and the sacrificial layer with a gate stack.

[0012] According to another aspect of the present disclosure, a vertically stacked semiconductor device is provided, comprising: a lower field effect transistor and an upper field effect transistor stacked in a vertical direction; an inter-device isolation layer between the lower field effect transistor and the upper field effect transistor; and a full silicide layer and a lower isolation layer alternately arranged on the lower surface of the lower field effect transistor; wherein the lower field effect transistor and the upper field effect transistor each comprise: a plurality of channel layers stacked spaced apart from each other in a vertical direction; a source / drain layer connected to the channel layers on both sides of the plurality of channel layers in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; wherein the lower surface of the lowest gate stack in the lower field effect transistor is covered by the lower isolation layer; the lower surface of the source / drain layer of the lower field effect transistor is covered by the upper surface of the silicide pattern, and the lower surface of the silicide pattern is connected to the contact hole.

[0013] According to an embodiment of the present disclosure, a contact hole connected to the lower surface of the silicide pattern is electrically connected to the power supply terminal; a contact hole connected to the upper surface of the source / drain layer of the upper field effect transistor extends downward from one side of the upper field effect transistor to facilitate electrical connection with the bit line terminal or the ground terminal from the back side of the vertically stacked semiconductor device.

[0014] According to an embodiment of the present disclosure, the thickness of the silicide pattern ranges from 5 to 500 nm.

[0015] According to an embodiment of the present disclosure, the present disclosure discloses a method for manufacturing a vertically stacked semiconductor device, by etching the substrate, thereby exposing the lower surface of the lowest gate stack and the lower surface of the source / drain layer in the lower field effect transistor, and then forming a full silicide layer covering the entire lower surface of the device at one time on the lower surface of the gate stack exposed in the lower field effect transistor and the lower surface of the source / drain layer exposed. Then the full silicide layer is patterned to remove the full silicide layer located on the lower surface of the lowest gate stack in the lower field effect transistor, thereby forming an opening that exposes the lower surface of the lowest gate stack in the lower field effect transistor, and at the same time forming a silicide layer pattern that is connected to the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in the first direction. Thus, a silicide layer pattern connected to the source / drain layer is formed in a self-aligned manner, avoiding the lithography overlay tolerance. In addition, since the source / drain layer in the lower field effect transistor is electrically connected to the contact hole through the silicide layer pattern, the metal area and volume of the source / drain contact can be expanded through the silicide layer pattern.

[0016] Furthermore, by filling the openings between the silicide layer patterns with dielectric material to form a lower isolation layer, self-aligned dielectric isolation under the gate is achieved, which can effectively remove the parasitic silicon channel on the back of the nanosheet channel caused by the substrate, thereby avoiding additional leakage. Therefore, the method for manufacturing a vertically stacked semiconductor device disclosed in the present invention has a simple manufacturing process and the semiconductor device obtained has good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0018] Figure 1 The diagram schematically shows a development process of an integrated circuit according to an embodiment of the present disclosure.

[0019] Figure 2 A schematic diagram schematically shows an evolution path of an integrated circuit core transistor structure according to an embodiment of the present disclosure.

[0020] Figure 3 The schematic diagram of the sequential integration process according to the embodiment of the present disclosure is schematically shown.

[0021] Figure 4 The diagram schematically shows a self-aligned same-time integration process according to an embodiment of the present disclosure.

[0022] Figure 5 The flowchart schematically shows a method for manufacturing a vertically stacked semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 6 The schematic diagram of a SRAM integrated circuit according to an embodiment of the present disclosure is schematically shown.

[0024] Figure 7 A schematic diagram of a single-layer SRAM structure according to an embodiment of the present disclosure is schematically shown.

[0025] Fig. 8A The schematic diagram of the layer structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0026] Figure 8B The diagram schematically shows a top structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 8C The diagram schematically shows a bottom layer structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure.

[0028] Fig.8D The diagram schematically shows a backside contact in a vertically stacked semiconductor device according to an embodiment of the present disclosure.

[0029] Fig. 9A The schematic diagram schematically shows an axial direction of a vertically stacked semiconductor device extending along a first direction according to an embodiment of the present disclosure.

[0030] Fig. 9B The schematic diagram schematically shows an axial direction of a vertically stacked semiconductor device extending along a second direction according to an embodiment of the present disclosure.

[0031] Figure 10A to Figure 10E Schematic diagrams of various axial directions of the layer structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0032] Figure 11A to Figure 49A , Figure 11B to Figure 49B , Fig.41C , Fig.41D , Fig.48C , Fig.48D , Fig.49C and Fig.49D A schematic cross-sectional view along the axial direction of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0033] Figure 46A' to Figure 49A' , Figure 46B'~Figure 49B' , Figure 48C' , Figure 48D' , Figure 49C' and Fig.49D' The cross-sectional view of a semiconductor device in the related art along the axial direction is schematically shown.

[0034] Fig.50 The schematic diagram of the structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0035] Fig.51 The schematic diagram of the SRAM structure implemented based on vertically stacked semiconductor devices according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0037] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0038] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0039] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0040] In the embodiment of the present disclosure, Figure 1 The technology development route shown is used as an example to demonstrate the development process of integrated circuits. Figure 1 In this paper, Tech Node refers to the semiconductor process node, which can be used to indicate the critical dimension that can be achieved by the process of integrated circuits. Figure 1 From the technology development route shown, it can be seen that the manufacturing processes of integrated circuits are sorted in descending order according to the size represented by the semiconductor process node, namely Planar 11A (i.e., planar transistor structure), Fin FET 11B, NS-GAA FET 11C, VFET 11D and StackedFET 11E. Among them, the sizes represented by the Tech Node 12A of Planar 11A are 90, 65, 45, 32, 28 and 20 from high to low, in nm; the sizes represented by the Tech Node 12B of Fin FET 11B are 14, 10, 7, 5 and 4 from high to low, in nm; the sizes represented by the Tech Node 12C of NS-GAA FET 11C are 3 and 2 from high to low, in nm; the sizes represented by the Tech Node 12D of VFET 11D and Stacked FET 11E are 1 and 0.7 from high to low, in nm.

[0041] Furthermore, if Figure 2As shown, in the evolution path of the core transistor structure of the integrated circuit, it will develop from Fin FET 201 to NS-GAA FET 202, Forksheet 203, and further to the three-dimensional stacked integrated transistor in a single chip, namely 3DS FET or CFET (Complementary Field Effect Transistor) 204, to obtain higher integration density and overall performance.

[0042] like Figure 3 and Figure 4 As shown, the main process methods for realizing 3DS FET include two categories: one is sequential integration process (Sequential 3D), and the other is self-aligned monolithic integration process (Monolithic 3D). Taking two transistors stacked up and down as an example, when the two transistors are made by sequential integration process, the channel materials of the two transistors can be different from each other; when the two transistors are made by self-aligned monolithic integration process, the channel materials of the two transistors can be the same. For example, the operation of the sequential integration process may include: bonding the substrate 301 to the upper part of the bottom device 302 to obtain the middle device 303; based on the bonded substrate in the middle device, manufacturing the top device, thereby obtaining the integrated circuit 304. The self-aligned monolithic process may include growing a polysilicon layer 402 surrounding multiple channel layers directly on the fin structure 401, and then processing it to obtain the integrated circuit 403.

[0043] Based on this, the sequential integration process method is simple, but will be limited by performance and resources; the latter self-aligned same-order integration process method has high integration and superior performance, but this method is complex and has many process technology challenges.

[0044] Specifically, the advantages of sequential integration include: flexible architecture design, channel materials can be adjusted as needed, flexible connection settings between transistors, etc. The disadvantages of sequential integration are mainly reflected in: high resource consumption, limitations of the manufacturing process, bonding, isolation space between NPs, thermal budget and lithography alignment.

[0045] The advantages of the self-aligned same-order integration process include: low resource consumption, precise process control, such as self-aligned top and bottom devices, and narrow isolation space between NPs, etc. The disadvantages are mainly reflected in: high process difficulty, such as processes with high aspect ratios and interconnections between devices, etc.

[0046] On this basis, the present disclosure provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device to obtain a highly integrated CFET semiconductor device through a simple process, including: a lower field effect transistor and an upper field effect transistor stacked in a vertical direction arranged on a substrate, and an inter-device isolation layer between the lower field effect transistor and the upper field effect transistor, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked spaced apart from each other in the vertical direction. A source / drain layer connected to the channel layer on both sides of the plurality of channel layers in a first direction. A gate stack extending in a second direction intersecting the first direction and surrounding the channel layer. The upper surface of the substrate is connected to the lower surface of the lowest gate stack and the lower surface of the source / drain layer in the lower field effect transistor. The substrate is etched to expose the lower surface of the lowest gate stack and the lower surface of the source / drain layer in the lower field effect transistor. A fully silicided layer is formed on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor. The fully silicided layer is patterned to remove the fully silicided layer located on the lower surface of the lowest gate stack in the lower field effect transistor, thereby forming an opening that exposes the lower surface of the lowest gate stack in the lower field effect transistor, and simultaneously forming a silicided layer pattern that is connected to the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in the first direction. A dielectric material is filled in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack. A contact hole connected to the silicided layer pattern is provided.

[0047] Figure 5 The diagram schematically shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0048] like Figure 5 As shown, the method for manufacturing a semiconductor device in this embodiment includes: operations S501 to S507.

[0049] In operation S501, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction and an inter-device isolation layer between the lower field effect transistor and the upper field effect transistor are arranged on a substrate, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked and spaced apart from each other in the vertical direction; source / drain layers connected to the channel layers on both sides of the plurality of channel layers in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; and an upper surface of the substrate connected to a lower surface of the lowest gate stack and a lower surface of the source / drain layer in the lower field effect transistor.

[0050] In operation S502 , the substrate is etched to expose a lower surface of a lowermost gate stack and a lower surface of a source / drain layer in the lower field effect transistor.

[0051] In operation S503 , a full silicide layer is formed on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor.

[0052] In operation S504, the fully silicide layer is composed to remove the fully silicide layer located on the lower surface of the lowest gate stack in the lower field effect transistor, thereby forming an opening exposing the lower surface of the lowest gate stack in the lower field effect transistor, and at the same time forming a silicide layer pattern connected to the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in the first direction.

[0053] In operation S505 , a dielectric material is filled in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack.

[0054] In operation S506, a contact hole connected to the silicide layer pattern is provided.

[0055] According to an embodiment of the present disclosure, the vertically stacked semiconductor device obtained by the manufacturing method of the present disclosure can be used to implement an SRAM structure (Static Random-Access Memory). For example, a first group of field effect transistors and a second group of field effect transistors arranged in a second direction and spaced apart from each other can be provided. The first group of field effect transistors and the second group of field effect transistors each include two vertically stacked semiconductor devices. Each vertically stacked semiconductor device may include vertically stacked field effect transistors. On this basis, based on two groups of stacked field effect transistors in the first group of field effect transistors and two groups of stacked field effect transistors in the second group of field effect transistors, the above-mentioned SRAM structure can be implemented.

[0056] The following describes the manufacturing method of the vertical semiconductor device of the embodiment of the present disclosure by taking the realization of the SRAM structure as an example. It should be understood that the SRAM here is only an example, and those skilled in the art can realize other integrated circuit structures based on the vertical semiconductor device in the embodiment of the present disclosure as required.

[0057] like Figure 6 As shown in Figure 1, SRAM is the core unit circuit of integrated circuits, and the continuous reduction of SRAM unit area is the main line of development of integrated circuits. The use of a three-dimensional stacked structure of transistors (3DS-FET or CFET) can greatly reduce the SRAM unit area, reducing the SRAM unit area by more than 30%. Figure 7 and Fig. 8A ,contrast Figure 7 Single-layer SRAM structure and Fig. 8A From the double-layer SRAM structure, we can see that Fig. 8A The area of ​​the realized three-dimensional stacked structure (corresponding to the vertically stacked semiconductor device of the present disclosure) is smaller than Figure 7The area of ​​the two-dimensional structure in . Further, Fig. 8A The three-dimensional stacked structure in can be divided into a top structure, a bottom structure and a back contact pad, wherein the top structure can be implemented based on NMOS and the bottom structure can be implemented based on PMOS. On this basis, Figure 8B Shows Fig. 8A The underlying structure of the three-dimensional stacked structure. Figure 8C Shows Fig. 8A The top structure of the three-dimensional stacked structure. Fig.8D Shows Fig.8D It should be noted that the dimensions marked in the drawings of the present disclosure are examples and are not used to limit the actual dimensions of the vertically stacked semiconductor devices in the present disclosure.

[0058] Taking SRAM as an example, combined with Fig. 9A and Fig. 9B Various axial directions of the vertically stacked semiconductor device defined in the embodiment of the present disclosure are shown. Figures 10A to 10E An example is shown Fig. 8A The axial directions of the layer structure of the vertically stacked semiconductor device for realizing SRAM are shown in FIG. XX' axial direction extends along the first direction. Y1-Y1' axial direction, Y2-Y2' axial direction, Y3-Y3' axial direction, and Y4-Y4' axial direction extend along the second direction.

[0059] The following is a cross-sectional view of each axis in the process of manufacturing a vertically stacked semiconductor device, namely Figure 11A to Figure 49A , Figure 11B to Figure 49B , Fig.41C , Fig.41D , Fig.48C , Fig.48D , Fig.49C and Fig.49D , to explain the contents of the embodiments of the present disclosure. It should be noted that in the following description Figure 11A to Figure 49A , Figure 11B to Figure 49B , Fig.41C , Fig.41D , Fig.48C , Fig.48D , Fig.49C and Fig.49D In the case where the numbers in the captions of multiple drawings are the same, the manufacturing processes corresponding to the multiple drawings are the same. In the case where the numbers in the captions of multiple drawings are the same but the letters are different, the manufacturing processes corresponding to the multiple drawings are the same, and the axes corresponding to the multiple drawings are different. For example, Fig.11A and Fig. 11B They are cross-sectional views of two axes in the same manufacturing process.

[0060] According to an embodiment of the present disclosure, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction are arranged on a substrate SUB, and an inter-device isolation layer 114 between the lower field effect transistor and the upper field effect transistor includes: a lower stacked structure, an intermediate layer 103 and an upper stacked structure are sequentially arranged on the substrate SUB, and the upper stacked structure and the lower stacked structure each include a channel layer 101 and a sacrificial layer 102 arranged alternately. The lower stacked structure, the intermediate layer and the upper stacked structure are patterned together with the upper part of the substrate SUB to form a fin extending in a first direction. A sacrificial gate extending in a second direction and intersecting with the fin is formed on the substrate. A gate spacer 110 is formed on the sidewall of the sacrificial gate. Using the sacrificial gate and the gate spacer 110 as a mask, the lower stacked structure, the intermediate layer 103 and the upper stacked structure are patterned, so that the patterned lower stacked structure, the intermediate layer 103 and the upper stacked structure have side surfaces exposed in the first direction. The intermediate layer 103 is replaced with an inter-device isolation layer 114. A source / drain layer 117 of a lower field effect transistor connected to the exposed side surface of the channel layer 101 in the lower stacked structure and a source / drain layer 119 of an upper field effect transistor connected to the exposed side surface of the channel layer 101 in the upper stacked structure are formed. And the sacrificial gate and sacrificial layer 102 are replaced with a gate stack.

[0061] Specifically, taking a group of stacked field effect transistors as an example, Figure 11A to Figure 12A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 11B to Figure 12B It is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 11A to Figure 12A ,as well as Figure 11B to Figure 12B , the material of the substrate SUB may include silicon, etc. The substrate SUB may be subjected to pretreatment operations such as well lithography, ion implantation, annealing and cleaning in sequence. Then, a lower stacked structure, an intermediate layer 103 and an upper stacked structure are sequentially arranged on the pretreated substrate SUB using an epitaxial growth process. The lower stacked structure and the upper stacked structure each include an alternating channel layer 101 and a sacrificial layer 102. Among them, the material of the sacrificial layer 102 and the intermediate layer 103 may be consistent, such as SiGe or Si, etc. The material of the channel layer 101 may be doped silicon, etc. The channel layer 101 located above the intermediate layer 103 and the channel layer 101 located below the intermediate layer 103 may have the same doping elements or different doping elements.

[0062] In the first embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 may be p-type doped silicon; the material of the channel layer 101 located below the middle layer 103 may be n-type doped silicon. In the second embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 may be n-type doped silicon; the material of the channel layer 101 located below the middle layer 103 may be p-type doped silicon. In the third embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 and the material of the channel layer 101 located below the middle layer 103 may both be n-type doped silicon or both be p-type doped silicon.

[0063] Figure 13A to Figure 15A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 13B to Figure 15B It is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 13A to Figure 15A ,as well as Figure 13B to Figure 15B . The sidewall 104 can be formed by a sidewall transfer (SIT) process. The material of the sidewall 104 can be silicon nitride or the like. In the embodiment of the present disclosure, a core mold 105 can be formed on the upper stacked structure, and the core mold 105 can be patterned by a photolithography process to obtain a linear pattern extending along the X direction. Among them, the material of the core mold 105 can be polycrystalline silicon or amorphous silicon or the like. The sidewall 104 is formed in the above-mentioned area, and the patterned core mold 105 is removed after the sidewall 104 is formed, so that only the sidewall 104 remains on the stacked structure, thereby completing the manufacture of the sidewall 104. On this basis, the upper stacked structure, the middle layer 103, the lower stacked structure and the substrate SUB can be etched using an anisotropic etching process according to the pattern of the sidewall 104 to form a fin located on the substrate SUB and a substrate etching area distributed on both sides of the fin along the first direction. In the substrate etching area, a dielectric material 106 is deposited, and the dielectric material 106 is etched back to a level lower than or equal to the upper surface of the lower fin formed by the substrate SUB, so that the dielectric material 106 is used as a shallow trench isolation member. The dielectric material in the embodiment of the present disclosure may include silicon dioxide or silicon nitride.

[0064] Figure 16A to Figure 20A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 16B to Figure 20B It is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 16A to Figure 20A ,as well as Figure 16B to Figure 20B The sacrificial gate across the fin can be formed on the dielectric material 106 by using processes such as thermal oxidation, chemical vapor deposition or sputtering. The sacrificial gate includes a gate oxide layer 107, a silicon layer 108 and a mask layer 109 from bottom to top, wherein the material of the gate oxide layer 107 can be SiO 2etc. The material of the silicon layer 108 is amorphous silicon or polycrystalline silicon. The material of the hard mask layer 109 may be oxide, carbide or organic matter, etc. On this basis, a gate sidewall 110 may be formed on the sidewall of the sacrificial gate by a sidewall formation process. The material of the sidewall may be SiCNO, etc. The upper stacked structure, the middle layer and the lower stacked structure may be etched according to the pattern of the sacrificial gate and the gate sidewall 110, thereby exposing the sidewalls of the upper stacked structure, the middle layer and the lower stacked structure. The middle layer 103 and the sacrificial layer 102 may be set to have different etching selectivities, whereby the middle layer 103 may be etched at a faster rate than the sacrificial layer 102. After the middle layer 103 is etched, an opening 112 is formed. The end of the sacrificial layer 102 in the first direction is recessed relative to the channel layer 101 to form an opening 111. Based on this, a dielectric material may be filled in the space released in the fin due to the selective etching of the sacrificial layer 102 and the middle layer 103. The portion of the dielectric material filled at the end of the sacrificial layer 102 is used as the inner sidewall 113, and the portion of the dielectric material filled between the lower stacked structure and the upper stacked structure is used as the device isolation layer 114. Thus, the inner sidewall 113 and the device isolation layer 114 are manufactured at the same time, reducing the steps of the manufacturing process. In addition, the inner sidewalls 113 of the first field effect transistor and the second field effect transistor manufactured by the above method have substantially aligned outer surfaces. Since the inner sidewall 113 in the upper stacked structure and the outer surface of the inner sidewall 113 in the lower stacked structure are substantially aligned in the vertical direction, the area of ​​the horizontal cross section of the upper source / drain layer 119 of the vertically stacked semiconductor device disclosed in the present invention is equal to the area of ​​the horizontal cross section of the lower source / drain layer 117, avoiding the unfavorable result of the side misalignment of the upper field effect transistor and the lower field effect transistor in the stacked field effect transistor caused by the inner sidewall 113 and the device isolation layer 114 being manufactured separately.

[0065] Figure 21A to Figure 27A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 21B to Figure 27B It is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 21A to Figure 27A ,as well as Figure 21B to Figure 27B, a lower source / drain position defining layer 115 in contact with the channel layer 101 is formed on both sides of the channel layer 101 located under the inter-device isolation layer 114, and a sidewall 116 is formed on the lower source / drain position defining layer 115 using a sidewall formation process. The material of the lower source / drain position defining layer 115 may include but is not limited to aC (amorphous carbon). The method for forming the lower source / drain position defining layer 115 includes but is not limited to spin coating. For example, after depositing aC, the deposited aC can be planarized and the aC can be etched back to a position not higher than the middle of the inter-device isolation layer 114. The material of the sidewall 116 includes but is not limited to SiN x The sidewall 116 is used to protect the channel layer 101 located on the upper part of the isolation layer between devices, so as to prevent the source / drain from growing at both ends of the channel layer 101 of the upper device during the source / drain growth of the lower device. When the upper and lower devices are of different types, the source / drain materials of the upper and lower devices can be different.

[0066] After forming the sidewall 116, the lower source / drain position defining layer 115 is removed to expose the sidewall of the channel layer 101 located below the device isolation layer 114, and on the exposed sidewall of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, thereby forming a source / drain layer 117 connected to the lower stacked structure. Among them, the source / drain material can be SiGe or Si. A dielectric material 118 can be deposited on the source / drain layer 117, and the dielectric material 118 can be etched to a position not higher than the device isolation layer 114 so as to electrically isolate the source / drain layers of the upper and lower devices. The sidewall 116 can be selectively etched to expose the sidewall of the channel layer 101 located above the device isolation layer 114. On the exposed sidewall of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, thereby forming a source / drain layer 119 connected to the upper stacked structure. On this basis, the source / drain layer 117 and the source / drain layer 119 are source / drain activated, thereby activating the source / drain layer 117 and the source / drain layer 119 .

[0067] Figure 28A to Figure 37A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 28B to Figure 37B It is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 28A to Figure 37A ,as well as Figure 28B to Figure 37B , a dielectric material 120 is formed on the substrate SUB and the dielectric material 120 is planarized. The planarization can remove the mask layer 109 in the sacrificial gate and expose the silicon layer 108. Then, the silicon layer 108 and the sacrificial layer 102 are etched back by an etch-back process, so that a cavity 121_1 exposed by etching is formed at the original position of the silicon layer 108 on the inner side of the sidewall 110 and the inner sidewall 113, and a cavity 121_2 exposed by etching is formed at the original position of the sacrificial layer 102.

[0068] A gate stack surrounding the channel layer 101 is sequentially formed on the inner sidewalls of the cavity 121_1 and the cavity 121_2. The gate stack includes a gate dielectric layer 122 and a P-type work function layer 123. The material of the gate dielectric layer 122 may be a high-k dielectric material, where K represents a dielectric constant. High-k dielectric materials include HfO2, HfSiOx, HfON, HfSiON, HfAlO x 、HfLaO x 、Al 2 O 3 、ZrO 2 、ZrSiO x 、 2 O 5 or La 2 O 3 The material of the P-type work function layer 123 may be titanium nitride or the like. A protective layer 124 is formed on the substrate SUB, and the protective layer 124 is etched until the top surface is located between the top surface and the bottom surface of the inter-device isolation layer 114 to shield the cavity for the lower layer device, so that the protective layer 124 protects the P-type work function layer 123 located in the cavity below the inter-device isolation layer 114, while exposing the P-type work function layer 123 located in the cavity above the inter-device isolation layer 114.

[0069] The P-type work function layer 123 located above the inter-device isolation layer 114 is etched by using a selective etching process, while the gate dielectric layer 122 located above the inter-device isolation layer 114 is retained. Then, an N-type work function layer 125 is formed around the gate dielectric layer 122 located above the inter-device isolation layer 114. Thus, different gate stacks surrounding the channel layer 101 are formed above and below the inter-device isolation layer 114, respectively. Thus, the channel layer 101, the gate stack, and the source / drain layer 119 located above the inter-device isolation layer constitute an N-type field effect transistor, and the channel layer 101, the gate stack, and the source / drain layer 117 located above the inter-device isolation layer constitute a P-type field effect transistor, thereby obtaining a stacked field effect transistor.

[0070] It should be understood that the above is only one embodiment of the present disclosure, and in the manufacturing process of other embodiments of the present disclosure, an N-type field effect transistor or a P-type field effect transistor can be formed as needed by changing the doping type of the source / drain layer and forming a corresponding type of work function layer. For example, the N-type field effect transistor of the upper layer can be formed as a P-type field effect transistor, and / or the P-type field effect transistor of the lower layer can be formed as an N-type field effect transistor.

[0071] After manufacturing the above-mentioned N-type field effect transistor and P-type field effect transistor, the protective layer 124 is removed to release the cavity below the inter-device isolation layer 114. Then, a conductive material is deposited in all the cavities 121_1 and all the cavities 121_2 to form a conductive layer 126, thereby completing the manufacture of the gate structure. The conductive material in the embodiment of the present disclosure may include tungsten and the like. After forming the conductive layer 126, the conductive layer 126 may be planarized, and a dielectric material may be deposited on the planarized conductive layer 126. On this basis, a contact hole 127 connected to the source / drain layer 119 may be formed in the dielectric material 120.

[0072] Specifically, taking the four field effect transistors in the first group of field effect transistors and the four field effect transistors in the second group of field effect transistors as an example, Figure 38A to Figure 41A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 38B~Figure 41B It is a cross-sectional view along the Y3 -Y3 'axis during the process of manufacturing a vertically stacked semiconductor device. Fig.41C It is a cross-sectional view along the Y1 -Y1 'axis during the process of manufacturing a vertically stacked semiconductor device. Fig.41D It is a cross-sectional view along the Y2 -Y2 'axis during the process of manufacturing a vertically stacked semiconductor device.

[0073] On this basis, Figure 38A to Figure 41A , Figure 38B~Figure 41B , Fig.41C and Fig.41DA schematic cross-sectional view of a structure in which the above-mentioned eight field effect transistors are integrated is shown. On the upper surface of the dielectric material 120, the dielectric material 120 is etched until the source / drain layer 119 is exposed, thereby forming openings 128_1, 128_2, and 128_3 located in the dielectric material 120. Among them, the opening 128_2 includes an opening 128_21 corresponding to the first group of field effect transistors and an opening 128_22 corresponding to the second group of field effect transistors. On this basis, taking the opening 128_2 as an example, according to the position of the source / drain layer 117 as a common layer, the opening 128_2 is further etched, so that the opening 128_2 exposes the source / drain layer 119 and the source / drain layer 117 at the same time. Conductive material is filled in the openings 128_1, 128_2, and 128_3, thereby forming contact holes 127_1, 127_2, and 127_3. The contact hole 127_2 includes a contact hole 127_21 formed by filling the opening 128_21 and a contact hole 127_22 formed by filling the opening 128_22. In a similar manner, the contact hole 127_1 may be formed. The contact hole 127_1 includes a contact hole 127_11 and a contact hole 127_12. A dielectric material is deposited on the contact holes 127_1, 127_2, and 127_3. It should be noted that Fig.41D There is a structure protruding from the upper surface of the conductive layer 126 above the conductive layer 126 on the right side of the middle. The structure is used as a connection line extending in a direction perpendicular to the paper surface (corresponding to the first direction). Fig.41D The conductive layer 126 on the left side of the center extends to the left side so as to lead out the pads for connecting the word line terminals from the back side.

[0074] Figure 42A to Figure 45A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 42B~Figure 45B It is a cross-sectional view along the Y4-Y4' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 42A to Figure 45A ,as well as Figure 42B~Figure 45B It should be noted that Figure 42A to Figure 45A ,as well as Figure 42B~Figure 45BIn the figure, the stacked field effect transistors are inverted for ease of description, and the same applies to the other figures below. It should be noted that the "above" and "below" in the following are described according to the vertically stacked semiconductor device before inversion. After the field effect transistor is inverted, another substrate USUB can be bonded above the stacked field effect transistor, and the material of the substrate USUB is the same as that of the above-mentioned substrate SUB. In the embodiment of the present disclosure, the first group of field effect transistors and the second group of field effect transistors each include a lower fin formed by etching the substrate SUB. The remaining part of the substrate after etching is connected between the lower fins of the first group of field effect transistors and the second group of field effect transistors. An intermediate dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate SUB is formed, including: etching a portion of the substrate from below until the lower surface of the lower fin of each of the first group of field effect transistors and the second group of field effect transistors is exposed. A dielectric material 129 is deposited on the lower surface of the lower fin of each of the first group of field effect transistors and the second group of field effect transistors. Thus, the lower fins of each of the first group of field effect transistors and the second group of field effect transistors can be electrically isolated from each other.

[0075] Specifically, a fully silicide layer Fully Silicide can be formed on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor. For example, the lower field effect transistor and the upper field effect transistor are inverted so that the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer 117 face upward. A silicon layer is deposited on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer 117 in the lower field effect transistor facing upward. A fully silicide layer Fully Silicide is formed by performing a low-temperature silicidation reaction between the metal and the silicon layer. For example, the metal includes at least one of Ti, Ni, Co, W, Pt, Al, Cu and Ru.

[0076] The fully silicide layer Fully Silicide is patterned to remove the fully silicide layer Fully Silicide located on the lower surface of the lowest gate stack in the lower field effect transistor, so that the lower surface of the lowest gate stack in the lower field effect transistor does not contact the fully silicide layer Fully Silicide, thereby forming an opening that exposes the lower surface of the lowest gate stack in the lower field effect transistor, and at the same time forming a silicide layer pattern FSP that is connected to the lower surface of the source / drain layer 117 in the lower field effect transistor on both sides of the opening in the first direction. By filling the dielectric material in the opening, the lower isolation layer 129 can be obtained. On this basis, the fully silicide layer Fully Silicide can be patterned. For example, according to the width of the gate stack surrounding the channel layer 101 in the first direction, the fully silicide layer Fully Silicide is etched along the second direction to form an opening and a silicide pattern distributed on both sides of the opening. The etching method here may include wet etching, dry etching, physical etching, and the like. The length of the opening between the two silicide layer patterns FSP in the first direction is substantially equal to the length of the gate stack surrounding the channel layer 101 in the first direction, and the opening extends along the second direction. Thus, the opening can completely expose the lower surface of the lowermost gate stack in the lower field effect transistor.

[0077] Continuing with the example of four field effect transistors in the first group of field effect transistors and four field effect transistors in the second group of field effect transistors, Figure 46A to Figure 49A It is a cross-sectional view along the XX' axis during the process of manufacturing a vertically stacked semiconductor device. Figure 46B~Figure 49B It is a cross-sectional view along the Y1 -Y1 'axis during the process of manufacturing a vertically stacked semiconductor device. Fig.48C It is a cross-sectional view along the Y2 -Y2 'axis during the process of manufacturing a vertically stacked semiconductor device. Fig.48D It is a cross-sectional view along the Y3 -Y3 'axis during the process of manufacturing a vertically stacked semiconductor device. Fig.49C It is a cross-sectional view along the Y2 -Y2 'axis during the process of manufacturing a vertically stacked semiconductor device. Fig.49D It is a cross-sectional view along the Y3 -Y3 'axis during the process of manufacturing a vertically stacked semiconductor device.

[0078] refer to Figure 46A to Figure 49A , Figure 46B~Figure 49B , Fig.48C , Fig.48D , Fig.49C and Fig.49D, the method for manufacturing a semiconductor device further includes: forming a dielectric layer surrounding the lower field effect transistor and the upper field effect transistor. Etching the dielectric layer from above to form a source / drain layer opening that exposes the upper surface of the source / drain layer 119 of the upper field effect transistor, wherein the projection surface of the source / drain layer opening in the vertical direction protrudes in the second direction from the projection surface of the source / drain layer of the upper field effect transistor in the vertical direction. Filling the source / drain layer opening with a conductive material, and sealing the filled source / drain layer opening with a dielectric material, thereby forming contact holes 127_11 and contact holes 127_12. Etching the dielectric layer from below according to the portion where the projection surface of the source / drain layer opening protrudes from the projection surface of the source / drain layer of the upper field effect transistor, to form openings 132_1 and openings 132_2 that expose the lower surface of the conductive material (i.e., the conductive material in the contact holes 127_11 and the contact holes 127_12). A conductive material is filled in the opening that exposes the lower surface of the conductive material, thereby forming a contact hole connected to the source / drain layer 119 of the upper field effect transistor. The contact hole is used to electrically connect the source / drain layer 119 of the upper field effect transistor to the ground terminal. Or the contact hole is used to electrically connect the source / drain layer 119 of the upper field effect transistor to the bit line terminal. For example, one of the contact hole 133_1 and the contact hole 133_2 can electrically connect the source / drain layer 119 of the upper field effect transistor to the ground terminal, and the other can electrically connect the source / drain layer 119 of the upper field effect transistor to the bit line terminal.

[0079] Specifically, a dielectric material is deposited on the lower layer of the substrate SUB and the dielectric material and the substrate SUB are photolithographically processed together to form an opening 131 exposing the lower surface of the silicide layer pattern FSP, and openings 132_1 and 132_2 exposing the conductive material in contact with the upper source / drain layer. Conductive material is deposited in the above openings 131, 132_1, and 132_2, so as to form a contact hole located at the back of the device through the opening 131 exposing the lower surface of the silicide layer pattern FSP, and to form an interlayer contact through hole located at the back of the device through the opening 132_1 and 132_2 exposing the conductive material in contact with the upper source / drain layer 119. The conductive material filled in the opening 131 forms a back contact hole (BSCON) 130 electrically connected to the power supply terminal. The conductive materials filled in the openings 132_1 and 132_2 respectively form back interlayer contact vias (BSVPR) 133_1 and back interlayer contact vias 133_2, which are then electrically connected to the ground terminal and the first bit line terminal, respectively. After depositing the conductive material, the conductive material exposed outside the dielectric material is planarized.

[0080] On this basis, a plurality of contact holes on the back side of the device can be formed by a back-end interconnection process. For example, the conductive material filled into the opening 134 constitutes a contact hole electrically connected to the second bit line terminal complementary to the first bit line terminal. Fig.49C The conductive layer 126 on the left side of the device is led out from the back of the device, thereby being electrically connected to the word line terminal WL at the back of the device. Figure 46A' to Figure 49A' , Figure 46B'~Figure 49B' , Figure 48C' , Figure 48D' , Figure 49C' and Fig.49D' It can be seen that in the vertically stacked semiconductor device in the related art, since the substrate SUB is not completely etched away and the silicide layer pattern FSP and the dielectric of the lower isolation layer 129 located between the silicide layer pattern FSP are not formed, the substrate SUB will contact the lower surface of the lowest gate stack in the lower field effect transistor, resulting in a parasitic silicon channel on the back of the nanosheet channel, thereby causing leakage.

[0081] Based on this, the method for manufacturing a vertically stacked semiconductor device disclosed in the present invention is to etch the substrate SUB to expose the lower surface of the lowest gate stack and the lower surface of the source / drain layer 117 in the lower field effect transistor, and then form a fully silicide layer Fully Silicide covering the entire lower surface of the device at one time on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer 117 in the lower field effect transistor. Then the fully silicide layer Fully Silicide is patterned to remove the fully silicide layer Fully Silicide located on the lower surface of the lowest gate stack in the lower field effect transistor, thereby forming an opening that exposes the lower surface of the lowest gate stack in the lower field effect transistor, and at the same time, forming a silicide layer pattern FSP that is connected to the lower surface of the source / drain layer 117 in the lower field effect transistor on both sides of the opening in the first direction. As a result, the silicide layer pattern FSP connected to the source / drain layer 117 is formed in a self-aligned manner, avoiding the lithography overlay tolerance. Furthermore, since the source / drain layer 117 in the lower field effect transistor is electrically connected to the contact hole 130 through the silicide layer pattern FSP, the metal area and volume of the source / drain contact can be expanded through the silicide layer pattern.

[0082] In addition, by filling the dielectric material in the opening between the above-mentioned silicide layer patterns FSP to form a lower isolation layer 129, self-aligned dielectric isolation under the gate is achieved, which can effectively remove the parasitic silicon channel on the back of the nanosheet channel caused by the substrate SUB, thereby avoiding additional leakage. Therefore, the method for manufacturing a vertically stacked semiconductor device disclosed in the present invention has a simple manufacturing process and the semiconductor device obtained has good performance. It should be understood that in the embodiments of the present invention, the dielectric materials include but are not limited to SiO2, SiNx, SiNO, SiCO, SiCNO, SiCN, and ploymer, aC and other media and combinations. The method of filling the dielectric includes but is not limited to ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), Spin, and the like. Also, etching methods include but are not limited to wet etching, RIE (Reactive Ion Etching), RPS (Remote Plasma Source) etching, Chemical Dry Etch, ALE (Atomic Layer Etching), etc. The present disclosure does not limit this, and any method that can implement the above manufacturing method of the present disclosure is sufficient.

[0083] Fig.50 A schematic diagram of a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0084] like Fig.50 As shown, the vertically stacked semiconductor device 5000 of this embodiment includes: a lower field effect transistor 5001 and an upper field effect transistor 5002 stacked in the vertical direction. An inter-device isolation layer 114 between the lower field effect transistor 5001 and the upper field effect transistor 5002. For example, since the inter-device isolation layer 114 and the adjacent inner sidewall 113 are manufactured at the same time, in the vertically stacked semiconductor device of the embodiment of the present disclosure, the inter-device isolation layer 114 is integrated with the adjacent inner sidewall 113. And, the silicide pattern FSP and the lower isolation layer 129 are alternately arranged on the lower surface of the lower field effect transistor 5001. Among them, the lower field effect transistor 5001 and the upper field effect transistor 5002 each include: a plurality of channel layers 101 stacked spaced apart from each other in the vertical direction. Source / drain layers 117 connected to the channel layers 101 on both sides of the plurality of channel layers 101 in the first direction. The gate stack extends in a second direction intersecting the first direction and surrounds the channel layer 101. The gate stack surrounding the channel layer 101 corresponds to Fig.50 The gate structure G in the channel layer 101 is surrounded by the gate structure G. Fig.50(not shown in the perspective view) wherein the lower surface of the lowest gate stack in the lower field effect transistor 5001 is covered by the lower isolation layer 129. The lower surface of the source / drain layer 117 of the lower field effect transistor 5001 is covered by the upper surface of the silicide pattern FSP, and the lower surface of the silicide pattern FSP is connected to the contact hole 130.

[0085] For example, the contact hole 130 connected to the lower surface of the silicide pattern FSP is electrically connected to the power supply terminal. The contact hole (corresponding to the above-mentioned contact hole 133_1 and contact hole 133_2) connected to the upper surface of the source / drain layer 119 of the upper field effect transistor 5002 extends downward from one side of the upper field effect transistor 5002 to facilitate electrical connection with the bit line terminal or the ground terminal from the back side of the vertically stacked semiconductor device 5000. The thickness of the full silicide layer ranges from 5 to 500 nm.

[0086] According to an embodiment of the present disclosure, in the upper field effect transistor, the gate stack includes a portion on the upper surface of the uppermost channel layer 101 among the multiple channel layers 101 in the upper field effect transistor, and in the lower field effect transistor, the gate stack includes a portion on the lower surface of the lowermost channel layer 101 among the multiple channel layers 101 in the lower field effect transistor. Thus, the manufacturing method of the present disclosure allows the gate stack to more fully surround the channel layer 101, thereby improving the performance of the manufactured semiconductor device.

[0087] According to an embodiment of the present disclosure, there are multiple groups of vertically stacked upper field effect transistors and lower field effect transistors, and two groups of vertically stacked field effect transistors among the multiple groups of vertically stacked field effect transistors constitute an inverter structure. In the vertically stacked semiconductor device, multiple inverter structures are cross-coupled with each other to form an SRAM structure.

[0088] According to an embodiment of the present disclosure, for two groups of vertically stacked field effect transistors for forming an inverter structure, the drain layers of the two groups of vertically stacked field effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal. In the two groups of vertically stacked field effect transistors, the two source layers of one group of vertically stacked field effect transistors are both electrically connected to the ground terminal, and the two source layers of the other group of vertically stacked field effect transistors are electrically connected to the bit line terminal and the power supply, respectively.

[0089] Specifically, the following Fig.51 The structure of the vertically stacked semiconductor device of the present disclosure is described for example. Fig.51 The schematic diagram of the SRAM structure implemented based on the vertically stacked semiconductor device according to the embodiment of the present disclosure is schematically shown. Fig.51In the embodiment of the present disclosure, the extension direction of the X-axis is defined as a first direction, the extension direction of the Y-axis is defined as a second direction intersecting the first direction, and the extension direction of the Z-axis is defined as a vertical direction. In one embodiment of the present disclosure, the first direction and the second direction may be perpendicular to each other in the same horizontal plane. The vertical direction may be a direction perpendicular to the horizontal plane.

[0090] like Fig.51 As shown, the SRAM structure 5100 of this embodiment includes: the first group of field effect transistors and the second group of field effect transistors respectively arranged along a first direction on the upper surface of a substrate SUB, and a dielectric layer surrounding the substrate SUB, the first group of field effect transistors and the second group of field effect transistors.

[0091] exist Fig.51 Each field effect transistor shown in the figure can be used as a transmission transistor or a pull-up transistor, etc. according to actual needs. Among them, the transmission transistor can be a transistor for transmitting write data from the bit line. The pull-up transistor can include a pull-up transistor and a pull-down transistor. The pull-up transistor can be a transistor for pulling up the node level. The pull-down transistor can be a transistor for pulling down the node level. And, in Fig.51 In order to avoid blocking the SRAM structure 5100, Fig.51 It should be understood that the dielectric layer in the embodiment of the present disclosure can be arranged in the SRAM structure 5100 according to the requirements.

[0092] Continue to refer Fig.51 ,exist Fig.51 Two groups of field effect transistors arranged along the second direction are shown. Each group of field effect transistors includes a plurality of field effect transistors integrated into an integrated structure. Based on this, for ease of description, in this disclosure, the Fig.51 The plurality of field effect transistors on the lower left substrate SUB are defined as the first group of field effect transistors, and are defined as Fig.51 In the space shown, it is located in front; and Fig.51 The transistor on the upper right substrate is defined as the second group of field effect transistors mentioned above, and its Fig.51 The space shown is located at the rear.

[0093] The following will Fig.51 The field effect transistor shown in the figure is defined as a pull transistor or a transfer transistor to facilitate understanding of the SRAM structure 5100 of the embodiment of the present disclosure. It should be understood that the following is only an example, and those skilled in the art can define the function of the field effect transistor in the SRAM structure 5100 as required.

[0094] Exemplarily, the transistor located at the upper left of the first group of field effect transistors is defined as a transmission transistor AC1; the transistor located at the upper right of the first group of field effect transistors is defined as a pull-down transistor PD1; and the transistor located at the lower right of the first group of field effect transistors is defined as a pull-up transistor PU1. Fig.51 It can be seen that the transmission transistor AC1 and the pull-down transistor PD1 are coupled through a common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the first group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection among the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 can be realized. Moreover, the common layer used for electrical connection among the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 corresponds to the first source / drain layer of the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 respectively. Among them, the transmission transistor AC1 can be electrically connected to the bit line end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the transmission transistor AC1, and the transmission transistor AC1 can be electrically connected to the word line end through the gate contact hole connected to its gate structure G. The pull-up transistor PU1 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU1; the pull-down transistor PD1 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD1. Based on this, the stacked pull-up transistors in the first group of field effect transistors can be configured as an inverter, the pull-up transistor PU1 can realize the level of the pull-up common layer, and the pull-down transistor PD1 can realize the level of the pull-down common layer.

[0095] Correspondingly, the transistor located at the upper right of the second group of field effect transistors is defined as the transmission transistor AC2; the transistor located at the lower left of the second group of field effect transistors is defined as the pull-down transistor PD2; and the transistor located at the upper left of the second group of field effect transistors is defined as the pull-up transistor PU2. Fig.51It can be seen that the transmission transistor AC2 and the pull-down transistor PU2 are coupled through a common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the second group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection among the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 can be realized. Moreover, the common layer used for electrical connection among the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 corresponds to the first source / drain layer of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 respectively. Among them, the transmission transistor AC2 can be electrically connected to the bit line end through a source layer contact hole connected to the second source layer located on the other side of the gate structure of the transmission transistor AC2, and the transmission transistor AC2 can be electrically connected to the word line end through a gate contact hole connected to its gate structure G. The pull-up transistor PU2 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU2; the pull-down transistor PD2 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD2. Based on this, the stacked pull-up transistors in the second group of field effect transistors can be configured as an inverter, the pull-up transistor PU2 can realize the level of the pull-up common layer, and the pull-down transistor PD2 can realize the level of the pull-down common layer.

[0096] In the embodiment of the present disclosure, the gate structure of the pull-up transistor PU1 and the pull-down transistor PD1 can be electrically connected to the common layer in the second group of field effect transistors through contact holes, thereby being electrically connected to the second data output terminal; the gate structure of the pull-up transistor PU2 and the pull-down transistor PD2 can be electrically connected to the common layer in the first group of field effect transistors through contact holes, thereby being electrically connected to the first data output terminal. The gate structure of the transfer transistor AC1 and the transfer transistor AC2 can be electrically connected to the word line terminal through contact holes, thereby realizing the SRAM structure of the present disclosure. The contact holes for electrically connecting the gate structure and the common layer, and the contact holes for electrically connecting the transfer transistor to the word line terminal can be made by the above-mentioned back-end interconnection process, which will not be described in detail here.

[0097] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0098] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A lower field effect transistor and an upper field effect transistor stacked in a vertical direction are arranged on a substrate, and an inter-device isolation layer is disposed between the lower field effect transistor and the upper field effect transistor, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked and spaced apart from each other in a vertical direction; source / drain layers connected to the channel layers on both sides of the plurality of channel layers in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; the upper surface of the substrate is connected to the lower surface of the lowest gate stack and the lower surface of the source / drain layer in the lower field effect transistor; Etching the substrate to expose the lower surface of the lowermost gate stack and the lower surface of the source / drain layer in the lower field effect transistor; forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor; The fully silicide layer is patterned to remove the fully silicide layer located on the lower surface of the lowest gate stack in the lower field effect transistor, thereby forming an opening exposing the lower surface of the lowest gate stack in the lower field effect transistor, and forming a silicide layer pattern on both sides of the opening in the first direction that is in contact with the lower surface of the source / drain layer in the lower field effect transistor; Filling a dielectric material in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; A contact hole connected to the silicide layer pattern is provided.

2. The method according to claim 1, wherein: The method forms a full silicide layer on the lower surface of the gate stack and the lower surface of the source / drain layer in the lower field effect transistor, comprising: Inverting the lower field effect transistor and the upper field effect transistor so that the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor face upward; Depositing a silicon layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor facing upward; The metal is used to perform a silicidation reaction on the silicon layer to form the full silicide layer.

3. The method according to claim 2, wherein: The metal includes at least one of Ti, Ni, Co, W, Pt, Al, Cu and Ru.

4. The method according to claim 1, wherein: The step of patterning the full silicide layer comprises: The fully silicided layer is etched along the second direction according to the width of the gate stack surrounding the channel layer in the first direction to form the opening and the silicide patterns distributed on both sides of the opening.

5. The method according to claim 1, wherein: The method further comprises: forming a dielectric layer surrounding the lower field effect transistor and the upper field effect transistor; Etching the dielectric layer from above to form a source / drain layer opening exposing the upper surface of the source / drain layer of the upper field effect transistor, wherein a projection surface of the source / drain layer opening in the vertical direction protrudes in the second direction from a projection surface of the source / drain layer of the upper field effect transistor in the vertical direction; Filling the source / drain layer opening with a conductive material, Using a dielectric material to seal the filled source / drain layer opening; According to the portion where the projection surface of the source / drain layer opening protrudes beyond the projection surface of the source / drain layer of the upper field effect transistor, the dielectric layer is etched from below to form an opening exposing the lower surface of the conductive material; The opening exposing the lower surface of the conductive material is filled with a conductive material, thereby forming a contact hole connected to the source / drain layer of the upper field effect transistor.

6. The method according to claim 5, wherein: The contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to the ground terminal; or the contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to the bit line terminal.

7. The method according to claim 1, wherein: The lower field effect transistor and the upper field effect transistor stacked in the vertical direction and arranged on the substrate, and the device isolation layer between the lower field effect transistor and the upper field effect transistor, include: A lower stacked structure, an intermediate layer and an upper stacked structure are sequentially arranged on the substrate, wherein the upper stacked structure and the lower stacked structure each include the channel layer and the sacrificial layer which are alternately arranged; patterning the lower stacked structure, the middle layer, and the upper stacked structure together with an upper portion of the substrate to form a fin extending along the first direction; forming a sacrificial gate on the substrate extending along the second direction so as to intersect the fin; forming a gate spacer on the sidewall of the sacrificial gate; Using the sacrificial gate and the gate spacer as masks, patterning the lower stacked structure, the middle layer and the upper stacked structure, so that the patterned lower stacked structure, the middle layer and the upper stacked structure have side surfaces exposed in the first direction; Replacing the intermediate layer with an inter-device isolation layer; forming a source / drain layer of the lower field effect transistor in contact with an exposed side surface of the channel layer in the lower stacked structure and a source / drain layer of the upper field effect transistor in contact with an exposed side surface of the channel layer in the upper stacked structure; and The sacrificial gate and the sacrificial layer are replaced with a gate stack.

8. A vertically stacked semiconductor device, comprising: A lower field effect transistor and an upper field effect transistor stacked in a vertical direction; an inter-device isolation layer between the lower field effect transistor and the upper field effect transistor; and, a full silicide layer and a lower isolation layer alternately disposed on the lower surface of the lower field effect transistor; Wherein, the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked and spaced apart from each other in a vertical direction; Source / drain layers connected to the channel layers at both sides of the plurality of channel layers in the first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layer; Wherein, the lower surface of the lowermost gate stack in the lower field effect transistor is covered by a lower isolation layer; The lower surface of the source / drain layer of the lower field effect transistor is covered by the upper surface of the silicide pattern, and the lower surface of the silicide pattern is connected to the contact hole.

9. The vertically stacked semiconductor device according to claim 8, wherein: A contact hole connected to the lower surface of the silicide pattern is electrically connected to a power supply terminal; A contact hole connected to the upper surface of the source / drain layer of the upper field effect transistor extends downward from one side of the upper field effect transistor to facilitate electrical connection with a bit line terminal or a ground terminal from the back side of the vertically stacked semiconductor device.

10. The vertically stacked semiconductor device according to claim 8, wherein: The thickness of the silicide pattern ranges from 5 to 500 nm.

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