BCD device preparation method and BCD device

Abstract

The embodiment of the invention provides a BCD device preparation method and a BCD device. The BCD device comprises an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer and a BCD structure. A first N-type epitaxial layer is arranged on the N-type substrate, and a second N-type epitaxial layer is arranged on the first N-type epitaxial layer; a first P well region is arranged in the first N-type epitaxial layer, and a second P well region is arranged in the second N-type epitaxial layer; wherein the first P well region and the second P well region adopt the same mask; a BCD structure is arranged on the second N-type epitaxial layer, and the BCD structure comprises a VDMOS structure. The problem that the traditional BCD process and the VDMOS process are poor in compatibility in the transverse direction and the longitudinal direction is solved by reducing the number of used masks, the chip area is reduced, the process is simplified, and the product cost is reduced.

Description

Technical Field

[0001] The embodiments of the present specification relate to the field of semiconductor technology, and in particular to a method for preparing a BCD device and a BCD device. Background Art

[0002] Intelligent power integrated circuit technology integrates logic or linear control circuits and protection circuits with corresponding power devices on the same chip, which not only reduces the number of components used and increases chip integration, but also reduces parasitic effects, reduces production and packaging costs, and improves the reliability of the control system. With the development of the power electronics market, intelligent power integrated circuit technology has been applied in almost all fields, from low power levels such as communications to high power levels such as industrial electronics.

[0003] The current mainstream power integration technology is the Bipolar-CMOS-DMOS process (BCD process for short). The BCD process is a process that integrates Bipolar devices, CMOS devices, and DMOS devices on the same silicon substrate. Bipolar devices have the characteristics of low noise, high precision, and high unit current density. CMOS devices have the characteristics of high integration, simple logic control, and low power consumption. When they are made on the same chip with DMOS devices, they can greatly improve system performance, reduce costs, and reduce power consumption. With the continuous development of BCD technology, it has been widely used in power management, motor drive, industrial electronics, automotive electronics, and other fields. However, the mainstream BCD process is still mainly horizontal, and has poor compatibility with the vertical VDMOS. In addition, the electrodes of the integrated DMOS need to be led out from the front of the wafer and interconnected, which leads to parasitic inductance of the leads, and makes problems such as high-voltage interconnection and thermal design prominent.

[0004] Therefore, a better solution is urgently needed. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a BCD device. One or more embodiments of this specification also relate to a method for preparing a BCD device to solve the technical defects existing in the prior art.

[0006] According to a first aspect of an embodiment of this specification, a method for preparing a BCD device is provided, comprising:

[0007] Determine the N-type substrate;

[0008] Growing a first N-type epitaxial layer on an N-type substrate, and forming a P-type buried layer in the first N-type epitaxial layer;

[0009] forming a first P well on the P-type buried layer;

[0010] growing a second N-type epitaxial layer on the first N-type epitaxial layer;

[0011] A second P-well is formed on the surface of the second N-type epitaxial layer; wherein the first P-well and the second P-well are connected, and the first P-well region and the second P-well region use the same mask;

[0012] A PB region is formed in the second N-type epitaxial layer as a drift region of the LDPMOS structure;

[0013] forming an ND region in the second P well as a drift region of the LDNMOS structure;

[0014] forming silicon dioxide and silicon nitride layers on the surface of the second N-type epitaxial layer, and forming an oxidized isolation region;

[0015] An electrode structure of a BCD device is formed on the second N-type epitaxial layer.

[0016] In a possible implementation, forming a P-type buried layer in the first N-type epitaxial layer includes:

[0017] In the first N-type epitaxial layer, a P-type buried layer mask is used to form a P-type buried layer ion implantation region through a photolithography process;

[0018] Boron ions are implanted into the P-type buried layer ion implantation region through an ion implantation process, and a push-in junction process is performed to form a P-type buried layer.

[0019] In a possible implementation, forming a first P-well on a P-type buried layer includes:

[0020] Using a P-well mask on the P-type buried layer region, a first P-well ion implantation region is formed by a photolithography process;

[0021] The first P-well is formed by implanting boron ions into the first P-well ion implantation region through an ion implantation process.

[0022] In a possible implementation, forming a second P-well on the surface of the second N-type epitaxial layer includes:

[0023] On the surface of the second N-type epitaxial layer, a second P-well ion implantation region is formed by a photolithography process using a P-well mask;

[0024] Boron ions are implanted into the second P-well ion implantation region through an ion implantation process, and a push-in junction process is performed to form a second P-well.

[0025] In a possible implementation, forming a PB region in the second N-type epitaxial layer includes:

[0026] Using a PB mask on the second N-type epitaxial layer, a PB ion implantation region is formed by a photolithography process;

[0027] implanting boron ions into the PB ion implantation area through an ion implantation process, and performing annealing to form a PB area;

[0028] Using an ND mask, a ND ion implantation region is formed in the second N-type epitaxial layer through a photolithography process;

[0029] Phosphorus ions are implanted into the ND ion implantation region by an ion implantation process, and annealing is performed to form the ND region.

[0030] In a possible implementation, forming an electrode structure of a BCD device on the second N-type epitaxial layer includes:

[0031] Forming a gate oxide layer on the surface of the second N-type epitaxial layer based on an oxidation process;

[0032] Depositing a polysilicon layer on the surface of the second N-type epitaxial layer based on a deposition process;

[0033] Based on the Poly mask, a gate structure is formed through photolithography and etching processes;

[0034] Based on the P+ mask and the N+ mask, an N-type heavily doped region and a P-type heavily doped region are formed through a photolithography process and an ion implantation process.

[0035] According to a second aspect of an embodiment of this specification, a BCD device is provided, characterized in that it includes: an N-type substrate, at least two epitaxial layers, and a BCD structure, wherein the at least two epitaxial layers include a first N-type epitaxial layer and a second N-type epitaxial layer;

[0036] A first N-type epitaxial layer is disposed on the N-type substrate, and a second N-type epitaxial layer is disposed on the first N-type epitaxial layer;

[0037] A first P-well region is provided in the first N-type epitaxial layer, and a second P-well region is provided in the second N-type epitaxial layer; wherein the first P-well region and the second P-well region use the same mask;

[0038] A BCD structure is arranged on the second N-type epitaxial layer; wherein the BCD structure includes a VDMOS structure.

[0039] In a possible implementation, a P-type buried layer region is provided in the first N-type epitaxial layer;

[0040] A first P-well region is provided in the P-type buried layer region; wherein the first P-well region uses boron ions as implanted ions;

[0041] The ND region is arranged in the second P-well region; wherein the implanted ions used in the second P-well region are boron ions, and the implanted ions used in the ND region are phosphorus ions.

[0042] In a possible implementation, the BCD structure includes an NMOS structure, a PMOS structure, an LDNMOS structure, an LDPMOS structure, a VDMOS structure, an NPN structure, a PNP structure, a Diode structure, and a Zener structure;

[0043] Performing PB implantation and well driving on the upper surface of the second N-type epitaxial layer to form a well region of a VDMOS structure, a drift region of an LDPMOS structure, a base region of an NPN structure, and an emitter region of a PNP structure;

[0044] Forming gates of NMOS structure, PMOS structure, LDNMOS structure, LDPMOS structure and VDMOS structure on the second N-type epitaxial layer through Poly deposition, photolithography process and etching process;

[0045] Forming source and drain electrodes of NMOS structure, PMOS structure, LDNMOS structure and LDPMOS structure on the upper surface of the second N-type epitaxial layer by photolithography and ion implantation;

[0046] A collector, a base and an emitter of an NPN structure and a PNP structure are formed on the upper surface of the second N-type epitaxial layer by photolithography and ion implantation;

[0047] An anode and a cathode of a diode structure and a source of a VDMOS structure are formed on the upper surface of the second N-type epitaxial layer by photolithography and ion implantation.

[0048] The drain of the VDMOS structure is led out from the back side of the N-type substrate.

[0049] In a possible implementation manner, the NMOS structure and the LDNMOS structure are enhancement types.

[0050] The embodiments of this specification provide a method for preparing a BCD device and a BCD device, wherein the BCD device comprises: an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, and a BCD structure; a first N-type epitaxial layer is arranged on the N-type substrate, and a second N-type epitaxial layer is arranged on the first N-type epitaxial layer; a first P-well region is arranged in the first N-type epitaxial layer, and a second P-well region is arranged in the second N-type epitaxial layer; wherein the first P-well region and the second P-well region use the same mask; a BCD structure is arranged on the second N-type epitaxial layer, wherein the BCD structure comprises a VDMOS structure. The problem of poor lateral and longitudinal compatibility between the traditional BCD process and the VDMOS process is solved by reducing the number of masks used, and the chip area is reduced to simplify the process and reduce the cost of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a structural diagram of a BCD device provided by an embodiment of this specification;

[0052] Figure 2 is a flow chart of a method for preparing a BCD device provided by an embodiment of this specification;

[0053] Figure 3 is a first schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0054] Figure 4 is a second schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0055] Figure 5 is a third schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0056] Figure 6 is a fourth schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0057] Figure 7 is a fifth schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0058] Figure 8 is a sixth schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0059] Fig. 9 is a seventh schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification;

[0060] Fig.10 This is the eighth schematic diagram of a method for preparing a BCD device provided by an embodiment of this specification. DETAILED DESCRIPTION

[0061] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0062] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0063] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0064] In this specification, a BCD device is provided. This specification also relates to a method for preparing the BCD device, which is described in detail one by one in the following examples.

[0065] See also Figure 1 , Figure 1 A structural diagram of a BCD device provided according to an embodiment of the present specification is shown, which specifically includes an N-type substrate 1, a first N-type epitaxial layer 2, a second N-type epitaxial layer 5, and a BCD structure; a first N-type epitaxial layer 2 is provided on the N-type substrate 1, and a second N-type epitaxial layer 5 is provided on the first N-type epitaxial layer 2; a first P-well 4 region is provided in the first N-type epitaxial layer 2, and a second P-well 6 region is provided in the second N-type epitaxial layer 5; wherein the first P-well 4 region and the second P-well 6 region use the same mask; a BCD structure is provided on the second N-type epitaxial layer 5; wherein the BCD structure includes a VDMOS structure.

[0066] The embodiments of the present specification reduce the number of masks used and produce diversified devices, thereby making the circuit design more flexible.

[0067] In a possible implementation, a P-type buried layer 3 region is provided in the first N-type epitaxial layer 2; a first P-well 4 region is provided in the P-type buried layer 3 region; wherein the first P-well 4 region uses boron ions as the implanted ions; an ND region is provided in the second P-well 6 region; wherein the second P-well 6 region uses boron ions as the implanted ions, and the ND region uses phosphorus ions as the implanted ions.

[0068] In practical applications, a first N-type epitaxial layer 2 is formed on the upper surface of an N-type substrate 1, a P-type buried layer 3 region is provided in the first N-type epitaxial layer 2, and the implanted ions in the P-type buried layer 3 region are boron ions; a first P-well 4 region is provided in the P-type buried layer 3 region, and the implanted ions in the first P-well 4 region are boron ions; a second N-type epitaxial layer 5 is formed on the upper surface of the first N-type epitaxial layer 2; a second P-well 6 region is provided in the second N-type epitaxial layer 5, and the implanted ions in the second P-well 6 region are boron ions; an ND region is provided in the second P-well 6 region, and the implanted ions in the ND region are phosphorus ions; and an ND region 8 provided in the second P-well 6 region serves as an N-type drift region of the LDNMOS.

[0069] In a possible implementation, the BCD structure includes an NMOS structure, a PMOS structure, an LDNMOS structure, an LDPMOS structure, a VDMOS structure, an NPN structure, a PNP structure, a Diode structure and a Zener structure; PB is implanted and well-pushed on the upper surface of the second N-type epitaxial layer 5 to form a well region of a VDMOS structure, a drift region of an LDPMOS structure, a base region of an NPN structure and an emitter region of a PNP structure; and an NMOS structure, a PMOS structure, an LDNMOS structure, an LDPMOS structure, a LDMOS structure, a NPN structure, a PNP structure, a Diode structure and a Zener structure are formed. The gates of the PMOS structure and the VDMOS structure are formed; the source and drain of the NMOS structure, the PMOS structure, the LDNMOS structure, and the LDPMOS structure are formed on the upper surface of the second N-type epitaxial layer 5 by photolithography and ion implantation; the collector, base, and emitter of the NPN structure and the PNP structure are formed on the upper surface of the second N-type epitaxial layer 5 by photolithography and ion implantation; the anode and cathode of the Diode structure and the source of the VDMOS structure are formed on the upper surface of the second N-type epitaxial layer 5 by photolithography and ion implantation; the drain of the VDMOS structure is led out from the back side of the N-type substrate 1.

[0070] In practical applications, PB is implanted and high-temperature well is driven on the upper surface of the second N-type epitaxial layer 5 to form the well region of VDMOS, the drift region of LDPMOS, the base region of NPN tube and the emitter region of PNP; the gate 11 of NMOS, PMOS, LDNMOS, LDPMOS and VDMOS is formed on the second N-type epitaxial layer 5 by Poly deposition, photolithography and etching. The N-type heavily doped region 12 and the P-type heavily doped region 13 are formed on the upper surface of the second N-type epitaxial layer 5 by photolithography and ion implantation, respectively forming the source and drain of NMOS, PMOS, LDNMOS and LDPMOS; the collector, base and emitter of NPN and PNP; the anode and cathode of Diode; and the source of VDMOS. The drain of the VDMOS device is led out from the back of the N-type substrate 1.

[0071] In a possible implementation manner, the NMOS structure and the LDNMOS structure are enhancement types.

[0072] In practical applications, NMOS and LDNMOS are enhancement types, and depletion type NMOS and LDNMOS can be made by adding a mask.

[0073] Since the first and second epitaxial layer structures are stacked vertically and the VDMOS structure is led out from the back of the wafer, the parasitic inductance generated by connecting the devices through leads is avoided. Compared with the existing BCD process of integrated LDMOS, it can reduce the chip area, improve chip utilization, and reduce the complexity of high-voltage interconnection.

[0074] The embodiments of this specification provide a method for preparing a BCD device and a BCD device, wherein the BCD device comprises: an N-type substrate 1, a first N-type epitaxial layer 2, a second N-type epitaxial layer 5, and a BCD structure; a first N-type epitaxial layer 2 is arranged on the N-type substrate 1, and a second N-type epitaxial layer 5 is arranged on the first N-type epitaxial layer 2; a first P-well 4 region is arranged in the first N-type epitaxial layer 2, and a second P-well 6 region is arranged in the second N-type epitaxial layer 5; wherein the first P-well 4 region and the second P-well 6 region use the same mask; a BCD structure is arranged on the second N-type epitaxial layer 5, wherein the BCD structure comprises a VDMOS structure. The problem of poor lateral and longitudinal compatibility between the traditional BCD process and the VDMOS process is solved by reducing the number of masks used, and the chip area is reduced to simplify the process and reduce the cost of the product.

[0075] Furthermore, the embodiments of this specification use a reverse biased PN junction for isolation, thereby ensuring the anti-interference capability of other devices except the VDMOS.

[0076] In the BCD device structure of the embodiment of the present specification, since the buried layer, the first P-well and the second P-well are of P-type, and the substrate, the first epitaxial layer and the second epitaxial layer are of N-type, when the substrate is increased in level, the PN junction formed by the P-well and the epitaxial layer is reverse biased, and the reverse biased PN junction plays an isolation role, thereby improving the anti-interference ability of other devices except VDMOS.

[0077] See also Figure 2 , Figure 2 A flow chart of a method for preparing a BCD device according to an embodiment of the present specification is shown, which specifically includes the following steps.

[0078] Step S101: determine an N-type substrate 1.

[0079] In practical applications, it is first necessary to select an N-type substrate 1 and perform subsequent steps on the N-type substrate 1 .

[0080] Step S102 : growing a first N-type epitaxial layer 2 on an N-type substrate 1 , and forming a P-type buried layer 3 in the first N-type epitaxial layer 2 .

[0081] In one possible implementation, a P-type buried layer 3 is formed in the first N-type epitaxial layer 2, including: in the first N-type epitaxial layer 2, using a P-type buried layer 3 mask, forming a P-type buried layer 3 ion implantation region by a photolithography process; implanting boron ions into the P-type buried layer 3 ion implantation region by an ion implantation process, and performing a push-junction process to form the P-type buried layer 3.

[0082] In practical applications, see Figure 3, grow the first N-type epitaxial layer 2 on the N-type substrate 1, use the P-type buried layer 3 mask, form the P-type buried layer 3 ion implantation area through the photolithography process, then implant boron ions through the ion implantation process, and then perform high-temperature push-in to form the P-type buried layer 3.

[0083] Step S103 : forming a first P well 4 on the P-type buried layer 3 .

[0084] In one possible implementation, a first P-well 4 is formed on the P-type buried layer 3, including: using a P-well mask on the P-type buried layer 3 to form a first P-well 4 ion implantation region through a photolithography process; and implanting boron ions into the first P-well 4 ion implantation region through an ion implantation process to form the first P-well 4.

[0085] In practical applications, see Figure 4 , a P-well mask is used on the P-type buried layer 3 to form a first P-well 4 ion implantation area through a photolithography process, and then boron ions are implanted therein through an ion implantation process to form the first P-well 4.

[0086] Step S104 : growing a second N-type epitaxial layer 5 on the first N-type epitaxial layer 2 .

[0087] In practical applications, see Figure 4 , the second N-type epitaxial layer 5 continues to grow on the first N-type epitaxial layer 2 .

[0088] Step S105: forming a second P-well 6 on the surface of the second N-type epitaxial layer 5; wherein the first P-well 4 and the second P-well 6 are connected.

[0089] In one possible implementation, a second P-well 6 is formed on the surface of the second N-type epitaxial layer 5, including: on the surface of the second N-type epitaxial layer 5, using a P-well mask, forming a second P-well 6 ion implantation region through a photolithography process; implanting boron ions into the second P-well 6 ion implantation region through an ion implantation process, and performing a push-junction process to form a second P-well 6.

[0090] In practical applications, see Figure 5 On the surface of the second N-type epitaxial layer 5, a P-well mask is used to form a second P-well 6 ion implantation area through a photolithography process, and then boron ions are implanted into it through an ion implantation process, followed by a high-temperature push-in junction to form a second P-well 6. After the high-temperature push-in junction, the first P-well 4 and the second P-well 6 are connected.

[0091] The second P well 6 serves as the well region of NMOS, the well region of LDNMOS, and the anode of Diode, and the second N-type epitaxial layer 5 region isolated by the second P well 6 serves as the well region of PMOS, the well region of LDPMOS, the collector of NPN, and the base region of PNP.

[0092] Step S106 : forming a PB region in the second N-type epitaxial layer 5 .

[0093] In a possible implementation, a PB region is formed in the second N-type epitaxial layer 5, including: using a PB mask in the second N-type epitaxial layer 5 to form a PB ion implantation region through a photolithography process; implanting boron ions into the PB ion implantation region through an ion implantation process, and annealing to form a PB region 7; using an ND mask in the second N-type epitaxial layer 5 to form an ND ion implantation region through a photolithography process; implanting phosphorus ions into the ND ion implantation region through an ion implantation process, and annealing to form an ND region 8.

[0094] In practical applications, see Figure 6 , using a PB mask, a PB ion implantation region is formed by a photolithography process, and then boron ions are implanted therein by an ion implantation process, followed by annealing to form a PB region, namely, PB region 7.

[0095] Among them, the PB region 7 serves as the P-type drift region of the LDPMOS, the base region of the NPN tube, the emitter region of the PNP, and the well region of the VDMOS.

[0096] For further information, see Figure 7 , using an ND mask, a ND ion implantation region is formed by a photolithography process, and then phosphorus ions are implanted therein by an ion implantation process, followed by annealing to form an ND region 8.

[0097] The ND region 8 is used as an N-type drift region of the LDNMOS.

[0098] Step S107 : forming silicon dioxide and silicon nitride layers on the surface of the second N-type epitaxial layer 5 , and forming an oxide isolation region 9 .

[0099] In practical applications, see Figure 8 , silicon dioxide and silicon nitride layers are formed on the upper surface of the second N-type epitaxial layer 5 by oxidation and deposition processes, and then a local oxidation isolation region 9 is formed by photolithography and etching processes using an active area mask, and then an oxidation process is used to form an oxidation isolation region 9.

[0100] Step S108 : forming an electrode structure of a BCD device on the second N-type epitaxial layer 5 .

[0101] In one possible implementation, an electrode structure of a BCD device is formed on the second N-type epitaxial layer 5, including: forming a gate oxide layer on the surface of the second N-type epitaxial layer 5 based on an oxidation process; depositing a polysilicon layer on the surface of the second N-type epitaxial layer 5 based on a deposition process; forming a gate structure through a photolithography process and an etching process based on a Poly mask; and forming an N-type heavily doped region 12 and a P-type heavily doped region 13 through a photolithography process and an ion implantation process based on a P+ mask and an N+ mask.

[0102] In practical applications, see Fig. 9 By adding a mask of a depletion injection layer, phosphorus ions or arsenic ions can be implanted into the channel region of the NMOS and LDNMOS using a photolithography process and an ion implantation process to form a depletion region 10, thereby manufacturing a depletion-type NMOS and LDNMOS.

[0103] For further information, see Fig.10 , a gate oxide layer is formed on the surface of the second N-type epitaxial layer 5 by an oxidation process, a polysilicon layer is deposited on the surface of the second N-type epitaxial layer 5 by a deposition process, and then a Poly mask is used to form the gates 11 of all MOS through a photolithography process and an etching process.

[0104] For further information, see Figure 1 , using P+ and N+ masks respectively, through photolithography process and ion implantation process, an N-type heavily doped region 12 and a P-type heavily doped region 13 are formed, thereby forming the source and drain of NMOS, PMOS, LDNMOS, and LDPMOS respectively; the collector, base, and emitter of NPN and PNP; the anode and cathode of Diode; and the source of VDMOS.

[0105] The N-type heavily doped region 12 and the P-type heavily doped region 13 serve as the cathode and anode of the Zener tube respectively.

[0106] It should be noted that there is no particular order for the P+ and N+ processes, and the P+ process can be performed first, or the N+ process can be performed first. The embodiments of this specification do not limit this.

[0107] After forming the above electrode structure, an intermediate dielectric layer, contact holes and a metal layer are then formed, and the back side of the N-type substrate 1 is thinned according to the back side thinning process of VDMOS, and metal is plated after thinning to lead the drain of the VDMOS out from the lower end surface of the N-type substrate 1. The above metal plating can use Ti, Ni and Ag.

[0108] The embodiments of the present specification provide a method for preparing a BCD device and a BCD device, wherein the method comprises: determining an N-type substrate 1; growing a first N-type epitaxial layer 2 on the N-type substrate 1, forming a P-type buried layer 3 in the first N-type epitaxial layer 2 by photolithography, ion implantation and push-junction process; forming a first P-well 4 on the P-type buried layer 3 by photolithography and ion implantation process; generating a second N-type epitaxial layer 5 on the first N-type epitaxial layer 2; forming a second P-well 6 on the surface of the second N-type epitaxial layer 5 by photolithography, ion implantation and push-junction process; wherein the first P-well 4 and the second P-well 6 are connected; forming a PB region on the second N-type epitaxial layer 5 by photolithography and ion implantation process; forming a silicon dioxide and silicon nitride layer on the surface of the second N-type epitaxial layer 5 by oxidation and deposition process, and forming an oxidized isolation region 9 by photolithography, etching and oxidation process; and forming an electrode structure of the BCD device on the second N-type epitaxial layer 5. The problem of poor lateral and longitudinal compatibility between the traditional BCD process and the VDMOS process is solved by reducing the number of masks used, reducing the chip area to simplify the process and reduce product costs.

[0109] The above is a schematic scheme of a method for preparing a BCD device of this embodiment. It should be noted that the technical scheme of the method for preparing a BCD device is the same as the technical scheme of the above-mentioned BCD device, and the details of the technical scheme of the method for preparing a BCD device that are not described in detail can be referred to the description of the technical scheme of the above-mentioned BCD device.

[0110] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0111] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0112] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A method for preparing a BCD device, characterized in that: include: Determine the N-type substrate; Growing a first N-type epitaxial layer on the N-type substrate, and forming a P-type buried layer in the first N-type epitaxial layer; forming a first P well on the P-type buried layer; growing a second N-type epitaxial layer on the first N-type epitaxial layer; forming a second P-well on the surface of the second N-type epitaxial layer; wherein the first P-well and the second P-well are connected, and the first P-well region and the second P-well region use the same mask; forming a PB region in the second N-type epitaxial layer as a drift region of the LDPMOS structure; forming an ND region in the second P well as a drift region of the LDNMOS structure; forming silicon dioxide and silicon nitride layers on the surface of the second N-type epitaxial layer, and forming an oxidized isolation region; An electrode structure of the BCD device is formed on the second N-type epitaxial layer.

2. The method according to claim 1, characterized in that The forming of a P-type buried layer in the first N-type epitaxial layer comprises: In the first N-type epitaxial layer, a P-type buried layer ion implantation region is formed by a photolithography process using a P-type buried layer mask; Boron ions are implanted into the P-type buried layer ion implantation region through an ion implantation process, and a push-in process is performed to form a P-type buried layer.

3. The method according to claim 1, characterized in that The forming of a first P well on the P-type buried layer comprises: Using a P-well mask on the P-type buried layer region, a first P-well ion implantation region is formed by a photolithography process; The first P-well is formed by implanting boron ions into the first P-well ion implantation region through an ion implantation process.

4. The method according to claim 1, characterized in that The forming of a second P-well on the surface of the second N-type epitaxial layer comprises: On the surface of the second N-type epitaxial layer, using a P-well mask, a second P-well ion implantation region is formed by a photolithography process; Boron ions are implanted into the second P-well ion implantation region through an ion implantation process, and a push-in junction process is performed to form a second P-well.

5. The method according to claim 1, characterized in that The forming of the PB region in the second N-type epitaxial layer comprises: Using a PB mask, a PB ion implantation region is formed in the second N-type epitaxial layer by a photolithography process; implanting boron ions into the PB ion implantation region through an ion implantation process, and performing annealing to form a PB region; Using an ND mask, a ND ion implantation region is formed in the second N-type epitaxial layer by a photolithography process; Phosphorus ions are implanted into the ND ion implantation region by an ion implantation process, and annealing is performed to form an ND region.

6. The method according to claim 1, characterized in that The electrode structure of the BCD device is formed on the second N-type epitaxial layer, comprising: forming a gate oxide layer on the surface of the second N-type epitaxial layer based on an oxidation process; Depositing a polysilicon layer on the surface of the second N-type epitaxial layer based on a deposition process; Based on the Poly mask, a gate structure is formed through photolithography and etching processes; Based on the P+ mask and the N+ mask, an N-type heavily doped region and a P-type heavily doped region are formed through a photolithography process and an ion implantation process.

7. A BCD device, characterized in that: It comprises: an N-type substrate, at least two epitaxial layers and a BCD structure, wherein the at least two epitaxial layers comprise a first N-type epitaxial layer and a second N-type epitaxial layer; A first N-type epitaxial layer is disposed on the N-type substrate, and a second N-type epitaxial layer is disposed on the first N-type epitaxial layer; A first P-well region is provided in the first N-type epitaxial layer, and a second P-well region is provided in the second N-type epitaxial layer; wherein the first P-well region and the second P-well region use the same mask; The BCD structure is disposed on the second N-type epitaxial layer; wherein the BCD structure includes a VDMOS structure.

8. The BCD device according to claim 7, characterized in that: A P-type buried layer region is provided in the first N-type epitaxial layer; The first P-well region is arranged in the P-type buried layer region; wherein the first P-well region uses boron ions as implanted ions; An ND region is disposed in the second P-well region; wherein the second P-well region uses boron ions as implanted ions, and the ND region uses phosphorus ions as implanted ions.

9. The BCD device according to claim 7, characterized in that: BCD structures include NMOS structure, PMOS structure, LDNMOS structure, LDPMOS structure, VDMOS structure, NPN structure, PNP structure, Diode structure and Zener structure; Performing PB implantation and well driving on the upper surface of the second N-type epitaxial layer to form a well region of a VDMOS structure, a drift region of an LDPMOS structure, a base region of an NPN structure, and an emitter region of a PNP structure; Forming gates of NMOS structure, PMOS structure, LDNMOS structure, LDPMOS structure and VDMOS structure on the second N-type epitaxial layer by means of Poly deposition, photolithography process and etching process; Forming source and drain electrodes of NMOS structure, PMOS structure, LDNMOS structure and LDPMOS structure on the upper surface of the second N-type epitaxial layer by photolithography and ion implantation; Forming the collector, base and emitter of the NPN structure and the PNP structure on the upper surface of the second N-type epitaxial layer by photolithography and ion implantation; Forming an anode and a cathode of a diode structure and a source of a VDMOS structure on the upper surface of the second N-type epitaxial layer by photolithography and ion implantation; The drain of the VDMOS structure is led out from the back side of the N-type substrate.

10. The BCD device according to claim 9, characterized in that: The NMOS structure and the LDNMOS structure are enhancement types.

Images