Array substrate, display device and manufacturing method of array substrate

Abstract

The embodiment of the invention provides an array substrate, a display device and a manufacturing method of the array substrate, and the array substrate comprises a substrate; the semiconductor layer is arranged on one side of the substrate, the semiconductor layer comprises a channel region, an ion concentration buffer region and conductor regions, the conductor regions are located at the two ends of the channel region in the first direction, and the ion concentration buffer region is located between the channel region and the conductor regions; the gate layer is arranged on the side, away from the substrate, of the semiconductor layer, the gate layer comprises a first surface facing the side of the semiconductor layer, and the orthographic projection of the channel region on the substrate is located in the orthographic projection of the first surface on the substrate. The orthographic projection of the channel region on the substrate is within the orthographic projection of the first surface on the substrate, and the first surface can form a field effect with the semiconductor layer. Moreover, the ion concentration buffer region is arranged, so that the opposite area between the first surface of the grid electrode and the ion concentration buffer region and the conductor region is reduced, the generation of extra capacitance is reduced, and the processing performance of the array substrate is improved.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate, a display device, and a method for manufacturing the array substrate. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the process performance of array substrates of current display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display device, and a method for manufacturing the array substrate, aiming to improve the process performance of the array substrate.

[0005] An embodiment of the first aspect of the present application provides an array substrate, comprising: a substrate; a semiconductor layer, arranged on one side of the substrate, the semiconductor layer comprising a channel region, an ion concentration buffer region and a conductor region, the conductor region being located at both ends of the channel region along a first direction, and the ion concentration buffer region being located between the channel region and the conductor region; a gate layer, arranged on a side of the semiconductor layer away from the substrate, the gate layer comprising a first surface on a side facing the semiconductor layer, the orthographic projection of the channel region on the substrate being located within the orthographic projection of the first surface on the substrate; the first direction is arranged to intersect with a thickness direction of the substrate.

[0006] According to an embodiment of the present application, the gate layer includes a second surface facing away from the semiconductor layer, and both ends of the orthographic projection of the first surface on the substrate along the first direction are located within the orthographic projection of the second surface on the substrate.

[0007] According to an embodiment of the present application, the orthographic projection of the ion concentration buffer on the substrate is offset from the orthographic projection of the first surface on the substrate, and the orthographic projection of the ion concentration buffer on the substrate is located within the orthographic projection of the second surface on the substrate.

[0008] According to an embodiment of the present application, the gate layer includes a first metal layer and a second metal layer stacked in a direction away from the substrate. In the first direction, both ends of the orthographic projection of the first metal layer on the substrate are located within the orthographic projection of the second metal layer on the substrate.

[0009] According to an embodiment of the present application, the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate.

[0010] According to an embodiment of the present application, the acid corrosion resistance of the second metal layer is greater than that of the first metal layer.

[0011] According to an embodiment of the present application, the first metal layer includes aluminum or titanium, and the second metal layer includes molybdenum.

[0012] According to an embodiment of the present application, an orthographic projection of the gate layer on the substrate and an orthographic projection of the ion concentration buffer zone on the substrate are arranged in a staggered manner.

[0013] According to an embodiment of the present application, the gate layer includes a second surface facing away from the semiconductor layer, and in the first direction, two ends of the orthographic projection of the second surface on the substrate are located within the orthographic projection of the first surface on the substrate.

[0014] An embodiment of the second aspect of the present application further provides a display device, comprising the array substrate in any one of the embodiments of the first aspect.

[0015] The third aspect of the present application also provides a method for manufacturing an array substrate, including:

[0016] A semiconductor layer is formed on one side of the substrate.

[0017] A gate layer is formed on a side of the semiconductor layer facing away from the substrate. In a first direction, two ends of an orthographic projection of the gate layer on the substrate are located within the orthographic projection of the semiconductor layer on the substrate.

[0018] Ion implantation is performed from the side of the gate layer away from the substrate toward the semiconductor layer to form a channel region and conductive regions located at two sides of the channel region along a first direction in the semiconductor layer.

[0019] An ion concentration buffer zone is formed between the conductive region and the channel region.

[0020] According to an embodiment of the present application, the step of forming a gate layer on a side of the semiconductor layer facing away from the substrate includes:

[0021] A gate material layer is formed on the side of the semiconductor layer facing away from the substrate.

[0022] The patterned gate material layer forms a gate layer, which includes a first surface facing the semiconductor layer and a second surface facing away from the semiconductor layer. In a first direction, both ends of the orthographic projection of the first surface on the substrate are located within the orthographic projection of the second surface on the substrate.

[0023] According to an embodiment of the present application, the step of performing ion implantation from the side of the gate layer away from the substrate toward the semiconductor layer includes:

[0024] The orthographic projection of the conductive area on the substrate and the orthographic projection of the second surface on the substrate are arranged in a staggered manner.

[0025] According to an embodiment of the present application, an orthographic projection of the channel region on the substrate is located within an orthographic projection of the first surface on the substrate.

[0026] According to an embodiment of the present application, the step of forming an ion concentration buffer zone between the conductive region and the channel region includes:

[0027] The orthographic projection of the ion concentration buffer area on the substrate is offset from the orthographic projection of the first surface on the substrate, and the orthographic projection of the ion concentration buffer area on the substrate is located within the orthographic projection of the second surface on the substrate.

[0028] According to an embodiment of the present application, the step of forming a gate layer on a side of the semiconductor layer facing away from the substrate includes:

[0029] A first metal layer and a second metal layer are sequentially formed on a side of the semiconductor layer facing away from the substrate, and the first metal layer and the second metal layer are stacked.

[0030] The first metal layer and the second metal layer are patterned, and the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate to form a gate layer.

[0031] According to an embodiment of the present application, the acid corrosion resistance of the second metal layer is greater than that of the first metal layer, and the step of patterning the first metal layer and the second metal layer includes:

[0032] The first metal layer and the second metal layer are wet-etched by an acidic solvent so that the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate.

[0033] According to an embodiment of the present application, after the step of forming a gate layer on the side of the semiconductor layer facing away from the substrate, the method further includes:

[0034] A first sacrificial layer is formed on a side of the gate layer facing away from the substrate. In a first direction, two ends of an orthographic projection of the gate layer on the substrate are located within the orthographic projection of the first sacrificial layer on the substrate.

[0035] According to an embodiment of the present application, the step of performing ion implantation from the side of the gate layer away from the substrate toward the semiconductor layer includes:

[0036] The orthographic projection of the conductive region on the substrate and the orthographic projection of the first sacrificial layer on the substrate are arranged in a staggered manner.

[0037] According to an embodiment of the present application, the step of forming an ion concentration buffer region between the conductive region and the channel region includes:

[0038] The orthographic projection of the ion concentration buffer zone on the substrate is staggered with the orthographic projection of the gate layer on the substrate, and the orthographic projection of the ion concentration buffer zone on the substrate is located within the orthographic projection of the first sacrificial layer on the substrate.

[0039] According to an embodiment of the present application, the manufacturing method further includes: removing the first sacrificial layer.

[0040] According to an embodiment of the present application, after the step of forming a gate layer on the side of the semiconductor layer facing away from the substrate, the method further includes:

[0041] A second sacrificial layer is formed on the side of the gate layer facing away from the substrate. In the first direction, two ends of the orthographic projection of the second sacrificial layer on the substrate are located between the orthographic projections of the two conductive regions on the substrate and have a spacing therebetween.

[0042] The gate layer is patterned so that the orthographic projection of the gate layer on the substrate is equal to the orthographic projection of the second sacrificial layer on the substrate in the first direction, so that the two ends of the orthographic projection of the gate layer on the substrate in the first direction are located between the orthographic projections of the two channel regions on the substrate and have a spacing.

[0043] According to an embodiment of the present application, the manufacturing method further includes: removing the second sacrificial layer.

[0044] According to an embodiment of the present application, the step of forming an ion concentration buffer zone between the conductive region and the channel region includes:

[0045] The semiconductor layer is subjected to an annealing process to form an ion concentration buffer zone between the conductive region and the channel region.

[0046] In the embodiment of the present application, the gate layer includes a first surface facing the semiconductor layer, the orthographic projection of the channel region on the substrate is located within the orthographic projection of the first surface on the substrate, and the first surface can form a field effect with the semiconductor layer. In addition, an ion concentration buffer zone is provided between the channel region and the conductive region, thereby reducing the facing area between the first surface of the gate and the ion concentration buffer zone and the conductive region, reducing the generation of additional capacitance, thereby improving the process performance of the array substrate and the process performance of the display panel formed by the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features.

[0048] Figure 1 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0049] Figure 2is a schematic structural diagram of another array substrate provided in an embodiment of the present application;

[0050] Figure 3 is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0051] Figures 4 to 7 It is a schematic diagram of a manufacturing method of an array substrate provided in an embodiment of the present application;

[0052] Figures 8 to 10 is a schematic diagram of another method for manufacturing an array substrate provided in an embodiment of the present application;

[0053] Figure 11 to Figure 12 This is a schematic diagram of a process for manufacturing another array substrate provided in an embodiment of the present application.

[0054] Explanation of the reference numerals: 100, substrate; 200, semiconductor layer; 210, channel region; 220, ion concentration buffer region; 230, conductor region; 300, gate layer; 310, first surface; 320, second surface; 330, first metal layer; 340, second metal layer; 400, first sacrificial layer; 500, second sacrificial layer; 600, insulating layer; X, first direction; Y, thickness direction. DETAILED DESCRIPTION

[0055] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. In the accompanying drawings and the following description, at least some of the known structures and technologies are not shown to avoid unnecessary ambiguity in the present application; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0056] In the description of the present application, it should be noted that, unless otherwise specified, "multiple" means more than two; the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0057] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0058] like Figure 1 As shown, an array substrate provided by an embodiment of the first aspect of the present application includes: a substrate 100, a semiconductor layer 200 and a gate layer 300; the semiconductor layer 200 is arranged on one side of the substrate 100, the semiconductor layer 200 includes a channel region 210, an ion concentration buffer region 220 and a conductive region 230, the conductive region 230 is located at both ends of the channel region 210 along a first direction X, and the ion concentration buffer region 220 is located between the channel region 210 and the conductive region 230; the gate layer 300 is arranged on the side of the semiconductor layer 200 away from the substrate 100, the gate layer 300 includes a first surface 310 on one side facing the semiconductor layer 200, and the orthographic projection of the channel region 210 on the substrate 100 is located within the orthographic projection of the first surface 310 on the substrate 100; the first direction X is arranged to intersect with the thickness direction Y of the substrate 100.

[0059] In this embodiment, the conductive region 230 is located at both ends of the channel region 210 along the first direction X, and the ion concentration buffer region 220 is located between the channel region 210 and the conductive region 230, that is, the ion concentration buffer region 220 is located at both ends of the channel region 210 along the first direction X. The gate layer 300 includes a first surface 310 on one side facing the semiconductor layer 200, and the orthographic projection of the channel region 210 on the substrate 100 is located within the orthographic projection of the first surface 310 on the substrate 100. The first surface 310 can form a field effect with the semiconductor layer 200. In addition, the ion concentration buffer region 220 is further provided between the channel region 210 and the conductive region 230, thereby reducing the facing area between the first surface 310 of the gate and the ion concentration buffer region 220 and the conductive region 230, reducing the generation of additional capacitance, which is conducive to reducing power consumption. At the same time, due to the existence of the ion concentration buffer region 220, it is easy to design and implement a short channel device, thereby improving the process performance of the array substrate and the process performance of the display panel formed by the array substrate.

[0060] In the related art, when the semiconductor layer 200 is subjected to an annealing process, the ions in the conductive region 230 will diffuse toward the channel region 210. When the ions diffuse to the channel region 210, additional capacitance will be generated between the gate and the gate, affecting the performance of the display product. In the embodiment of the present application, an ion concentration buffer region 220 is provided between the conductive region 230 and the channel region 210. When the semiconductor layer 200 is subjected to an annealing process, the ion concentration buffer region 220 is provided between the conductive region 230 and the channel region 210 to reduce the ions in the conductive region 230 from directly entering the channel region 210, thereby improving the process performance of the array substrate.

[0061] Optional, such as Figure 1 As shown, the region of the semiconductor layer 200 opposite to the first surface 310 can generate a field effect, and the region of the semiconductor layer 200 opposite to the first surface 310 is the channel region 210 .

[0062] Optional, such as Figure 1 As shown, an insulating layer 600 is disposed between the semiconductor layer 200 and the gate layer 300 .

[0063] like Figure 1 As shown, in some optional embodiments, the gate layer 300 includes a second surface 320 facing away from the semiconductor layer 200 , and both ends of the orthographic projection of the first surface 310 on the substrate 100 along the first direction X are located within the orthographic projection of the second surface 320 on the substrate 100 .

[0064] In these optional embodiments, along the first direction X, the length of the first surface 310 is smaller than the second surface 320. When ion implantation is performed on the semiconductor layer 200, the second surface 320 is used as a mask layer to form conductive regions 230 located at both ends of the semiconductor layer 200 along the first direction X. The orthographic projection of the conductive region 230 on the substrate 100 and the orthographic projection of the second surface 320 on the substrate 100 are staggered. Since the length of the first surface 310 along the first direction X is smaller than the second surface 320, there is a distance between the conductive region 230 and the first surface 310 along the first direction X, and the distance is arranged opposite to the ion concentration buffer region 220. In the process of annealing the semiconductor layer 200 to form the ion concentration buffer region 220, ions in the conductive region 230 diffuse toward the middle to form the ion concentration buffer region 220. The ion concentration buffer region 220 diffuses from the edge of the first surface 310 to the edge of the second surface 320, thereby avoiding the ion concentration buffer region 220 from being opposite to the first surface 310, thereby reducing the generation of additional capacitance. Optionally, the orthographic projection of the conductive area 230 on the substrate 100 and the orthographic projection of the second surface 320 on the substrate 100 may be staggered so that the orthographic projection of the conductive area 230 on the substrate 100 and the orthographic projection of the second surface 320 on the substrate 100 do not overlap, that is, there is no overlapping area. Alternatively, the orthographic projection of the conductive area 230 on the substrate 100 and the orthographic projection of the second surface 320 on the substrate 100 may overlap partially but not completely.

[0065] like Figure 1 As shown, in some optional embodiments, the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 is offset from the orthographic projection of the first surface 310 on the substrate 100, and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 is located within the orthographic projection of the second surface 320 on the substrate 100.

[0066] In these optional embodiments, the ion concentration buffer zone 220 diffuses from the edge of the first surface 310 to the edge of the second surface 320, and the ion concentration buffer zone 220 and the orthographic projection of the first surface 310 on the substrate 100 are staggered, thereby avoiding the ion concentration buffer zone 220 from being opposite to the first surface 310 and reducing the generation of additional capacitance.

[0067] Optionally, the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 and the orthographic projection of the first surface 310 on the substrate 100 may be misaligned so that the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 and the orthographic projection of the first surface 310 on the substrate 100 do not overlap, that is, there is no overlapping area. Alternatively, the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 and the orthographic projection of the first surface 310 on the substrate 100 may overlap partially but not completely.

[0068] like Figure 1As shown, in some optional embodiments, the gate layer 300 includes a first metal layer 330 and a second metal layer 340 stacked in a direction away from the substrate 100, and in the first direction X, both ends of the orthographic projection of the first metal layer 330 on the substrate 100 are located within the orthographic projection of the second metal layer 340 on the substrate 100.

[0069] In these optional embodiments, the first metal layer 330 and the second metal layer 340 are stacked to form the gate layer 300, the first metal forms the first surface 310, the second metal forms the second surface 320, the two ends of the orthographic projection of the first metal layer 330 on the substrate 100 along the first direction X are located within the orthographic projection of the second metal layer 340 on the substrate 100, and the cross section of the gate layer 300 along the first direction X and perpendicular to the substrate 100 is an inverted trapezoidal structure. The projection area of ​​the second metal layer 340 on the substrate 100 is the mask projection area during ion implantation. The first metal layer 330 is directly opposite to the semiconductor layer 200 to form a field effect.

[0070] Optional, such as Figure 1 As shown, the orthographic projection of the first metal layer 330 on the substrate 100 is located within the orthographic projection of the second metal layer 340 on the substrate 100 , and the first metal layer 330 and the second metal layer 340 form a prism structure.

[0071] Optionally, the acid corrosion resistance of the second metal layer 340 is greater than that of the first metal layer 330, so that when an acidic solvent is used, the first metal layer 330 corrodes faster, thereby forming an orthographic projection of the first metal layer 330 on the substrate 100, where both ends along the first direction X are located within the orthographic projection of the second metal layer 340 on the substrate 100, or the orthographic projection of the first metal layer 330 on the substrate 100 is located within the orthographic projection of the second metal layer 340 on the substrate 100.

[0072] Optionally, the first metal layer 330 includes aluminum or titanium, and the second metal layer 340 includes molybdenum. Aluminum and titanium are less resistant to acid corrosion than molybdenum.

[0073] like Figure 2 As shown, in some other optional embodiments, the orthographic projection of the gate layer 300 on the substrate 100 and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 are offset.

[0074] In these optional embodiments, the orthographic projection of the gate layer 300 on the substrate 100 is located between the two ion concentration buffer zones 220 along the first direction X, and is offset from the orthographic projection of the ion concentration buffer zone 220 on the substrate 100, thereby avoiding the ion concentration buffer zone 220 from being opposite to the first surface 310 and reducing the generation of additional capacitance.

[0075] Optionally, the orthographic projection of the gate layer 300 on the substrate 100 and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 may be staggered so that the orthographic projection of the gate layer 300 on the substrate 100 and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 do not overlap, that is, there is no overlapping area. Alternatively, the orthographic projection of the gate layer 300 on the substrate 100 and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 may overlap partially but not completely.

[0076] Optional, such as Figure 2 As shown, the gate layer 300 includes a second surface 320 on a side away from the semiconductor layer 200, and in the first direction X, both ends of the orthographic projection of the second surface 320 on the substrate 100 are located within the orthographic projection of the first surface 310 on the substrate 100. Along the first direction X, the length of the first surface 310 is greater than the second surface 320, and the cross-section of the gate layer 300 along the first direction X and the direction perpendicular to the substrate 100 is a positive trapezoidal structure.

[0077] The embodiment of the second aspect of the present application further provides a display device, comprising an array substrate of any of the above-mentioned embodiments of the first aspect. Since the display device provided by the embodiment of the second aspect of the present application comprises the array substrate of any of the above-mentioned embodiments of the first aspect, the display device provided by the embodiment of the second aspect of the present application has the beneficial effects of the array substrate of any of the above-mentioned embodiments of the first aspect, which will not be described in detail here.

[0078] The display device in the embodiments of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0079] The third aspect of the present application also provides a method for manufacturing an array substrate. Figure 3 As shown, the following steps are included:

[0080] Step S01: Figure 4 As shown, a semiconductor layer 200 is formed on one side of a substrate 100 .

[0081] Step S02: Figure 5 As shown, the gate layer 300 is formed on the side of the semiconductor layer 200 facing away from the substrate 100 , and in the first direction X, both ends of the orthographic projection of the gate layer 300 on the substrate 100 are located within the orthographic projection of the semiconductor layer 200 on the substrate 100 .

[0082] Step S03: Figure 6As shown, ion implantation is performed from the side of the gate layer 300 away from the substrate 100 toward the semiconductor layer 200 to form a channel region 210 and conductive regions 230 located on both sides of the channel region 210 along the first direction X in the semiconductor layer 200 .

[0083] Step S04: Figure 1 As shown, an ion concentration buffer region 220 is formed between the conductive region 230 and the channel region 210 .

[0084] In the present embodiment, in the ion implantation process of the semiconductor layer 200, the gate layer 300 is used as a mask layer, and the two ends of the orthographic projection of the gate layer 300 on the substrate 100 along the first direction X are located within the orthographic projection of the semiconductor layer 200 on the substrate 100, thereby leaking out of the two ends of the semiconductor layer 200 along the first direction X, and ions are implanted into the two ends of the semiconductor layer 200 to form the conductive area 230. Since the middle of the semiconductor layer 200 is blocked by the gate layer 300, ions are not implanted, thereby forming the channel area 210, and finally, the ion concentration buffer area 220 is formed between the conductive area 230 and the channel area 210. Since there is the ion concentration buffer area 220 between the conductive area 230 and the channel area 210, the ions in the conductive area 230 will first enter the ion concentration buffer area 220 during the diffusion process, and will not directly enter the channel area 210, thereby reducing the area of ​​the gate layer 300 facing the ion concentration buffer area 220 and the conductive area 230 where the ions exist, and reducing the generation of additional capacitance. Furthermore, the gate electrode can be used as a mask layer to simplify the process without the need to set up an additional mask layer.

[0085] In some optional embodiments, in step S02, as Figure 5 As shown, including:

[0086] A gate material layer is formed on a side of the semiconductor layer 200 facing away from the substrate 100 .

[0087] The patterned gate material layer forms a gate layer 300, which includes a first surface 310 on a side facing the semiconductor layer 200 and a second surface 320 on a side facing away from the semiconductor layer 200. In the first direction X, both ends of the orthographic projection of the first surface 310 on the substrate 100 are located within the orthographic projection of the second surface 320 on the substrate 100.

[0088] In these optional embodiments, the first surface 310 is the side of the gate layer 300 facing the semiconductor layer 200, so that a field effect is formed between the first surface 310 and the semiconductor layer 200. The two ends of the orthographic projection of the first surface 310 on the substrate 100 along the first direction X are located within the orthographic projection of the second surface 320 on the substrate 100, that is, the length of the first surface 310 along the first direction X is smaller than that of the second surface 320. When ion implantation is performed on the semiconductor layer 200, the second surface 320 is used as a mask layer to form the conductive area 230 located at the two ends of the semiconductor layer 200 along the first direction X. The orthographic projection of the conductive area 230 on the substrate 100 is staggered with the orthographic projection of the second surface 320 on the substrate 100. Since the length of the first surface 310 along the first direction X is smaller than that of the second surface 320, there is a distance between the conductive area 230 and the first surface 310 along the first direction X, and the distance is arranged relative to the ion concentration buffer area 220. During the process of annealing the semiconductor layer 200 to form the ion concentration buffer zone 220, the ions in the conductive region 230 diffuse toward the middle to form the ion concentration buffer zone 220. The ion concentration buffer zone 220 diffuses from the edge of the first surface 310 to the edge of the second surface 320, thereby avoiding the ion concentration buffer zone 220 from being opposite to the first surface 310 and reducing the generation of additional capacitance.

[0089] Optionally, in step S03, if Figure 6 As shown, including:

[0090] The orthographic projection of the conductive region 230 on the substrate 100 and the orthographic projection of the second surface 320 on the substrate 100 are arranged in a staggered manner.

[0091] When ion implantation is performed on the semiconductor layer 200, the second surface 320 is used as a mask layer to form conductive areas 230 located at both ends of the semiconductor layer 200 along the first direction X, so that the conductive areas 230 and the second surface 320 are staggered, and the orthographic projection of the conductive areas 230 on the substrate 100 and the orthographic projection of the first surface 310 on the substrate 100 are spaced apart along the first direction X to form the ion concentration buffer area 220.

[0092] Optional, such as Figure 1 As shown, the orthographic projection of the channel region 210 on the substrate 100 is located within the orthographic projection of the first surface 310 on the substrate 100 .

[0093] The channel region 210 is disposed opposite to the first surface 310 so as to form a field effect. The portion where the orthographic projection of the semiconductor layer 200 on the substrate 100 overlaps with the orthographic projection of the first surface 310 on the substrate 100 is the channel region 210 .

[0094] Optionally, in step S04, Figure 1 As shown, including:

[0095] The orthographic projection of the ion concentration buffer zone 220 on the substrate 100 is offset from the orthographic projection of the first surface 310 on the substrate 100 , and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 is located within the orthographic projection of the second surface 320 on the substrate 100 .

[0096] The ion concentration buffer zone 220 diffuses from the edge of the first surface 310 to the edge of the second surface 320 , and the ion concentration buffer zone 220 and the orthographic projection of the first surface 310 on the substrate 100 are staggered, thereby avoiding the ion concentration buffer zone 220 and the first surface 310 being opposite to each other and reducing the generation of additional capacitance.

[0097] In some optional embodiments, in step S02, it includes:

[0098] like Figure 7 As shown, a first metal layer 330 and a second metal layer 340 are sequentially formed on a side of the semiconductor layer 200 facing away from the substrate 100 , and the first metal layer 330 and the second metal layer 340 are stacked.

[0099] like Figure 5 As shown, the first metal layer 330 and the second metal layer 340 are patterned, and the orthographic projection of the first metal layer 330 on the substrate 100 is located within the orthographic projection of the second metal layer 340 on the substrate 100 to form the gate layer 300 .

[0100] In these optional embodiments, the first metal and the second metal layer 340 are stacked to form the gate layer 300, the first metal forms the first surface 310, the second metal forms the second surface 320, the two ends of the orthographic projection of the first metal layer 330 on the substrate 100 along the first direction X are located within the orthographic projection of the second metal layer 340 on the substrate 100, and the cross section of the gate layer 300 along the first direction X and perpendicular to the substrate 100 forms an inverted trapezoidal structure. The projection area of ​​the second metal layer 340 on the substrate 100 is the mask projection area during ion implantation. The first metal layer 330 and the semiconductor layer 200 are directly opposite to form a field effect. The difference in length of the first metal layer 330 and the second metal layer 340 along the first direction X is the length of the ion concentration buffer zone 220 formed by the ion diffusion of the conductive area 230.

[0101] Optionally, the acid corrosion resistance of the second metal layer 340 is greater than that of the first metal layer 330, and the step of patterning the first metal layer 330 and the second metal layer 340 includes:

[0102] like Figure 5 As shown, the first metal layer 330 and the second metal layer 340 are wet-etched by an acidic solvent so that the orthographic projection of the first metal layer 330 on the substrate 100 is located within the orthographic projection of the second metal layer 340 on the substrate 100 .

[0103] The orthographic projections of the first metal layer 330 and the second metal layer 340 on the substrate 100 are overlapped by patterning. During the wet etching process using an acidic solvent, the corrosion rate of the first metal layer 330 is greater than the corrosion rate of the second metal layer 340, so that the orthographic projection of the first metal layer 330 on the substrate 100 is located within the orthographic projection of the second metal layer 340 on the substrate 100.

[0104] like Figure 8 As shown, in some optional embodiments, after step S02, it also includes: forming a first sacrificial layer 400 on the side of the gate layer 300 facing away from the substrate 100, and in the first direction X, both ends of the orthographic projection of the gate layer 300 on the substrate 100 are located within the orthographic projection of the first sacrificial layer 400 on the substrate 100.

[0105] In these optional embodiments, the first sacrificial layer 400 is formed on the side of the gate layer 300 facing away from the substrate 100, and both ends of the orthographic projection of the gate layer 300 on the substrate 100 along the first direction X are located within the orthographic projection of the first sacrificial layer 400 on the substrate 100, that is, the length of the gate layer 300 along the first direction X is less than the length of the first sacrificial layer 400 along the first direction X, so that the first sacrificial layer 400 can be used as a mask layer in the ion implantation process. When the ion implantation is performed, the ions are implanted into both ends of the semiconductor layer 200 in the first direction X to form the conductive area 230, and the semiconductor layer 200 outside the portion blocked by the first sacrificial layer 400 forms the conductive area 230, so that there is a distance between the conductive area 230 and the gate layer 300 along the first direction X, so that the ions will not directly enter the channel area 210 during ion diffusion, thereby reducing the generation of additional capacitance.

[0106] Optionally, in step S03, if Fig. 9 As shown, the orthographic projection of the conductive area 230 on the substrate 100 and the orthographic projection of the first sacrificial layer 400 on the substrate 100 are staggered.

[0107] During ion implantation, the portion of the semiconductor layer 200 shielded by the first sacrificial layer 400 will not be implanted with ions, so that the orthographic projection of the conductive region 230 on the substrate 100 and the orthographic projection of the first sacrificial layer 400 on the substrate 100 are offset, so that the conductive region 230 and the gate layer 300 are spaced apart along the first direction X.

[0108] Optionally, in step S04, Fig.10 As shown, the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 is staggered with the orthographic projection of the gate layer 300 on the substrate 100 , and the orthographic projection of the ion concentration buffer zone 220 on the substrate 100 is located within the orthographic projection of the first sacrificial layer 400 on the substrate 100 .

[0109] During the ion diffusion process of the conductive regions 230 at both ends toward the middle, the ion diffusion length of the conductive region 230 at one end is equal to the distance between one end of the first sacrificial layer 400 and one end of the gate layer 300, so that the orthographic projection of the ion concentration buffer region 220 formed by the ion diffusion on the substrate 100 is located within the orthographic projection of the first sacrificial layer 400 on the substrate 100 and is offset from the orthographic projection of the gate layer 300 on the substrate 100, so as to reduce the formation of additional capacitance caused by ion diffusion into the channel region 210.

[0110] Optional, such as Figure 2 As shown, the manufacturing method further includes: removing the first sacrificial layer 400 .

[0111] After the ion implantation process is completed, the first sacrificial layer 400 is removed to reduce the thickness of the array substrate.

[0112] In some optional embodiments, after step S02, the method further includes:

[0113] like Fig.11 As shown, a second sacrificial layer 500 is formed on the side of the gate layer 300 facing away from the substrate 100 . In the first direction X, two ends of the orthographic projection of the second sacrificial layer 500 on the substrate 100 are located between the orthographic projections of the two conductive regions 230 on the substrate 100 and have a spacing therebetween.

[0114] like Fig.12 As shown, the gate layer 300 is patterned so that the orthographic projection of the gate layer 300 on the substrate 100 is equal to the length of the orthographic projection of the second sacrificial layer 500 on the substrate 100 along the first direction X, so that the two ends of the orthographic projection of the gate layer 300 on the substrate 100 along the first direction X are located between the orthographic projections of the two channel regions 210 on the substrate 100 and have a spacing.

[0115] In these optional embodiments, the gate layer 300 serves as a mask layer for ion implantation into the semiconductor layer 200. Ions are implanted into the semiconductor layer 200 to form semiconductor layers 200 located on both sides of the gate layer 300 in the first direction X. In the subsequent ion diffusion process, ions diffuse into the region opposite to the semiconductor layer 200 and the gate layer 300 to form additional capacitance. The second sacrificial layer 500 is used as a mask layer for the patterning process of the gate layer 300. The two ends of the orthographic projection of the second sacrificial layer 500 on the substrate 100 along the first direction X are located between the orthographic projections of the two conductive areas 230 on the substrate 100 and have a spacing. The gate layer 300 is patterned by setting the second sacrificial layer 500 as a mask layer so that the orthographic projection of the gate layer 300 on the substrate 100 is equal to the length of the orthographic projection of the second sacrificial layer 500 on the substrate 100 along the first direction X, that is, the two ends of the orthographic projection of the gate layer 300 on the substrate 100 along the first direction X are located between the orthographic projections of the two channel areas 210 on the substrate 100 and have a spacing. When the ion diffusion process is performed, the ion diffusion will not directly enter the area opposite to the semiconductor layer 200 and the gate layer 300, but will be formed in the ion concentration buffer layer staggered on the gate layer 300.

[0116] Optional, such as Figure 2 As shown, the manufacturing method further includes: removing the second sacrificial layer 500. After the process of patterning the gate layer 300, the second sacrificial layer 500 is removed to reduce the thickness of the array substrate.

[0117] In some optional embodiments, in step S04, it includes:

[0118] The semiconductor layer 200 is subjected to an annealing process to form an ion concentration buffer region 220 between the conductive region 230 and the channel region 210 .

[0119] In these optional embodiments, the semiconductor layer 200 is subjected to an annealing process to improve the electrical performance and reliability of the transistor formed by the semiconductor layer 200. When the semiconductor layer 200 is subjected to an annealing process, the ions in the conductive region 230 diffuse toward the middle to form an ion concentration buffer region 220, and the ion concentration buffer region 220 is disposed at an offset position between the orthogonal projection of the substrate 100 and the orthogonal projection of the gate layer 300 on the substrate 100, or the ion concentration buffer region 220 is disposed at an offset position between the orthogonal projection of the substrate 100 and the orthogonal projection of the gate layer 300 on the substrate 100 on one side facing the substrate 100 to reduce the generation of additional capacitance, thereby improving the process performance of the array substrate.

[0120] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A semiconductor layer, disposed on one side of the substrate, the semiconductor layer comprising a channel region, an ion concentration buffer region and a conductive region, the conductive region being located at two ends of the channel region along a first direction, and the ion concentration buffer region being located between the channel region and the conductive region; A gate layer is disposed on a side of the semiconductor layer away from the substrate, the gate layer includes a first surface facing the semiconductor layer, and an orthographic projection of the channel region on the substrate is located within an orthographic projection of the first surface on the substrate; The first direction is arranged to intersect with the thickness direction of the substrate.

2. The array substrate according to claim 1, characterized in that: The gate layer comprises a second surface facing away from the semiconductor layer, and two ends of an orthographic projection of the first surface on the substrate along the first direction are located within an orthographic projection of the second surface on the substrate; Preferably, the orthographic projection of the ion concentration buffer area on the substrate is staggered with the orthographic projection of the first surface on the substrate, and the orthographic projection of the ion concentration buffer area on the substrate is located within the orthographic projection of the second surface on the substrate; Preferably, the gate layer comprises a first metal layer and a second metal layer stacked in a direction away from the substrate, and in the first direction, two ends of an orthographic projection of the first metal layer on the substrate are located within an orthographic projection of the second metal layer on the substrate; Preferably, the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate; Preferably, the acid corrosion resistance of the second metal layer is greater than that of the first metal layer; Preferably, the first metal layer includes aluminum or titanium, and the second metal layer includes molybdenum.

3. The array substrate according to claim 1, characterized in that: The orthographic projection of the gate layer on the substrate and the orthographic projection of the ion concentration buffer zone on the substrate are arranged in a staggered manner; Preferably, the gate layer includes a second surface facing away from the semiconductor layer, and in the first direction, two ends of an orthographic projection of the second surface on the substrate are located within the orthographic projection of the first surface on the substrate.

4. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 3.

5. A method for manufacturing an array substrate, characterized in that: include: forming a semiconductor layer on one side of the substrate; forming a gate layer on a side of the semiconductor layer away from the substrate, wherein two ends of an orthographic projection of the gate layer on the substrate are located within an orthographic projection of the semiconductor layer on the substrate in a first direction; Performing ion implantation from a side of the gate layer away from the substrate toward the semiconductor layer to form a channel region and conductive regions located on both sides of the channel region along a first direction in the semiconductor layer; An ion concentration buffer zone is formed between the conductive region and the channel region.

6. The manufacturing method according to claim 5, characterized in that: The step of forming a gate layer on the side of the semiconductor layer facing away from the substrate includes: forming a gate material layer on a side of the semiconductor layer facing away from the substrate; Patterning the gate material layer to form the gate layer, the gate layer comprising a first surface facing the semiconductor layer and a second surface facing away from the semiconductor layer, in the first direction, two ends of an orthographic projection of the first surface on the substrate are located within an orthographic projection of the second surface on the substrate; Preferably, the step of performing ion implantation from the side of the gate layer away from the substrate toward the semiconductor layer comprises: The orthographic projection of the conductive area on the substrate and the orthographic projection of the second surface on the substrate are arranged in a staggered manner; Preferably, the orthographic projection of the channel region on the substrate is located within the orthographic projection of the first surface on the substrate; Preferably, the step of forming an ion concentration buffer zone between the conductor region and the channel region comprises: The orthographic projection of the ion concentration buffer zone on the substrate is offset from the orthographic projection of the first surface on the substrate, and the orthographic projection of the ion concentration buffer zone on the substrate is located within the orthographic projection of the second surface on the substrate.

7. The manufacturing method according to claim 5, characterized in that: The step of forming a gate layer on a side of the semiconductor layer facing away from the substrate includes: Forming a first metal layer and a second metal layer in sequence on a side of the semiconductor layer facing away from the substrate, wherein the first metal layer and the second metal layer are stacked; patterning the first metal layer and the second metal layer, wherein an orthographic projection of the first metal layer on the substrate is located within an orthographic projection of the second metal layer on the substrate to form the gate layer; Preferably, the acid corrosion resistance of the second metal layer is greater than that of the first metal layer, and the step of patterning the first metal layer and the second metal layer comprises: The first metal layer and the second metal layer are wet-etched by an acidic solvent so that the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate.

8. The manufacturing method according to claim 5, characterized in that: After the step of forming a gate layer on the side of the semiconductor layer away from the substrate, the method further includes: forming a first sacrificial layer on a side of the gate layer away from the substrate, wherein in the first direction, two ends of an orthographic projection of the gate layer on the substrate are located within an orthographic projection of the first sacrificial layer on the substrate; Preferably, the step of performing ion implantation from the side of the gate layer away from the substrate toward the semiconductor layer comprises: The orthographic projection of the conductive area on the substrate and the orthographic projection of the first sacrificial layer on the substrate are arranged in a staggered manner; Preferably, the step of forming an ion concentration buffer region between the conductor region and the channel region comprises: The orthographic projection of the ion concentration buffer zone on the substrate is staggered with the orthographic projection of the gate layer on the substrate, and the orthographic projection of the ion concentration buffer zone on the substrate is located within the orthographic projection of the first sacrificial layer on the substrate; Preferably, the manufacturing method further comprises: removing the first sacrificial layer.

9. The manufacturing method according to claim 5, characterized in that: After the step of forming a gate layer on the side of the semiconductor layer away from the substrate, the method further includes: A second sacrificial layer is formed on a side of the gate layer away from the substrate, wherein in the first direction, two ends of an orthographic projection of the second sacrificial layer on the substrate are located between orthographic projections of the two conductive regions on the substrate and have a spacing therebetween; Patterning the gate layer so that the orthographic projection of the gate layer on the substrate and the orthographic projection of the second sacrificial layer on the substrate have the same length along the first direction, so that in the first direction, two ends of the orthographic projection of the gate layer on the substrate are located between the orthographic projections of the two channel regions on the substrate and have a spacing therebetween; Preferably, the manufacturing method further comprises: removing the second sacrificial layer.

10. The manufacturing method according to claim 5, characterized in that: The step of forming an ion concentration buffer zone between the conductor region and the channel region includes: An annealing process is performed on the semiconductor layer to form the ion concentration buffer region between the conductive region and the channel region.

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