Array substrate and preparation method thereof, display panel and display device

Abstract

The invention provides an array substrate and a preparation method thereof, a display panel and a display device.The array substrate comprises a substrate, an active layer, a first driving transistor and a first switching transistor, the active layer is arranged on one side of the substrate, the control end of the first driving transistor is electrically connected to a first node, and the control end of the first switching transistor is electrically connected to a second node; a first pole of the first switching transistor is electrically connected to a second pole of the first driving transistor, a second pole of the first switching transistor is electrically connected to a first node, and the first switching transistor comprises a first sub-switching transistor and a second sub-switching transistor. The first sub-switch transistor comprises a first channel part located in the active layer, the second sub-switch transistor comprises a second channel part located in the active layer, a gap exists between the orthographic projection of the first channel part on the substrate and the orthographic projection of the second channel part on the substrate, and the resistivity of the first channel part is smaller than that of the second channel part.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] With the continuous development of display technologies, such as liquid crystal display (LCD) and organic light-emitting diode (OLED) displays, display panels are widely used in various industries. However, current display panels may still have screen flickering problems during use, affecting the user's viewing experience. Summary of the invention

[0003] The embodiments of the present application provide an array substrate and a method for manufacturing the same, a display panel, and a display device, which can improve the problem of screen flickering.

[0004] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate comprising a substrate, an active layer, a first driving transistor and a first switching transistor, the active layer being arranged on one side of the substrate, the control end of the first driving transistor being electrically connected to a first node, the first electrode of the first switching transistor being electrically connected to the second electrode of the first driving transistor, the second electrode of the first switching transistor being electrically connected to the first node, and the first switching transistor comprising a first sub-switch transistor and a second sub-switch transistor.

[0005] The first sub-switch transistor includes a first channel portion located in the active layer, and the second sub-switch transistor includes a second channel portion located in the active layer, the first channel portion is electrically connected to the second electrode of the first switch transistor, the second communication portion is electrically connected to the first electrode of the first switch transistor, and there is a gap between the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate, wherein the resistivity of the first channel portion is less than the resistivity of the second channel portion.

[0006] In the second aspect, an embodiment of the present application provides a display panel, which includes an array substrate in any of the foregoing embodiments and a plurality of sub-pixels, the array substrate includes a plurality of pixel circuits, the pixel circuit includes a first driving transistor and a first switching transistor, and the pixel circuit is used to control the light emission of the sub-pixels.

[0007] In a third aspect, an embodiment of the present application provides a display device, which includes a display panel in any of the aforementioned embodiments.

[0008] In a fourth aspect, an embodiment of the present application provides a method for preparing an array substrate, wherein the array substrate includes a first switch transistor and a first drive transistor, wherein the control terminal of the first drive transistor is electrically connected to a first node, the first electrode of the first switch transistor is electrically connected to the second electrode of the first drive transistor, the second electrode of the first switch transistor is electrically connected to the first node, and the first switch transistor includes a first sub-switch transistor and a second sub-switch transistor. The preparation method includes:

[0009] forming an active layer on one side of the substrate;

[0010] The first channel portion is subjected to plasma treatment.

[0011] The embodiments of the present application provide an array substrate and a preparation method thereof, a display panel, and a display device. Since the first channel portion is located between the first node and the fifth node and has a strong conductive ability, when there is a certain voltage difference between the fifth node and the first node, the current can flow quickly from the fifth node to the first node through the first channel portion, thereby making the potential at the first node consistent with the potential at the fifth node in a short time, thereby reducing the leakage degree between the first node and the fifth node in the light-emitting stage, reducing the flickering degree of the display screen, and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 is a schematic diagram of a top view structure of a part of a film layer in an array substrate provided in an embodiment of the present application;

[0014] Figure 2 yes Figure 1 A schematic diagram of the amplified structure at the first switch transistor;

[0015] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at AA in the middle;

[0016] Figure 4 is a circuit diagram of a pixel circuit in an array substrate provided in an embodiment of the present application;

[0017] Figure 5 yes Figure 4 The timing diagram corresponding to the circuit structure shown;

[0018] Figure 6 yes Figure 1 A schematic diagram of the amplified structure at the second switch transistor;

[0019] Figure 7 is a schematic cross-sectional structure diagram of another array substrate provided in an embodiment of the present application;

[0020] Figure 8 is a schematic diagram of a top view structure of a portion of a film layer in another array substrate provided in an embodiment of the present application;

[0021] Fig. 9 is a schematic diagram of an enlarged structure of a first switch transistor of another array substrate provided in an embodiment of the present application;

[0022] Fig.10 It is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0023] Fig.11 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0024] Fig.12 It is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application.

[0025] Marking Description:

[0026] 100, array substrate; 200, display panel; 300, display device;

[0027] 10. Pixel circuit;

[0028] 20. substrate;

[0029] 30. active layer; 31. first channel portion; 32. second channel portion; 33. third channel portion; 34. fourth channel portion; 35. fifth channel portion; 36. first active structure;

[0030] 40, first conductive layer; 41, first sub-control terminal; 42, second sub-control terminal; 43, third sub-control terminal; 44, fourth sub-control terminal;

[0031] 50, storage capacitor; 51, first plate; 52, second plate;

[0032] 60, sub-pixel;

[0033] 70. A second conductive layer;

[0034] T3, first driving transistor; T4, first switching transistor; T41, first sub-switching transistor; T42, second sub-switching transistor; T5, second switching transistor; T51, third sub-switching transistor; T52, fourth sub-switching transistor;

[0035] N1, first node; N3, third node; N4, fourth node; N5, fifth node. DETAILED DESCRIPTION

[0036] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0037] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0038] First, see Figures 1 to 5 The embodiment of the present application provides an array substrate 100, which includes a substrate 20, an active layer 30, a first driving transistor T3 and a first switching transistor T4. The active layer 30 is arranged on one side of the substrate 20. The control end of the first driving transistor T3 is electrically connected to the first node N1, the first electrode of the first switching transistor T4 is electrically connected to the second electrode of the first driving transistor T3, the second electrode of the first switching transistor T4 is electrically connected to the first node N1, and the first switching transistor T4 includes a first sub-switch transistor T41 and a second sub-switch transistor T42.

[0039] The first sub-switch transistor T41 includes a first channel portion 31 located in the active layer 30, and the second sub-switch transistor T42 includes a second channel portion 32 located in the active layer 30, the first channel portion 31 is electrically connected to the second electrode of the first switch transistor T4, and the second channel portion 32 is electrically connected to the first electrode of the first switch transistor T4, and there is a gap between the orthographic projection of the first channel portion 31 on the substrate 20 and the orthographic projection of the second channel portion 32 on the substrate 20, wherein the resistivity of the first channel portion 31 is less than the resistivity of the second channel portion 32.

[0040] The array substrate 100 is used for subsequent preparation to form a display panel, which includes but is not limited to a liquid crystal display panel and an organic light-emitting display panel. For the convenience of description, the embodiment of the present application takes the array substrate 100 being used to form an organic light-emitting display panel as an example for explanation.

[0041] The array substrate 100 includes a pixel circuit 10 . In the display panel 200 formed subsequently, the pixel circuit 10 is a circuit structure for controlling whether the sub-pixel 60 emits light. Figure 4 The figure shows a circuit diagram corresponding to the case where the pixel circuit 10 is 7T1C, that is, the pixel circuit 10 includes seven thin film transistors and one storage capacitor. Each thin film transistor includes a control terminal, a first electrode and a second electrode, and the control terminal is used to control whether the first electrode and the second electrode are turned on or off.

[0042] The pixel circuit 10 includes a first driving transistor T3, a first switching transistor T4 and five other switching transistors. Figure 1 and Figure 4 For example, the control terminal of the first driving transistor T3 is electrically connected to the first node N1, and the control terminal of the first driving transistor T3 can be reused as the first plate 51 of the storage capacitor 50, the first electrode of the first driving transistor T3 is electrically connected to the first power supply signal VDD, and the second electrode of the first driving transistor T3 is electrically connected to the first electrode of the first switching transistor T4. The control terminal of the first switching transistor T4 is electrically connected to the second scanning signal Scan2, and the second electrode of the first switching transistor T4 is electrically connected to the first node N1.

[0043] Figure 5 It corresponds to Figure 4 The circuit timing diagram, specifically, as Figure 1 , Figure 4 and Figure 5 As shown, within a frame time I, the pixel circuit 10 may include a reset stage, a charging stage and a light-emitting stage. The reset stage corresponds to the t1 period. In the reset stage, the second switching transistor T5 is turned on by the low level of the first scanning signal ScanN1, and the first reset signal Vref1 is applied to the first node N1, and the control end of the first driving transistor T3 and the first plate 51 of the storage capacitor 50 are reset.

[0044] The charging stage corresponds to the time period t2, at which the first switch transistor T4 is turned on by the low level of the second scan signal ScanN2, and the transistors T2 and T7 are turned on by the low level of the third scan signal ScanP. The data signal passes through the transistor T2, the first drive transistor T3 and the first switch transistor T4 to charge the first node N1 (i.e., the first plate 51 of the storage capacitor 50). The potential at the first node N1 increases, and the second reset signal Vref2 is applied to the anode 61 of the sub-pixel 60 to reset the anode 61 of the sub-pixel 60.

[0045] According to the characteristics of the first driving transistor T3, the potentials of the first node N1 and the third node N3 can increase to Vdata+Vth during the charging process. Vdata represents the voltage value of the data signal Data, and Vth represents the threshold voltage of the first driving transistor T3. Since the first driving transistor T3 is described by taking a PMOS transistor as an example, the threshold voltage Vth is a negative value.

[0046] The light-emitting stage is the t3 period, at this time, the transistor T1 and the transistor T6 are turned on by the low level of the light-emitting signal Emit, and the potential maintained at the first node N1 makes the first driving transistor T3 also turned on, the first power signal VDD is applied to the anode of the sub-pixel after passing through the transistor T1, the first driving transistor T3 and the transistor T6, and the second power signal VEE is applied to the cathode of the sub-pixel. Under the joint drive of the anode and cathode of the sub-pixel, the sub-pixel 60 realizes the light-emitting function.

[0047] It should be noted that in Figure 3 In the example, all thin film transistors are PMOS transistors (low level conduction, high level cut-off). In the actual pixel circuit 10, some or all of the transistors can be adjusted to NMOS transistors (high level conduction, low level cut-off). And according to different actual needs, the pixel circuit 10 can adopt Figure 1 The 7T1C circuit structure shown, or other circuit structures such as 8T1C may also be used, which is also not limited in the embodiments of the present application.

[0048] also, Figure 4The figure shows the situation where the transistor T7 and the second switch transistor T5 are respectively controlled by different scan signals. Of course, in other embodiments, the same scan signal can be applied to the control end of the second switch transistor T5 and the control end of the transistor T7 respectively. On this basis, in the reset stage, the conduction of the second switch transistor T5 and the transistor T7 can be controlled simultaneously to reset the anode of the sub-pixel while resetting the first node N1. In other words, the anode of the sub-pixel can be reset in the reset stage, or it can be reset in the charging stage. Similarly, in other embodiments, the control ends of the first switch transistor T4 and the transistor T2 can also be electrically connected to the same scan signal. The embodiments of the present application are not limited to this. For the convenience of description, the embodiments of the present application will be described later with Figure 4 The pixel circuit shown is introduced.

[0049] Further, the first switch transistor T4 includes a first sub-switch transistor T41 and a second sub-switch transistor T42, that is, the first switch transistor T4 is a dual-gate transistor. Specifically, the control terminal of the first switch transistor T4 includes a first sub-control terminal 41 located in the first sub-switch transistor T41 and a second sub-control terminal 42 located in the second sub-switch transistor T42, and the first sub-control terminal 41 and the second sub-control terminal 42 are electrically connected to the second scan signal ScanN2.

[0050] Compared with a single-gate transistor, setting the first switch transistor T4 as a double-gate transistor helps to reduce the leakage characteristics of the first switch transistor T4 itself. However, there is a fifth node N5 between the first sub-switch transistor T41 and the second sub-switch transistor T42. In the charging stage, the voltages at the fifth node N5 and the first node N1 are often the same or similar, and at the end of the charging stage, the level of the second scan signal ScanN2 will suddenly rise from a low level to a high level.

[0051] In the related art, the fifth node N5 itself is a less stable node, so the sudden change of the second scan signal ScanN2 will cause the voltage at the fifth node N5 to be coupled to a larger potential, so that there is a larger potential difference between the first node N1 and the fifth node N5. The generation of the potential difference will cause leakage between the first node N1 and the fifth node N5. Furthermore, since the structure between the first node N1 and the fifth node N5 is a semiconductor structure, it itself has a large resistivity, so the leakage process between the first node N1 and the fifth node N5 is relatively slow. During the light-emitting stage, a continuous and slow leakage will occur between the first node N1 and the fifth node N5, causing the display screen to flicker, affecting the actual display perception.

[0052] In view of this, the embodiment of the present application adjusts the resistivity of the first channel portion 31 in the first sub-switch transistor T41 to reduce the screen flickering problem. Specifically, the array substrate 100 includes a substrate 20 and an active layer 30 located on one side of the substrate 20. The substrate 20 is a film layer structure used to support the array substrate 100, and the active layer 30 is a film layer structure including semiconductor materials in the array substrate 100. The active layer 30 includes a first channel portion 31 and a second channel portion 32. The first channel portion 31 is a partial structure of the active layer 30 that overlaps with the orthographic projection of the first sub-control terminal 41 on the substrate 20, and the second channel portion 32 is a partial structure of the active layer 30 that overlaps with the orthographic projection of the second sub-control terminal 42 on the substrate 20. The first channel portion 31 and the second channel portion 32 are used to jointly form the channel structure of the first switch transistor T4.

[0053] It should be noted that the active layer 30 may have a variety of material compositions, which are not limited in the present application. For example, the first switch transistor T4 may be an IGZO (Indium Gallium Zinc Oxide)-TFT, in which case the material of the active layer 30 includes a metal oxide, or the first switch transistor T4 may be an LTPS (Low Temperature Poly-Silicon)-TFT, in which case the material of the active layer 30 includes low temperature polysilicon.

[0054] In addition, the array substrate 100 may include various other film layer structures in addition to the substrate 20 and the active layer 30 . The embodiment of the present application does not limit the specific film layer composition of the array substrate 100 .

[0055] In some optional embodiments, the array substrate 100 further includes a first conductive layer 40 located on the side of the active layer 30 away from the substrate 20, and an insulating layer located between the first conductive layer 40 and the active layer 30, and the first sub-control terminal 41 and the second sub-control terminal 42 of the first switch transistor T4 are both located in the first conductive layer 40. Figure 1 Only the arrangement of the active layer 30, the first conductive layer 40 and a few other cross-line structures corresponding to a local area of ​​the array substrate is shown.

[0056] The first channel portion 31 is electrically connected to the second electrode of the first switch transistor T4, that is, one end of the first channel portion 31 is electrically connected to the second electrode of the first driving transistor T3. The second communication portion is electrically connected to the first electrode of the first switch transistor T4, that is, one end of the second channel portion 32 is electrically connected to the first node N1. The first channel portion 31 and the second channel portion 32 are two separate structures, and there is a gap between the orthographic projection of the first channel portion 31 on the substrate 20 and the orthographic projection of the second channel portion 32 on the substrate 20.

[0057] On this basis, the embodiment of the present application adjusts the first channel portion 31 so that the resistivity of the first channel portion 31 is reduced. Among them, the embodiment of the present application does not limit how to reduce the resistivity of the first channel portion 31. For example, the resistivity of the first channel portion 31 can be reduced by adjusting the material composition in the first channel portion 31, or the corresponding doping concentration of the original material in the first channel portion 31 can be increased to reduce the resistivity of the first channel portion 31, or the resistivity of the first channel portion 31 can be reduced by other process methods.

[0058] Furthermore, the resistivity of the adjusted first channel portion 31 is less than the resistivity of the second channel portion 32. The resistivity is a parameter index that characterizes the corresponding conductivity of the structure. The smaller the resistivity, the stronger the conductivity of the first channel portion 31. Under this design, since the first channel portion 31 is located between the first node N1 and the fifth node N5 and the first channel portion 31 has a strong conductivity, when there is a certain voltage difference between the fifth node N5 and the first node N1, the current can quickly flow from the fifth node N5 to the first node N1 through the first channel portion 31, so that the potential at the first node N1 and the potential at the fifth node N5 are kept consistent in a short time, thereby reducing the leakage degree between the first node N1 and the fifth node N5 in the light-emitting stage, reducing the flickering degree of the display screen, and improving the display effect.

[0059] In some embodiments, the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32 .

[0060] Doping concentration refers to the chemical concentration of some impurities added to the material. These impurities can be atoms, ions, molecules or small particles. By adding impurities of different elements into the material, the properties of the material in terms of photoelectricity, heat, conductivity, magnetism, etc. can be changed.

[0061] The resistivity of the first channel portion 31 and the second channel portion 32 is usually closely related to the doping concentration. Specifically, the doping concentration of the first channel portion 31 is relatively high, which means that the concentration of impurities doped in the first channel portion 31 is relatively high. These impurities can provide or accept electrons, thereby increasing the number of carriers, reducing the resistivity, and making the first channel portion 31 have better conductivity. Similarly, if the doping concentration of the first channel portion 31 is relatively low, its corresponding resistivity will be relatively high, and the conductivity will be relatively poor compared to the first channel portion 31.

[0062] In the embodiment of the present application, by setting the doping concentration of the first channel portion 31 to be greater than the doping concentration of the second channel portion 32, the first channel portion 31 can have more impurities for providing or receiving electrons relative to the second channel portion 32, thereby increasing the number of carriers in the first channel portion 31, and making the first channel portion 31 have stronger conductivity. When there is a certain voltage difference between the fifth node N5 and the first node N1, the current can flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31, thereby improving the flickering problem of the display screen and improving the display effect.

[0063] It should be noted that the present embodiment does not limit the material type of the dopant in the first channel portion 31 and the second channel portion 32. Optionally, the first channel portion 31 and the second channel portion 32 may include the same dopant, such as boron ions.

[0064] Further, in some optional embodiments, during the preparation of the active layer 30, the first channel portion 31 and the second channel portion 32 may be doped at the corresponding positions at the same time, and then the first channel portion 31 may be additionally doped for a second time, so that the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32. Compared with the original preparation process, this design can improve the flicker problem of the display screen by only adding an additional doping process, has little effect on the preparation cost and preparation efficiency of the array substrate 100, and has strong practicality.

[0065] Further optionally, when performing an additional secondary doping treatment on the first channel portion 31, a sacrificial layer can be first formed on the active layer 30, the sacrificial layer is used to cover other structures in the active layer 30 except the first channel portion 31, and an opening structure for exposing the first channel portion 31 is provided on the sacrificial layer, and then a doping process is performed to make the doping concentration at the first channel portion 31 greater than the doping concentration at other positions in the active layer 30.

[0066] Of course, in other embodiments, the first channel portion 31 and the second channel portion 32 can also be formed by completely separate doping treatment, that is, the first channel portion 31 is doped only once, and the doping process corresponding to the first channel portion 31 is relatively independent of the doping process corresponding to the second channel portion 32, and the embodiments of the present application do not limit this.

[0067] In some embodiments, the doping concentration of the first channel portion 31 is E, and E satisfies: 10 12 Pieces / cm -3 ≤E≤10 15 Pieces / cm -3 . Optionally, E is 10 12 Pieces / cm -3 , 10 13Pieces / cm -3 , 5*10 13 Pieces / cm -3 , 15 14 Pieces / cm -3 and 10 15 Pieces / cm -3 one of them.

[0068] During the preparation of the active layer 30, the first channel portion 31 and the second channel portion 32 may be doped by ion implantation. Specifically, doping ions may be implanted into a portion of the active layer 30 in the form of an ion beam to form the first channel portion 31 and the second channel portion 32. On this basis, the doping concentrations corresponding to the first channel portion 31 and the second channel portion 32 are often related to the corresponding implantation energy and number of implantations during the ion implantation process.

[0069] In combination with the above content, it can be known that the first channel portion 31 can be subjected to a secondary ion implantation process, and the second channel portion 32 can be subjected to a single ion implantation process, so that the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32. Alternatively, only the first channel portion 31 and the second channel portion 32 can be subjected to a single ion implantation process, in which case the energy of the ion implantation corresponding to the first channel portion 31 needs to be greater than the energy of the ion implantation corresponding to the second channel portion 32, so that the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32.

[0070] Furthermore, when only one ion implantation process is used to dope the first channel portion 31, the energy of the corresponding ion beam is W, and W satisfies: 8Kev≤W≤25Kev. This design can make the doping concentration of the first channel portion 31 greater than the doping concentration of the second channel portion 32, and make E satisfy: 10 12 Pieces / cm -3 ≤E≤10 15 Pieces / cm -3 .

[0071] In the embodiment of the present application, the doping concentration E of the first channel portion 31 is limited to not less than 10 12 cm -3 , so that the first channel portion 31 has a smaller resistivity, thereby improving the corresponding conductivity of the first channel portion 31, and then when there is a certain voltage difference between the fifth node N5 and the first node N1, the current can quickly flow from the fifth node N5 to the first node N1 through the first channel portion 31, thereby improving the flicker problem of the display screen. At the same time, the doping concentration E of the first channel portion 31 is limited to not more than 10 15 cm -3, so that the first channel portion 31 is still in a semiconductor state, meeting the cut-off and on-control requirements of the first sub-switch transistor T41.

[0072] In some embodiments, the ratio of the doping concentration in the first channel portion 31 to the doping concentration in the second channel portion 32 is a, and a satisfies: 3≤a≤200. Optionally, a is one of 3, 10, 20, 50, 100, 150, and 200.

[0073] When other factors remain the same, the resistivity of the first channel portion 31 and the second channel portion 32 is negatively correlated with the corresponding doping concentration. When the doping concentrations of the first channel portion 31 and the second channel portion 32 remain the same or similar, the two will have the same or similar resistivity. On this basis, in the related art, when the fifth node N5 is coupled to a larger potential due to the sudden change of the second scan signal ScanN2, the voltage difference between the fifth node N5 and the first node N1 will cause slow leakage at the first channel portion 31, which is easy to cause flickering problems. The voltage difference between the fifth node N5 and the third node N3 will also cause slow leakage at the second channel portion 32, affecting the display accuracy.

[0074] In the embodiment of the present application, by setting the doping concentration in the first channel portion 31 to be greater than the doping concentration in the second channel portion 32, and setting the ratio a between the doping concentration in the first channel portion 31 and the doping concentration in the second channel portion 32 to be not less than 3, the first channel portion 31 has a smaller resistivity than the second channel portion 32. In this way, in addition to enabling the current to quickly flow from the fifth node N5 to the first node N1 through the first channel portion 31 to improve the flicker problem, more current can be made to flow from the fifth node N5 to the first node N1, rather than from the fifth node N5 to the third node N3, by means of the resistivity difference between the first channel portion 31 and the second channel portion 32, thereby reducing the leakage degree between the fifth node N5 and the third node N3 and improving the display accuracy. At the same time, a is set to be not more than 200, so that the first channel portion 31 is still in a semiconductor state, meeting the cut-off and conduction control requirements of the first sub-switch transistor T41.

[0075] In some embodiments, the first channel portion 31 is plasma treated.

[0076] Plasma treatment is a method of treating semiconductor materials in plasma. The ions in the plasma beam can sinter the surface of the material, remove impurities to reduce its resistivity, and increase its conductivity. Unlike ion implantation, which is the process of injecting doping ions into semiconductor materials, plasma treatment is the process of treating semiconductor materials.

[0077] In the embodiment of the present application, plasma treatment is performed on the first channel portion 31, which can also help reduce the resistivity of the first channel portion 31, so that the first channel portion 31 has stronger conductivity, thereby improving the flicker problem. Compared with the original preparation process, this design can improve the flicker problem of the display screen by only adding an additional process, which has little impact on the preparation cost and preparation efficiency of the array substrate 100, and has strong practicality.

[0078] In some embodiments, Figure 1 and Figure 2 As shown, the first driving transistor T3 includes a third channel portion 33 located in the active layer 30 , and the resistivity of the first channel portion 31 is smaller than the resistivity of the third channel portion 33 .

[0079] The third channel portion 33 is a portion of the active layer 30 that overlaps with the control terminal of the first driving transistor T3 on the substrate 20. Figure 1 It can be seen that the control end of the first driving transistor T3 can be reused as the first electrode 51 of the storage capacitor 50 and electrically connected to the first node N1. On this basis, the third channel portion 33 is a partial structure in the active layer 30 that overlaps with the orthographic projection of the first electrode 51 on the substrate 20.

[0080] Similar to the first channel portion 31, reducing the resistivity of the third channel portion 33 also helps to increase the current transfer rate, thereby reducing the flicker problem. However, increasing the resistivity of the third channel portion 33 will increase the conductivity of the third channel portion 33, which may easily cause the first driving transistor T3 to fail to turn off normally, resulting in a split screen problem on the display screen.

[0081] In view of this, the embodiment of the present application only adjusts the first channel portion 31, so that the resistivity of the first channel portion 31 is less than the resistivity of the first channel portion 31 and the second channel portion 32. In this way, the current can flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31, thereby improving the flickering problem of the display screen. And because the second channel portion 32 and the third channel portion 33 are not adjusted, the turn-off reliability of the first switch transistor T4 can be improved by means of the second channel portion 32, and the turn-off reliability of the first drive transistor T3 can be improved by means of the third channel portion 33, thereby meeting the normal operation requirements of the pixel circuit 10.

[0082] In some embodiments, see Figure 1 , Figure 4 as well as Figure 6The array substrate 100 also includes a second switch transistor T5, a first electrode of the second switch transistor T5 is electrically connected to the first node N1, the second switch transistor T5 includes a third sub-switch transistor T51 and a fourth sub-switch transistor T52, the third sub-switch transistor T51 includes a fourth channel portion 34 located in the active layer 30, the fourth sub-switch transistor includes a fifth channel portion 35 located in the active layer 30, the fourth channel portion 34 is electrically connected to the first electrode of the second switch transistor T5, the fifth channel portion 35 is electrically connected to the second electrode of the second switch transistor T5, there is a gap between the orthographic projection of the fourth channel portion 34 on the substrate 20 and the orthographic projection of the fifth channel portion 35 on the substrate 20, and the resistivity of the fourth channel portion 34 is less than the resistivity of the fifth channel portion 35.

[0083] In conjunction with the accompanying drawings, the control end of the second switch transistor T5 is electrically connected to the first scan signal line ScanN1, the first electrode of the second switch transistor T5 is electrically connected to the first node N1, and the second electrode of the second switch transistor T5 is electrically connected to the first reset signal Vref1. Further, in the reset phase, the second switch transistor T5 is turned on by the low level of the first scan signal ScanN1, the first reset signal Vref1 is applied to the first node N1, and the control end of the first drive transistor T3 and the first plate 51 of the storage capacitor 50 are reset.

[0084] Further, the second switch transistor T5 includes a third sub-switch transistor T51 and a fourth sub-switch transistor T52, that is, the second switch transistor T5 is a dual-gate transistor. Specifically, the control terminal of the second switch transistor T5 includes a third sub-control terminal 43 located in the third sub-switch transistor T51 and a fourth sub-control terminal 44 located in the fourth sub-switch transistor T52, and the third sub-control terminal 43 and the fourth sub-control terminal 44 are electrically connected to the first scan signal ScanN1.

[0085] Compared with a single-gate transistor, setting the second switch transistor T5 as a double-gate transistor helps to reduce the leakage characteristics of the second switch transistor T5 itself. However, there is a fourth node N4 between the third sub-switch transistor T51 and the fourth sub-switch transistor T52. In the reset phase, the voltages at the fourth node N4 and the first node N1 are often the same or similar, and at the end of the reset phase, the level of the first scan signal ScanN1 suddenly rises from a low level to a high level.

[0086] In the related art, similar to the fifth node N5, the fourth node N4 itself is a less stable node, so the sudden change of the first scan signal ScanN1 will cause the voltage at the fourth node N4 to be coupled to a larger potential, so that there is a larger potential difference between the first node N1 and the fourth node N4. The generation of the potential difference will cause leakage between the first node N1 and the fourth node N4. Furthermore, since the structure between the first node N1 and the fourth node N4 is a semiconductor structure, it itself has a large resistivity, so the leakage process between the first node N1 and the fourth node N4 is relatively slow. During the light-emitting stage, continuous and slow leakage will occur between the first node N1 and the fourth node N4, causing the display screen to flicker, affecting the actual display perception.

[0087] In view of this, the embodiment of the present application adjusts the resistivity of the fourth channel portion 34 in the second sub-switch transistor T42 to reduce the screen flickering problem. Specifically, the active layer 30 includes a fourth channel portion 34 and a fifth channel portion 35, the fourth channel portion 34 is a partial structure of the active layer 30 that overlaps with the orthographic projection of the third sub-control terminal on the substrate 20, and the fifth channel portion 35 is a partial structure of the active layer 30 that overlaps with the orthographic projection of the fourth sub-control terminal on the substrate 20, and the fourth channel portion 34 and the fifth channel portion 35 are used to jointly form the channel structure of the second switch transistor T5.

[0088] The fourth channel portion 34 is electrically connected to the first electrode of the second switch transistor T5, that is, one end of the fourth channel portion 34 is electrically connected to the first node N1. The fifth communication portion is electrically connected to the second electrode of the second switch transistor T5, that is, one end of the fifth channel portion 35 is electrically connected to the first reset signal Vref1. The fourth channel portion 34 and the fifth channel portion 35 are two separate structures, and there is a gap between the orthographic projection of the fourth channel portion 34 on the substrate 20 and the orthographic projection of the fifth channel portion 35 on the substrate 20.

[0089] On this basis, the embodiment of the present application adjusts the fourth channel portion 34 so that the resistivity of the fourth channel portion 34 is reduced. Among them, the embodiment of the present application does not limit how to reduce the resistivity of the fourth channel portion 34. For example, the doping concentration of the fourth channel portion 34 can be increased by adjusting the number and energy of ion implantation, thereby reducing the resistivity of the fourth channel portion 34. Alternatively, the resistivity of the fourth channel portion 34 can be reduced by plasma treatment of the fourth channel portion 34. Optionally, the fourth channel portion 34 has the same or similar doping concentration as the first channel portion 31.

[0090] Furthermore, the resistivity of the adjusted fourth channel portion 34 is less than the resistivity of the fifth channel portion 35, so that the fifth channel portion 35 has a stronger conductivity. Under this design, since the fifth channel portion 35 is located between the first node N1 and the fourth node N4 and the fifth channel portion 35 has a stronger conductivity, when there is a certain voltage difference between the fourth node N4 and the first node N1, the current can flow quickly from the fourth node N4 to the first node N1 through the fourth channel portion 34, so that the potential at the first node N1 and the potential at the fourth node N4 are kept consistent in a short time, thereby reducing the leakage degree between the first node N1 and the fourth node N4 in the light-emitting stage, reducing the flickering degree of the display screen, and improving the display effect.

[0091] In some embodiments, see Figure 1 , Figure 2 , Figure 4 as well as Figure 7 The active layer 30 further includes a first active structure 36, and two ends of the first active structure 36 are respectively connected to the first channel portion 31 and the second channel portion 32. The array substrate 100 includes a shielding structure P, which is located on one side of the active layer 30 in the thickness direction of the substrate 20, and the orthographic projection of the shielding structure P on the substrate 20 overlaps with the orthographic projection of the first active structure 36 on the substrate 20, and the shielding structure P is used to transmit a normal voltage potential.

[0092] The first active structure 36 is a semiconductor structure located between the first channel portion 31 and the second channel portion 32 in the active layer 30. Optionally, the first active structure 36, the first channel portion 31 and the second channel portion 32 are an integrated structure. During the preparation process, different degrees of doping treatment is performed on the areas on both sides of the first active structure 36 to form the first channel portion 31 and the second channel portion 32 on both sides of the first active structure 36.

[0093] The first active structure 36 corresponds to the location of the fifth node N5. At the end of the charging stage, the level of the second scan signal ScanN2 will suddenly change from a low level to a high level. It can be seen from the accompanying drawings that the first sub-control terminal 41 and the second sub-control terminal 42 for receiving the second scan signal ScanN2 are relatively close to the first active structure 36. Therefore, in the related art, when the second scan signal ScanN2 suddenly changes, at least one of the first sub-control terminal 41 and the second sub-control terminal 42 will be coupled with the first active structure 36 and form a parasitic capacitor, causing the potential at the first active structure 36 to increase along with the second scan signal ScanN2, thereby causing a large difference between the potential of the active layer 30 at the first node N1 and the potential at the first active structure 36. Therefore, during the light-emitting stage, the first active structure 36 will continue to leak electricity to the structure of the active layer 30 at the first node N1 through the first channel portion 31, causing a screen flickering problem.

[0094] In the embodiment of the present application, in addition to improving the flicker problem by reducing the resistivity of the first channel portion 31, the flicker problem can also be improved by means of a shielding structure P. Specifically, a shielding structure P can be provided at a position corresponding to the first active structure 36 by adding a conductor structure or changing the layout of the original conductor structure in the array substrate 100. The shielding structure P is a conductor structure for shielding. The shielding structure P and the first active structure 36 can have a variety of positional relationships. For example, the shielding structure P can be located on the side of the first active structure 36 facing the substrate 20, or the shielding structure P can be located on the side of the first active structure 36 facing away from the substrate 20. The shielding structure P is used to transmit a constant voltage potential. The embodiment of the present application does not limit the specific signal type of the constant voltage potential. Optionally, the shielding structure P can be used to transmit the first power supply signal VDD.

[0095] In the embodiment of the present application, the shielding structure P is configured to transmit a normal voltage potential and to overlap the orthographic projection of the shielding structure P on the substrate 20 with the orthographic projection of the first active structure 36 on the substrate 20, thereby reducing the parasitic capacitance generated between at least one of the first sub-control terminal 41 and the second sub-control terminal 42 and the first active structure 36 with the shielding structure P. When the level at the second scan signal ScanN2 suddenly changes from a low level to a high level, the degree of change in the potential at the first active structure 36, i.e., the fifth node N5, is reduced, thereby reducing the potential difference between the first node N1 and the fifth node N5. This design can reduce the leakage degree between the first node N1 and the fifth node N5, thereby improving the flickering problem of the display screen.

[0096] In some embodiments, see Figure 2 , Figure 4 and Figure 8The array substrate 100 further includes a storage capacitor 50, which includes a first plate 51 located in the first conductive layer, and a second plate 52 located on the side of the first plate 51 away from the substrate, and the control ends of the first sub-switch transistor T41 and the second switch transistor T5 are located in the first conductive layer. The second plate 52 includes a shielding structure P.

[0097] The storage capacitor 50 includes a first electrode plate 51 and a second electrode plate 52, wherein the orthographic projection of the first electrode plate 51 on the substrate overlaps with the orthographic projection of the second electrode plate 52 on the substrate. The first electrode plate 51 is located on the side of the second electrode plate 52 facing the substrate, and the first electrode plate 51, the first sub-control terminal 41 and the second sub-control terminal 42 are all located in the first conductive layer. Among them, the first electrode plate 51 is electrically connected to the fifth node N5 and can be reused as the control terminal of the first driving transistor T3. On this basis, the channel portion of the first driving transistor T3 is a partial structure in the active layer 30 at the overlapping area with the orthographic projection of the first electrode plate 51 on the substrate. Among them, Figure 8 Only the arrangement of the active layer 30, the first conductive layer 40, the second electrode plate 52 and a few other cross-line structures corresponding to the local area of ​​the array substrate is shown.

[0098] The second electrode plate 52 is a electrode plate in the storage capacitor 50 for electrically connecting to the first power signal VDD, and the first power signal VDD is a constant voltage potential. On this basis, the embodiment of the present application adjusts the size and layout of the second electrode plate 52 so that part of the structure in the second electrode plate 52 can be reused as a shielding structure P, wherein the shielding structure P is a part of the structure in the second electrode plate 52 whose corresponding orthographic projection is located outside the orthographic projection of the first electrode plate 51 on the substrate, and the orthographic projection of the shielding structure P on the substrate can overlap with the orthographic projection of the first active structure 36 on the substrate. Under this design, the shielding structure P can be formed without adding a new conductive layer in the array substrate 100, and the first power signal VDD can also be used to meet the need for the constant voltage potential required by the shielding structure P, thereby improving the problem of screen flickering and simplifying the preparation process of the array substrate 100, which has strong practicality.

[0099] It should be noted that the embodiment of the present application does not limit the specific positional relationship between the second electrode plate 52 and the first active structure 36. The orthographic projection of the second electrode plate 52 on the substrate 20 may overlap with the orthographic projection of part or all of the structure in the first active structure 36 on the substrate 20, as long as the second electrode plate 52 can overlap with the orthographic projection of the first active structure 36 on the substrate 20 to form a shielding structure P.

[0100] In some embodiments, the orthographic projection of the second plate 52 on the substrate covers the orthographic projection of the first active structure 36 on the substrate.

[0101] In the embodiment of the present application, the orthographic projection of the first active structure 36 on the substrate can be completely located within the orthographic projection of the second electrode 52 on the substrate, which can improve the shielding effect of the second electrode 52 on the first active structure 36, thereby further reducing the parasitic capacitance generated by at least one of the first sub-control terminal 41 and the second sub-control terminal 42 and the first active structure 36, reducing the potential difference between the first node N1 and the fifth node N5, and improving the screen flickering problem.

[0102] In some embodiments, Figure 1 , Figure 2 , Figure 4 as well as Figure 7 As shown, the array substrate 100 further includes a second conductive layer 70 located on the side of the active layer 30 facing the substrate 20 , and the shielding structure P is located in the second conductive layer 70 .

[0103] The second conductive layer 70 is a conductive film layer located on the side of the active layer 30 close to the substrate 20, and the shielding structure P is disposed in the second conductive layer 70 and overlaps with the orthographic projection of the first active structure 36 on the substrate 20. The second conductive layer 70 may include only the shielding structure P, or may include other structures, which is not limited in the embodiment of the present application.

[0104] In the related art, during the use of the display panel, light emitted by the display panel or ambient light will enter the interior of the display panel and be reflected at or below the substrate 20 and propagate to the active layer 30, thereby adversely affecting the performance of the thin film transistor and causing display abnormalities and other problems.

[0105] In the embodiment of the present application, the shielding structure P is arranged on the side of the active layer 30 close to the substrate 20, so as to have a shielding effect on the first active structure 36 to improve the flicker problem. At the same time, the shielding structure P is used to block part of the reflected light propagating to the active layer 30, thereby improving the performance of the thin film transistors in the array substrate 100 and improving the display reliability of the display panel formed subsequently.

[0106] In some embodiments, see Figure 4 , Figure 7 as well as Fig. 9 The width-to-length ratio of the first active structure 36 is greater than the width-to-length ratio of at least one of the first channel portion 31 and the second channel portion 32 .

[0107] The width-to-length ratio of the first active structure 36 refers to the ratio of the width to the length of the first active structure 36, wherein, according to the different actual layout modes of the active layer 30, the first active structure 36 may be in a straight line, in which case the length of the first active structure 36 is the dimension of the first active structure 36 in the direction of the corresponding straight line, or the first active structure 36 may be in a curved or straight line, in which case the extension direction of the first active structure 36 at different positions may change, and the length of the first active structure 36 is the sum of its extension lengths at different positions. The lengths of the first channel portion 31 and the second channel portion 32 are similar, and the present application embodiment does not limit this.

[0108] Furthermore, in the embodiment of the present application, the width-to-length ratio of the first active structure 36 is set to be greater than the width-to-length ratio of at least one of the first channel portion 31 and the second channel portion 32, so that the first active structure 36 has a larger width dimension relative to at least one of the first channel portion 31 and the second channel portion 32. This design helps to increase the size of the capacitance formed between the first active structure 36 and the shielding structure P, thereby further enhancing the shielding effect of the shielding structure P on the first active structure 36, reducing the risk of the first active structure 36 having a potential change due to a sudden change in the second scan signal ScanN2, thereby reducing the leakage level between the first node N1 and the fifth node N5, and improving the flickering problem of the display screen.

[0109] In some embodiments, the material of the active layer 30 includes low temperature polysilicon.

[0110] The material of the active layer 30 includes low-temperature polysilicon, which means that the first switch transistor T4 is an LTPS-TFT. Compared with the solution in which the first switch transistor T4 is an IGZO-TFT, the mobility corresponding to the LTPS-TFT is large, the resistance is small, and the influence on the transmitted signal is small, but the LTPS-TFT is more prone to leakage problems, especially under low-frequency conditions, the leakage problem of the LTPS-TFT is more serious. In view of this, the embodiment of the present application further reduces the resistivity of the first channel portion 31, thereby helping to achieve fast leakage between the first node N1 and the fifth node N5, thereby reducing the screen flickering problem caused by slow leakage during the light-emitting stage and improving the display perception.

[0111] Second, see Figure 1 , Figure 2 , Figure 4 as well as Fig.10 An embodiment of the present application provides a display panel 200, which includes an array substrate 100 and a plurality of sub-pixels 60 in any of the aforementioned embodiments. The array substrate 100 includes a plurality of pixel circuits 10. The pixel circuit 10 includes a first driving transistor T3 and a first switching transistor T4. The pixel circuit 10 is used to control the sub-pixel 60 to emit light.

[0112] It should be noted that the display panel 200 provided in the embodiment of the present application may be an organic light-emitting display panel 200, or may be a liquid crystal display panel 200, or may be a micro-light-emitting diode display panel 200. The embodiment of the present application does not limit the specific type of the display panel 200. For the convenience of description, the embodiment of the present application takes the display panel 200 as an organic light-emitting display panel 200 as an example for description.

[0113] In the embodiment of the present application, the first channel portion 31 is adjusted so that its resistivity is smaller than the resistivity of the second channel portion 32, so that when there is a certain voltage difference between the fifth node N5 and the first node N1, the current can flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31, so that the potential at the first node N1 can be kept consistent with the potential at the fifth node N5 in a short time, thereby reducing the leakage degree between the first node N1 and the fifth node N5 in the light-emitting stage, reducing the flickering degree of the display screen, and improving the display effect.

[0114] In addition, the display panel 200 in the embodiment of the present application can have the beneficial effects of the array substrate 100 in any of the aforementioned embodiments. For details, please refer to the aforementioned description of the beneficial effects of the array substrate 100, which will not be repeated in the embodiment of the present application.

[0115] In some embodiments, the plurality of sub-pixels 60 include a first sub-pixel 60 and a second sub-pixel 60 of different colors, and the plurality of pixel circuits 10 include a first pixel circuit 10 for driving the first sub-pixel 60, and a second pixel circuit 10 for driving the second sub-pixel 60. The resistivity of the first channel portion 31 corresponding to the first switch transistor T4 in the first pixel circuit 10 is less than the resistivity of the first channel portion 31 corresponding to the first switch transistor T4 in the second pixel circuit 10.

[0116] In order to realize the color luminescence function, the display panel 200 may include multiple types of sub-pixels 60 with different colors. The first sub-pixel 60 and the second sub-pixel 60 are sub-pixels 60 corresponding to different luminescent colors. The specific luminescent colors of the first sub-pixel 60 and the second sub-pixel 60 are not limited in the embodiment of the present application.

[0117] The first pixel circuit 10 is a circuit structure for controlling whether the first sub-pixel 60 emits light or not, and the second pixel circuit 10 is a circuit structure for controlling whether the second sub-pixel 60 emits light or not. In order to reduce the difficulty of preparing and designing the array substrate 100, the number and connection method of the thin film transistors and the storage capacitor 50 in the first pixel circuit 10 and the second pixel circuit 10 can be kept consistent, and the first pixel circuit 10 and the second pixel circuit 10 both include a first driving transistor T3 and a first switching transistor T4.

[0118] Taking into account the different sensitivities of the human eye to light of different colors and some other factors, the contribution of the first sub-pixel 60 and the second sub-pixel 60 of different colors to the display effect may also be different. On this basis, the embodiment of the present application makes differentiated designs for the first pixel circuit 10 for controlling the first sub-pixel 60 and the second pixel circuit 10 for controlling the second sub-pixel 60.

[0119] Specifically, in the embodiment of the present application, in view of the situation where the influence of the first sub-pixel 60 on the display effect is greater than that of the second sub-pixel 60, the resistivity of the first channel portion 31 corresponding to the first switch transistor T4 in the first pixel circuit 10 is set to be smaller than the resistivity of the first channel portion 31 corresponding to the first switch transistor T4 in the second pixel circuit 10, so that the first channel portion 31 in the first pixel circuit 10 has a stronger conductivity than the first channel portion 31 in the second pixel circuit 10, thereby further reducing the flicker problem caused by the light emission of the first sub-pixel 60 and improving the display effect.

[0120] It should be noted that, in the first pixel circuit 10, the resistivity of the first channel portion 31 is smaller than the resistivity of the second channel portion 32. Depending on the degree of influence of the second sub-pixel 60 on the display effect, in the second pixel circuit 10, the resistivity of the first channel portion 31 may be smaller than the resistivity of the second channel portion 32, or the resistivity of the first channel portion 31 may be equal to the resistivity of the second channel portion 32, and the embodiment of the present application does not limit this.

[0121] In some embodiments, the first sub-pixel 60 is configured to emit green light.

[0122] Compared with other colors, the human eye is more sensitive to green light. If the green light flickers, the user can perceive the change in the display effect. In view of this, the embodiment of the present application adjusts the first pixel circuit 10 for controlling the first sub-pixel 60, and reduces the resistivity of the first channel portion 31 in the first pixel circuit 10, thereby helping to reduce the flicker problem corresponding to the green light and improving the user's viewing experience.

[0123] Third, see Fig.11An embodiment of the present application provides a display device 300, and the display device 300 includes a display panel in any of the aforementioned embodiments.

[0124] It should be noted that the display device 300 in the embodiment of the present application can have the beneficial effects of the array substrate and the display panel in any of the aforementioned embodiments. For specific details, please refer to the aforementioned description of the beneficial effects of the array substrate and the display panel, and the embodiment of the present application will not go into details.

[0125] Fourth, please refer to Figures 1 to 4 as well as Fig.12 The embodiment of the present application provides a method for preparing an array substrate 100, wherein the array substrate 100 includes a first switch transistor T4 and a first driving transistor T3, wherein the control terminal of the first driving transistor T3 is electrically connected to a first node N1, the first electrode of the first switch transistor T4 is electrically connected to the second electrode of the first driving transistor T3, the second electrode of the first switch transistor T4 is electrically connected to the first node N1, and the first switch transistor T4 includes a first sub-switch transistor T41 and a second sub-switch transistor T42. The preparation method includes:

[0126] S100: forming an active layer on one side of the substrate.

[0127] In step S100 , the first sub-switching transistor T41 includes a first channel portion 31 located in the active layer 30 , and the second sub-switching transistor T42 includes a second channel portion 32 located in the active layer 30 .

[0128] S110: Plasma treatment is performed on the first channel portion.

[0129] In step S110, the resistivity of the first channel portion 31 after plasma treatment is less than the resistivity of the second channel portion 32, so that when the potential at the fifth node N5 between the first channel portion 31 and the second channel portion 32 is increased, the current can flow quickly from the fifth node N5 to the first node N1 through the first channel portion 31, so that the potential at the first node N1 can be kept consistent with the potential at the fifth node N5 in a short time, thereby reducing the leakage degree between the first node N1 and the fifth node N5 in the light-emitting stage, reducing the flickering degree of the display screen, and improving the display effect.

[0130] It should be noted that, in some other embodiments, in step S110, the first channel portion 31 may not be subjected to plasma treatment, but may be subjected to secondary doping treatment by ion implantation, so that the doping concentration of the first channel portion 31 is greater than the doping concentration of the second channel portion 32. In this way, the resistivity of the first channel portion 31 can also be smaller than the resistivity of the second channel portion 32, thereby improving the screen flickering problem.

[0131] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0132] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer, disposed on one side of the substrate; a first driving transistor, wherein a control terminal of the first driving transistor is electrically connected to a first node; a first switch transistor, wherein a first electrode of the first switch transistor is electrically connected to a second electrode of the first drive transistor, a second electrode of the first switch transistor is electrically connected to the first node, and the first switch transistor includes a first sub-switch transistor and a second sub-switch transistor; The first sub-switch transistor includes a first channel portion located in the active layer, and the second sub-switch transistor includes a second channel portion located in the active layer, the first channel portion is electrically connected to the second electrode of the first switch transistor, the second channel portion is electrically connected to the first electrode of the first switch transistor, and there is a gap between the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate; The resistivity of the first channel portion is smaller than the resistivity of the second channel portion.

2. The array substrate according to claim 1, characterized in that: The doping concentration in the first channel portion is greater than the doping concentration in the second channel portion.

3. The array substrate according to claim 2, characterized in that: The doping concentration of the first channel portion is E, and E satisfies: 10 12 Pieces / cm -3 ≤E≤10 15 Pieces / cm -3 .

4. The array substrate according to claim 2, characterized in that: A ratio between a doping concentration in the first channel portion and a doping concentration in the second channel portion is a, and a satisfies: 3≤a≤200.

5. The array substrate according to claim 1, characterized in that: The first channel portion is plasma treated.

6. The array substrate according to claim 1, characterized in that: The control terminal of the first driving transistor includes a third channel portion located in the active layer, and the resistivity of the first channel portion is smaller than the resistivity of the third channel portion.

7. The array substrate according to claim 1, characterized in that: Also includes a second switch transistor, a first electrode of the second switch transistor is electrically connected to the first node, and a control terminal of the second switch transistor includes a third sub-switch transistor and a fourth sub-switch transistor; The third sub-switch transistor includes a fourth channel portion located in the active layer, the fourth sub-switch transistor includes a fifth channel portion located in the active layer, the fourth channel portion is electrically connected to the first electrode of the second switch transistor, the fifth channel portion is electrically connected to the second electrode of the second switch transistor, and there is a gap between the orthographic projection of the fourth channel portion on the substrate and the orthographic projection of the fifth channel portion on the substrate; Wherein, the resistivity of the fourth channel portion is smaller than the resistivity of the fifth channel portion.

8. The array substrate according to claim 1, characterized in that: The active layer further includes a first active structure, two ends of the first active structure are respectively connected to the first channel portion and the second channel portion; The array substrate also includes a shielding structure, which is located on one side of the active layer in the thickness direction of the substrate. The shielding structure is arranged so that its orthographic projection on the substrate overlaps with the orthographic projection of the first active structure on the substrate, and the shielding structure is used to transfer a normal voltage potential.

9. The array substrate according to claim 8, characterized in that: It also includes a storage capacitor, the storage capacitor includes a first plate located in the first conductive layer, and a second plate located on a side of the first plate away from the substrate, and the control end of the first switch transistor is located in the first conductive layer; Wherein, the second electrode plate includes the shielding structure.

10. The array substrate according to claim 9, characterized in that: The orthographic projection of the second electrode plate on the substrate covers the orthographic projection of the first active structure on the substrate.

11. The array substrate according to claim 8, characterized in that: It also includes a second conductive layer located on a side of the active layer facing the substrate, and the shielding structure is located in the second conductive layer.

12. The array substrate according to claim 8, characterized in that: The width-to-length ratio of the first active structure is greater than the width-to-length ratio of at least one of the first channel portion and the second channel portion.

13. The array substrate according to claim 1, characterized in that: The material of the active layer includes low temperature polysilicon.

14. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 13 and a plurality of sub-pixels, the array substrate comprises a plurality of pixel circuits, the pixel circuit comprises the first driving transistor and the first switching transistor, and the pixel circuit is used to control the sub-pixels to emit light.

15. The display panel according to claim 14, characterized in that: The plurality of sub-pixels include a first sub-pixel and a second sub-pixel of different colors, and the plurality of pixel circuits include a first pixel circuit for driving the first sub-pixel and a second pixel circuit for driving the second sub-pixel; The resistivity of the first channel portion corresponding to the first switch transistor in the first pixel circuit is smaller than the resistivity of the first channel portion corresponding to the first switch transistor in the second pixel circuit.

16. The display panel according to claim 15, characterized in that: The first sub-pixel is used for emitting green light.

17. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 14 to 16.

18. A method for preparing an array substrate, characterized in that: The array substrate includes a first switch transistor and a first drive transistor, the control end of the first drive transistor is electrically connected to a first node, the first electrode of the first switch transistor is electrically connected to a second electrode of the first drive transistor, the second electrode of the first switch transistor is electrically connected to the first node, and the first switch transistor includes a first sub-switch transistor and a second sub-switch transistor; the preparation method includes: An active layer is formed on one side of the substrate, wherein the first sub-switch transistor includes a first channel portion located in the active layer, and the second sub-switch transistor includes a second channel portion located in the active layer; Plasma treatment is performed on the first channel portion so that a resistivity of the first channel portion is smaller than a resistivity of the second channel portion.

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