Manufacturing method of backside illuminated image sensor
By forming a protective layer at the top corner position of the silicon through-hole of the back-illuminated image sensor and performing maskless etching, the problem of breakdown caused by thin oxide remaining at the top corner position is solved, and a larger rounded corner radius and better electrical properties.
Patent Information
- Application Number
- CN202411500550.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-02-14
AI Technical Summary
When manufacturing back-illuminated image sensors, the rounded corner radius at the top corner position is usually small, resulting in a thin residual oxide and prone to breakdown problems.
The top corner protective layer is formed at the top corner position of the through-silicon hole, and a maskless etching is performed at the bottom of the through-silicon hole with the protective layer, etching the termination layer so that the top of the contact hole structure is exposed from the through-silicon hole.
By fully protecting the top corners, the rounded corner radius can be increased to 1110A, meeting the needs of large rounded corner etching and improving the electrical performance of the device.
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Figure CN119451259A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a back-illuminated image sensor. Background Art
[0002] Back side illumination (BSI) is a type of CMOS image sensor. The main advantage of BSI is that it can separate the electrical components from the light, so that the light path can be optimized independently, avoiding the absorption and reflection of the metal wiring layer of the front-illuminated image sensor, so BSI can achieve a higher quantum effect (QE).
[0003] In the manufacturing process, a through silicon via is formed from the back of the back-illuminated image sensor to connect the front and back of the back-illuminated image sensor. The etched through silicon via stays on the front oxide layer (HARP). The subsequent process needs to use a maskless etching (Blanket Etch) to remove the dielectric layer under the through silicon via, so that the contact hole structure at the front is exposed, and the electrical connection between the front device and the back optical collection device is realized.
[0004] When manufacturing the TSV, in order to ensure isolation and a higher breakdown voltage, the amount of oxide residue at the top and top corner of the TSV needs to be strictly controlled.
[0005] However, when making silicon through vias in related technologies, the fillet radius at the top corner is usually small, resulting in a thinner oxide residue at the top corner, where breakdown problems are likely to occur due to low withstand voltage. Summary of the invention
[0006] The present application provides a method for manufacturing a back-illuminated image sensor, which can solve the problem in the related art that the fillet radius at the corner position is usually small, resulting in a thinner oxide residue at the top corner position.
[0007] In order to solve the technical problem described in the background technology, the present application provides a method for manufacturing a back-illuminated image sensor, and the method for manufacturing a back-illuminated image sensor comprises the following steps:
[0008] A semiconductor structure is provided with pixel units formed on the back, through silicon vias are formed between adjacent pixel units, and inner walls of the through silicon vias are sequentially covered with a silicon oxide layer and a silicon nitride layer; a contact hole structure is formed on the front of the semiconductor structure, and the contact hole structure is aligned with the through silicon vias;
[0009] Etching the metal silicide barrier layer at the bottom of the through silicon via in an etching environment having a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that an etching stop layer under the metal silicide barrier layer is exposed from the through silicon via;
[0010] Forming a top corner protection layer on the outer wall of the top of the through silicon via, wherein the top corner protection layer covers the top corner position of the through silicon via;
[0011] The bottom of the through silicon via with the top corner protection layer is etched without a mask, and the etching stop layer is etched, so that the top of the contact hole structure is exposed from the through silicon via.
[0012] Optionally, the step of etching the metal silicide barrier layer at the bottom of the through silicon via in an etching environment having a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer so that the etching stop layer under the metal silicide barrier layer is exposed from the through silicon via comprises:
[0013] Under pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, etching gas is introduced periodically first and then cleaning gas is introduced, and the metal silicide barrier layer at the bottom of the silicon via is etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer located under the metal silicide barrier layer is exposed from the silicon via.
[0014] Optionally, under pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, the etching gas is periodically introduced first and then the cleaning gas is introduced, and the metal silicide barrier layer at the bottom of the silicon via is etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon via, in the step, the etching gas includes C4F6 gas and C4F8 gas, and the ratio of the C4F6 gas to the C4F8 gas is 2:1 to 4:1.
[0015] Optionally, under pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, the etching gas is periodically introduced first and then the cleaning gas is introduced, and the metal silicide barrier layer at the bottom of the silicon via is etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon via, and in the step, the cleaning gas includes oxygen and nitrogen.
[0016] Optionally, during the pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, the etching gas is first introduced and then the cleaning gas is introduced, and the metal silicide barrier layer at the bottom of the silicon via is etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon via.
[0017] Optionally, the step of forming a top corner protection layer on the outer wall at the top of the through silicon via, wherein the top corner protection layer covers the top corner position of the through silicon via, comprises:
[0018] Under high frequency and low energy, any two or more combinations of CH2F2 gas, CO gas, C4F8 gas and CH2F2 gas are introduced to deposit a top corner protection layer at the top corner position of the through silicon via.
[0019] Optionally, the step of performing maskless etching on the bottom of the through silicon via with the top corner protection layer, etching the etch stop layer, so that the top of the contact hole structure is exposed from the through silicon via, comprises:
[0020] Under the conditions of a frequency of 1000 Hz to 2000 Hz and an energy of 500 W to 1000 W, C4F8 gas, oxygen and argon gas are introduced to perform maskless etching on the bottom of the silicon via with the top corner protection layer, and the etching stop layer is etched so that the top of the contact hole structure is exposed from the silicon via.
[0021] The technical solution of the present application includes at least the following advantages: the present application can enable the etching process to fully protect the top corner, so that the fillet radius at the top corner position is larger, up to 1110A, which is suitable for the etching needs of large fillets and meets the electrical requirements of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 A flow chart of a method for manufacturing a back-illuminated image sensor provided by an embodiment of the present application is shown;
[0024] Figure 2 A schematic diagram of a semiconductor structure provided by an embodiment of the present application is shown;
[0025] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S2 is completed is shown;
[0026] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S3 is completed is shown;
[0027] Figure 5 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S4 is completed. DETAILED DESCRIPTION
[0028] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0029] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0031] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0032] Figure 1 A flow chart of a method for manufacturing a back-illuminated image sensor according to an embodiment of the present application is shown. Figure 1 It can be seen that the manufacturing method of the back-illuminated image sensor includes the following steps:
[0033] Step S1: providing a semiconductor structure with a photodiode formed on the back, with through silicon vias formed between adjacent photodiodes, and inner walls of the through silicon vias sequentially covered with a silicon oxide layer and a silicon nitride layer; a contact hole structure is formed at the front of the semiconductor structure, and the contact hole structure is aligned with the through silicon vias.
[0034] Figure 2 A schematic diagram of a semiconductor structure provided by an embodiment of the present application is shown. Figure 1 It can be seen that the semiconductor structure includes a relative back and front, a pixel unit 110 is formed on the back, and a silicon via 120 is formed between adjacent pixel units 110. The inner wall of the silicon via 120 is covered with a silicon oxide layer 130 and a silicon nitride layer 140 in sequence from the lower side to the upper side as shown in the figure.
[0035] A stacked layer structure is formed at the front of the semiconductor structure, and a contact hole structure 210 is formed in the stacked layer structure, and the contact hole structure 210 is aligned with the through silicon via 120. The stacked layer structure includes a metal layer 220, a dielectric layer 230, an etch stop layer 240, and a metal silicide barrier layer 250 stacked in sequence from the lower side to the upper side as shown in the figure, and the lower end of the contact hole structure 210 is in contact with and connected to the metal layer 220, and the upper end of the contact hole structure 210 extends into the metal silicide barrier layer 250.
[0036] Step S2: etching the metal silicide barrier layer at the bottom of the through silicon via in an etching environment having a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the through silicon via.
[0037] Exemplarily, the material of the metal silicide barrier layer at the bottom of the through silicon via may be silicon oxide.
[0038] Reference Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after step S2 is completed, from Figure 3 It can be seen that the metal silicide barrier layer 250 at the bottom of the through silicon via 120 is etched in an etching environment having a high etching selectivity ratio for the silicon oxide layer 130 relative to the silicon nitride layer 140. The etching rate of the silicon nitride layer 140 is low in the etching process, and the etching rate of the silicon oxide layer is high in the etching process, so that the etching of the silicon nitride layer 140 is less in the etching process, and the metal silicide barrier layer 250 at the bottom of the through silicon via 120 is removed in the etching process, and then the etching stop layer 240 located under the metal silicide barrier layer 250 is exposed from the through silicon via 120, and the top portion of the contact hole structure 210 extending into the metal silicide barrier layer 250 is also exposed from the through silicon via 120.
[0039] When performing step S2, the etching gas and then the cleaning gas can be periodically introduced under a pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, and the metal silicide barrier layer at the bottom of the silicon through hole can be etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon through hole.
[0040] The etching gas includes C4F6 gas and C4F8 gas, and the ratio of the C4F6 gas to the C4F8 gas is 2:1 to 4:1.
[0041] Wherein, the cleaning gas includes oxygen and nitrogen.
[0042] When performing the above steps, the process may be repeated 3 to 5 times, with the etching gas being introduced first and the cleaning gas being introduced second.
[0043] Step S3: forming a top corner protection layer on the outer wall of the top of the through silicon via, wherein the top corner protection layer covers the top corner position of the through silicon via.
[0044] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S3 is completed, from Figure 4 It can be seen from the figure that a top corner protection layer 150 is formed at the top corner position of the through silicon via 120, and the top corner protection layer 150 protects the top corner position.
[0045] Exemplarily, under high frequency and low energy, any two or more combinations of CH2F2 gas, CO gas, C4F8 gas and CH2F2 gas are introduced to deposit a top corner protection layer at the top corner of the through silicon via.
[0046] Step S4: performing maskless etching on the bottom of the through silicon via with the top corner protection layer, etching the etching stop layer, so that the top of the contact hole structure is exposed from the through silicon via.
[0047] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed, from Figure 5 It can be seen that the maskless etching of the bottom of the silicon via 120 with the top corner protection layer 150 can make the etching process fully protect the top corner, so that the fillet radius at the top corner position is larger, up to 1110A, which is suitable for the etching requirements of large fillets and meets the electrical requirements of the device.
[0048] Exemplarily, C4F8 gas, oxygen and argon gas can be introduced at a frequency of 1000 Hz to 2000 Hz and an energy of 500 W to 1000 W to perform maskless etching on the bottom of the silicon via with the top corner protection layer, and the etching stop layer is etched so that the top of the contact hole structure is exposed from the silicon via.
[0049] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for manufacturing a back-illuminated image sensor, characterized in that: The method for manufacturing the back-illuminated image sensor comprises the following steps: A semiconductor structure is provided with pixel units formed on the back, through silicon vias are formed between adjacent pixel units, and inner walls of the through silicon vias are sequentially covered with a silicon oxide layer and a silicon nitride layer; a contact hole structure is formed on the front of the semiconductor structure, and the contact hole structure is aligned with the through silicon vias; Etching the metal silicide barrier layer at the bottom of the through silicon via in an etching environment having a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that an etching stop layer under the metal silicide barrier layer is exposed from the through silicon via; Forming a top corner protection layer on the outer wall of the top of the through silicon via, wherein the top corner protection layer covers the top corner position of the through silicon via; The bottom of the through silicon via with the top corner protection layer is etched without a mask, and the etching stop layer is etched, so that the top of the contact hole structure is exposed from the through silicon via.
2. The method for manufacturing a back-illuminated image sensor according to claim 1, wherein: The step of etching the metal silicide barrier layer at the bottom of the through silicon via in an etching environment having a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer so that the etching stop layer under the metal silicide barrier layer is exposed from the through silicon via comprises: Under pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, etching gas is introduced periodically first and then cleaning gas is introduced, and the metal silicide barrier layer at the bottom of the silicon via is etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer located under the metal silicide barrier layer is exposed from the silicon via.
3. The method for manufacturing a back-illuminated image sensor according to claim 2, wherein: In the step of periodically introducing an etching gas first and then a cleaning gas under a pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, etching the metal silicide barrier layer at the bottom of the silicon via in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon via, the etching gas includes C4F6 gas and C4F8 gas, and the ratio of the C4F6 gas to the C4F8 gas is 2:1 to 4:
1.
4. The method for manufacturing a back-illuminated image sensor according to claim 2, wherein: In the step of periodically introducing an etching gas first and then a cleaning gas under a pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, etching the metal silicide barrier layer at the bottom of the silicon via in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon via, the cleaning gas includes oxygen and nitrogen.
5. The method for manufacturing a back-illuminated image sensor according to claim 2, wherein: Under the pulsed radio frequency with a frequency of 1500 Hz to 2500 Hz and a duty cycle of 30% to 60%, the etching gas is first introduced and then the cleaning gas is introduced, and the metal silicide barrier layer at the bottom of the silicon via is etched in an etching environment with a high etching selectivity ratio for the silicon oxide layer relative to the silicon nitride layer, so that the etching stop layer under the metal silicide barrier layer is exposed from the silicon via.
6. The method for manufacturing a back-illuminated image sensor according to claim 1, wherein: The step of forming a top corner protection layer on the outer wall at the top of the through silicon via, wherein the top corner protection layer covers the top corner position of the through silicon via, comprises: Under high frequency and low energy, any two or more combinations of CH2F2 gas, CO gas, C4F8 gas and CH2F2 gas are introduced to deposit a top corner protection layer at the top corner position of the through silicon via.
7. The method for manufacturing a back-illuminated image sensor according to claim 1, wherein: The step of performing maskless etching on the bottom of the through silicon via with the top corner protection layer, etching the etching stop layer, so that the top of the contact hole structure is exposed from the through silicon via, comprises: Under the conditions of a frequency of 1000 Hz to 2000 Hz and an energy of 500 W to 1000 W, C4F8 gas, oxygen and argon gas are introduced to perform maskless etching on the bottom of the silicon via with the top corner protection layer, and the etching stop layer is etched so that the top of the contact hole structure is exposed from the silicon via.