Vertical charge transfer imaging sensor and manufacturing method thereof

Abstract

The invention relates to a vertical charge transfer imaging sensor and a manufacturing method thereof. In the vertical charge transfer imaging sensor, shallow trench isolation and deep trench isolation are formed on one side of a semiconductor substrate, the deep trench isolation comprises a trench electrode and a first isolation medium which are filled in a deep trench formed on one side of the semiconductor substrate, and the deep trench isolation defines a plurality of substrate units in a pixel region. Each substrate unit comprises a photosensitive area and a charge reading area which are isolated by a shallow trench, the substrate units and the control gates respectively form two polar plates of a capacitor corresponding to the photosensitive areas, and the substrate electrodes are formed on the other side of the substrate, are in contact with the polar plates formed by the substrate units and are isolated from the trench electrodes. The deep trench isolation forms physical isolation between pixels, crosstalk between the pixels can be effectively avoided, the trench electrode provides an operable electrode end for the vertical charge transfer imaging sensor, and diversified operation modes can be achieved conveniently.

Description

Technical Field

[0001] The present invention relates to the field of photosensitive technology, and in particular to a vertical charge transfer imaging sensor and a method for manufacturing the vertical charge transfer imaging sensor. Background Art

[0002] Vertically charge transferring pixel sensors (VPS) are image sensors that use semiconductor substrates and floating gate transistor structures to achieve imaging. Figure 1 and Figure 2 In the vertical charge transfer imaging sensor, each pixel includes a semiconductor substrate 10 portion, the semiconductor substrate 10 portion includes a photosensitive region 11 and a charge reading region 12 separated by shallow trench isolation (STI), and a gate dielectric layer 13 extending from the photosensitive region 11 to the charge reading region 12, a floating gate FG, an inter-gate dielectric layer 14, and a control gate CG are stacked on the front side of the semiconductor substrate 10 portion. The source region S and the drain region D are formed in the charge reading region 12 on both sides of the control gate (CG), so that each pixel includes a MOS capacitor formed in the photosensitive region 11 and a read transistor formed in the charge reading region 12 connected to each other. When the vertical charge transfer imaging sensor is working, light is incident from the back side of the semiconductor substrate 10 portion to generate photoelectrons. Under the action of a suitable bias voltage, the photoelectrons move toward the control gate CG side and gather on the lower surface of the gate dielectric layer 13 of the photosensitive region 11 or cross the potential barrier to enter the floating gate (FG), thereby causing the drain current and / or threshold voltage of the read transistor to change. By detecting this change, photoelectric sensing and imaging can be achieved.

[0003] Compared with traditional photodiode-based semiconductor sensors (such as CMOS image sensors), vertical charge transfer imaging sensors can achieve higher full well charges at the same pixel size, thereby having a higher signal-to-noise ratio and having obvious advantages in pixel miniaturization.

[0004] For VPS sensors, the main challenge currently faced is how to ensure photoelectric conversion efficiency while avoiding crosstalk between pixels when pixels are miniaturized. Summary of the invention

[0005] In order to ensure the photoelectric conversion efficiency of a vertical charge transfer imaging sensor and avoid crosstalk between pixels, the present invention provides a vertical charge transfer imaging sensor and a manufacturing method thereof.

[0006] In one aspect, the present invention provides a vertical charge transfer imaging sensor, the vertical charge transfer imaging sensor comprising:

[0007] A semiconductor substrate having a first doping type, the semiconductor substrate comprising a pixel region and a peripheral region;

[0008] A semiconductor substrate, wherein the semiconductor substrate comprises a pixel region;

[0009] Shallow trench isolation and deep trench isolation are formed on one side of the semiconductor substrate, the deep trench isolation includes a deep trench penetrating the semiconductor substrate and a trench electrode and a first isolation medium filled in the deep trench, the first isolation medium isolates the trench electrode from the semiconductor substrate, the deep trench isolation defines a plurality of substrate units in the pixel area, each of the substrate units includes a photosensitive area and a charge reading area separated by the shallow trench isolation;

[0010] A gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate are stacked on the surface of each substrate unit and extend from the photosensitive area to the charge reading area, wherein the charge reading area is formed with a source region and a drain region respectively located on both sides of the corresponding control gate; and

[0011] A substrate electrode is formed on the other side of the semiconductor substrate, wherein the substrate electrode contacts each of the substrate units and is isolated from the trench electrodes.

[0012] Optionally, the semiconductor substrate includes a trench electrode lead-out region located at the periphery of the pixel region, the trench electrode extends from the pixel region to the trench electrode lead-out region along the deep trench, and extends from the bottom of the deep trench to the top of the trench electrode lead-out region.

[0013] Optionally, the vertical charge transfer imaging sensor further comprises a trench electrode connection block, wherein the trench electrode connection block is formed in the trench electrode lead-out region and covers the trench electrode.

[0014] Optionally, in the pixel area, the first isolation medium filled in the deep trench includes a linear oxide layer and a deep trench filling layer, the linear oxide layer is between the trench electrode and the semiconductor substrate, and the deep trench filling layer covers the trench electrode and is located at the top of the deep trench.

[0015] Optionally, the substrate electrode is arranged on the other side of the semiconductor substrate corresponding to the deep trench of the pixel region, and a second isolation medium is provided between the substrate electrode and the trench electrode.

[0016] Optionally, the second isolation medium includes a high dielectric constant material.

[0017] Optionally, the control gates formed on the substrate units are connected to form a plurality of word lines, and each word line spans across a plurality of the substrate units.

[0018] In one aspect, the present invention provides a method for manufacturing a vertical charge transfer imaging sensor, the method comprising:

[0019] Providing a semiconductor substrate, the semiconductor substrate comprising a pixel region;

[0020] A shallow trench isolation and a deep trench isolation are formed on one side of the semiconductor substrate, wherein the deep trench isolation includes a deep trench penetrating a portion of the semiconductor substrate and a trench electrode and a first isolation medium filled in the deep trench, wherein the first isolation medium insulates the trench electrode from the semiconductor substrate, and the deep trench isolation defines a plurality of substrate units in the pixel region, each of the substrate units including a photosensitive region and a charge reading region separated by the shallow trench isolation;

[0021] A gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate are stacked on the surface of each substrate unit, wherein the gate dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate extend from the photosensitive area to the charge reading area, and a source region and a drain region are formed in the charge reading area and are located on both sides of the corresponding control gate; and

[0022] The semiconductor substrate is thinned from the other side to expose the deep trench isolation, and a substrate electrode is formed on the other side, the substrate electrode is in contact with each of the substrate units and isolated from the trench electrode.

[0023] Optionally, forming the shallow trench isolation and the deep trench isolation on one side of the semiconductor substrate includes:

[0024] A pad oxide layer and a first hard mask layer are stacked on the surface of the semiconductor substrate, and the shallow trench isolation is formed, wherein the shallow trench isolation penetrates the first hard mask layer, the pad oxide layer and a portion of the semiconductor substrate;

[0025] forming a second hard mask layer, wherein the second hard mask layer covers the first hard mask layer and the shallow trench isolation;

[0026] forming the deep trench, wherein the deep trench penetrates the second hard mask layer, the first hard mask layer, the pad oxide layer and a portion of the semiconductor substrate;

[0027] forming a linear oxide layer and a trench conductive layer in the deep trench, wherein the linear oxide layer covers the semiconductor substrate exposed by the deep trench, the trench conductive layer covers the linear oxide layer and fills the deep trench, and the top surface of the trench conductive layer is higher than the surface of the semiconductor substrate;

[0028] Etching back the trench conductive layer in the pixel area to below the surface of the semiconductor substrate to form an etched-back space at the top of the deep trench in the pixel area, and the remaining trench conductive layer is a trench electrode; and

[0029] A deep trench filling layer is formed in the back-etching space, and the linear oxide layer and the deep trench filling layer serve as the first isolation medium.

[0030] Optionally, the semiconductor substrate includes a trench electrode lead-out region located at the periphery of the pixel region, the trench electrode extends from the pixel region to the trench electrode lead-out region along the deep trench, and extends from the bottom of the deep trench to the top of the trench electrode lead-out region.

[0031] Optionally, forming the substrate electrode comprises:

[0032] forming a first groove at the exposed deep trench isolation from the other side of the semiconductor substrate, wherein the first groove exposes the trench electrode and the substrate unit around the trench electrode;

[0033] forming a second isolation medium on the other side, wherein the second isolation medium fills the first groove and covers the surface of the substrate unit;

[0034] forming a second groove, wherein the bottom of the second groove is located at the upper part of the first groove, the side surface of the second groove exposes the substrate unit around the deep trench isolation, and the trench electrode is covered by the second isolation medium; and

[0035] The second groove is filled with a conductive material to form the substrate electrode.

[0036] The vertical charge transfer imaging sensor and the method for manufacturing the vertical charge transfer imaging sensor provided by the present invention have the following technical effects:

[0037] First, the deep trench isolation passes through the semiconductor substrate and defines a plurality of substrate units in the pixel area, each of which corresponds to a pixel of the vertical charge transfer imaging sensor, that is, physical isolation is formed between each pixel, which can ensure the photoelectric conversion efficiency of the vertical charge transfer imaging sensor, effectively avoid crosstalk between pixels, and is conducive to pixel miniaturization;

[0038] Second, the substrate electrode is formed on the other side of the semiconductor substrate (i.e., the side away from the control gate), and the substrate electrode does not need to occupy the area of ​​one side of the control gate, which is conducive to pixel miniaturization;

[0039] Third, the deep trench isolation includes a deep trench penetrating the semiconductor substrate and a trench electrode and a first isolation medium filled in the deep trench, wherein the first isolation medium isolates the trench electrode from the semiconductor substrate, and the trench electrode provides an operable electrode terminal for the vertical charge transfer imaging sensor, which can realize diversified operation modes in conjunction with other electrode terminals in the sensor;

[0040] Fourth, the trench electrode can be coupled with the substrate electrode for use. In the process of photosensitization, by applying a positive bias voltage between the substrate electrode and the trench electrode, the potential barrier at the interface between the deep trench isolation and the substrate unit can be increased, so that the probability of photoelectrons being captured at the interface is reduced, which is helpful to improve the photoelectric conversion efficiency and improve the dark current and white pixel problems. In addition, the positive bias voltage is flexibly adjustable, and the isolation medium between the trench electrode and the substrate unit can be made of a low dielectric constant material, which is low in cost.

[0041] Fifth, after completing a photosensitivity and charge reading operation, a reset can be performed by applying a negative bias voltage between the substrate electrode and the trench electrode to release the charges trapped in the deep trench isolation boundary area, which helps to improve the background noise during the next photosensitivity and charge reading operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a plan view of a pixel in a vertical charge transfer imaging sensor.

[0043] Figure 2 yes Figure 1 Schematic diagram of the cross section along line XX'.

[0044] Figure 3 FIG. 4 is a schematic plan view of a vertical charge transfer imaging sensor according to an embodiment of the present invention.

[0045] Figure 4 yes Figure 3 Schematic diagram of the cross section of the AA' line area.

[0046] Figure 5 It is a schematic flow chart of a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention.

[0047] Figures 6A to 6V It is a cross-sectional schematic diagram of a method for manufacturing a vertical charge transfer imaging sensor according to an embodiment of the present invention during the manufacturing process. DETAILED DESCRIPTION

[0048] The vertical charge transfer imaging sensor and its manufacturing method of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. The embodiments of the present invention should not be considered to be limited to the specific shapes of the areas shown in the figures, but may include the actual shapes obtained, such as deviations caused by manufacturing. For the sake of clarity, in all the drawings used to assist in explaining the embodiments of the present invention, the same components are marked with the same reference numerals in principle, and repeated descriptions thereof are omitted.

[0049] Reference Figure 3 and Figure 4 The embodiment of the present invention includes a vertical charge transfer imaging sensor (or VPS sensor), and the vertical charge transfer imaging sensor includes:

[0050] A semiconductor substrate 100, wherein the semiconductor substrate 100 includes a pixel area A1;

[0051] Shallow trench isolation STI and deep trench isolation DTI are formed on one side of the semiconductor substrate 100, the deep trench isolation DTI includes a deep trench DT penetrating the semiconductor substrate 100, a trench electrode E1 filled in the deep trench DT, and a first isolation medium (specifically, a linear oxide layer 105 and a deep trench filling layer 107), the first isolation medium insulates the trench electrode E1 from the semiconductor substrate 100, the deep trench isolation DTI defines a plurality of substrate units 110 in the pixel area A1, each of the substrate units 110 includes a photosensitive area 110a and a charge reading area 110b separated by the shallow trench isolation STI;

[0052] A gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 111 and a control gate CG are stacked on the surface of each substrate unit 100 and extend from the photosensitive region 110a to the charge reading region 110b, wherein the charge reading region 110b is formed with a source region S and a drain region D respectively located on both sides of the corresponding control gate CG; and

[0053] The substrate electrode E2 is formed on the other side of the semiconductor substrate 100 . The substrate electrode E2 is in contact with each of the substrate units 110 and isolated from the trench electrode E1 .

[0054] The semiconductor substrate 100 may be any suitable semiconductor substrate in the art, and its material may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide. The semiconductor substrate 100 may be ion-doped, and specifically may be a silicon substrate doped with boron or boron difluoride, and the boron ion density may be, for example, 1×1012 / cm 2 ~2×10 12 / cm 2 (P-). The charge reading region 110b of the semiconductor substrate 100 is formed with a P-type body region (PW, not shown), and the source region S and the drain region D are, for example, N-type doped and formed on the top of the P-type body region. It should be noted that this article mainly uses the floating gate transistor in the vertical transfer charge sensor pixel as an N-type device as an example for explanation. It can be understood that in the case where the floating gate transistor is a P-type device, the charge reading region 110b forms an N-type body region, and the source region S and the drain region D are P-type doped.

[0055] Optionally, the plurality of substrate units 110 of the pixel area A1 are arranged in an array, each substrate unit 110 corresponds to a pixel including a MOS capacitor formed in a photosensitive region 110 a of the corresponding substrate unit 110 and a read transistor formed in a charge read region 110 b .

[0056] like Figure 3 As shown, in this embodiment, the semiconductor substrate 100 further includes a peripheral region located outside the pixel region A1, and the peripheral region can be used to form a part of the circuit of the vertical charge transfer imaging sensor. The present invention is not limited thereto, and in some embodiments, the peripheral region can be disposed on another substrate, and the other substrate can be stacked and interconnected with the semiconductor substrate 100.

[0057] In this embodiment, part of the peripheral area is used as a trench electrode pick-up area A2 to form a connection with the trench electrode E1. The deep trench DT and the trench electrode E1 therein extend from the pixel area A1 to the trench electrode pick-up area A2. In the pixel area A1, the trench electrode E1 is lower than the lower surface of the gate dielectric layer 108 and is covered by a deep trench filling layer 107; in the trench electrode pick-up area A2, the trench electrode E1 extends from the bottom of the deep trench DT to the top and may protrude from the surface of the semiconductor substrate 100 (see Figure 6Q-2 ). Optionally, the vertical charge transfer imaging sensor further includes a trench electrode connection block E1-T, wherein the trench electrode connection block E1-T is formed in the trench electrode lead-out area A2 and covers the trench electrode E1, so that the trench electrode connection block E1-T is electrically connected to the trench electrode E1.

[0058] In some embodiments, the substrate electrode E2 is disposed on the other side of the semiconductor substrate 100 corresponding to the deep trench DT of the pixel area A1 , and a second isolation dielectric 113 is provided between the substrate electrode E2 and the trench electrode E1 .

[0059] In some embodiments, the second isolation dielectric 113 includes a high dielectric constant material (dielectric constant greater than 3.9). Optionally, the second isolation dielectric 113 also covers the end surface of the other side of the semiconductor substrate 100 .

[0060] In some embodiments, the control gate CG formed on each of the substrate units 110 is connected to form a plurality of word lines WL, and each of the word lines WL spans across a plurality of the substrate units 110 .

[0061] In the vertical charge transfer imaging sensor, each pixel includes a substrate unit 110, a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 111 and a control gate CG stacked on the substrate unit 110, and a source region S and a drain region D formed in the charge reading region 110b on both sides of the control gate CG. The photosensitive region 110a and the gate dielectric layer 108, the floating gate FG, the inter-gate dielectric layer 111 and the control gate CG thereon constitute a MOS capacitor for realizing photosensitivity, and the source region S and the drain region D in the charge reading region 110b and the gate dielectric layer 108, the floating gate FG, the inter-gate dielectric layer 111 and the control gate CG on the charge reading region 110b constitute a reading transistor for realizing charge reading.

[0062] As an example, the vertical charge transfer imaging sensor can achieve light sensing and reading by performing the following process:

[0063] First, a photosensitization operation is performed, a negative bias voltage (e.g., -3V) is applied to the semiconductor substrate 100, and a positive bias voltage is applied to the control gate CG, so as to form a continuous depletion region in the semiconductor substrate 100. When photons enter the depletion region from the side of the semiconductor substrate 100 away from the control gate CG, they are excited to form photoelectrons. Driven by the electric field, the photoelectrons gather on the lower surface of the gate dielectric layer 108 of the photosensitive region 110a or cross the potential barrier to enter the floating gate FG. Since the photosensitive region 110 is connected to the floating gate FG of the charge reading region 110b, the floating gate FG of the charge reading region 110b changes, thereby causing the drain current and / or threshold voltage of the reading transistor to change.

[0064] Next, a charge reading operation is performed, the source region S and the semiconductor substrate 100 are grounded (0V), the drain region D is connected to a positive bias voltage (for example, greater than 0 and less than 3V), and the drain current of the reading transistor is detected, or a change in the threshold voltage of the reading transistor is detected;

[0065] Next, a reset is performed to connect the control gate CG to a negative bias voltage, and the semiconductor substrate 100 and the source region S to a positive bias voltage (eg, greater than 0 and less than 3V) to release the photoelectrons gathered on the lower surface of the gate dielectric layer 108 or stored in the floating gate FG.

[0066] In the embodiment of the present invention, the trench electrode E1 provides an operable electrode terminal for the vertical charge transfer imaging sensor, and cooperates with other electrode terminals in the sensor (such as electrode terminals connected to the control gate, source region, drain region and substrate electrode respectively), so as to realize diversified operation modes. In some embodiments, the trench electrode E1 can be used as a coupling terminal of the substrate electrode E2. By applying a positive bias voltage between the substrate electrode E2 and the trench electrode E1, the potential barrier at the interface between the deep trench isolation DTI and the substrate unit 110 can be increased, so that the probability of photoelectrons being captured at the interface is reduced, which helps to improve the photoelectric conversion efficiency and improve the dark current and white pixel problems. In addition, after completing the photosensitivity and charge reading operations, a negative bias voltage can be applied between the substrate electrode and the trench electrode to reset (reset), and the charge captured in the deep trench isolation boundary area can be released, which helps to improve the background noise during the next photosensitivity and charge reading operations.

[0067] The embodiment of the present invention also includes a method for manufacturing a vertical charge transfer imaging sensor, which can be used to manufacture the vertical charge transfer imaging sensor described in the above embodiment. Figure 5 and Figures 6A to 6V The manufacturing method of the vertical charge transfer imaging sensor is described.

[0068] Fig. 6A It is a schematic cross-sectional view of a semiconductor substrate after forming a pad oxide layer and a first hard mask layer. Fig. 6A The cross section shown is, for example, Figure 3 The plane diagram shown is taken from the AA' line. Figure 3 , Figure 5 (Specifically step S1) and Fig. 6A , a semiconductor substrate 100 having a first doping type is provided, wherein the semiconductor substrate 100 includes a pixel area A1. The semiconductor substrate 100 is, for example, a silicon substrate having a P-type doping (P-). The pixel area A1 is used to form a photosensitive pixel. The semiconductor substrate 100 may include a trench electrode lead-out area A2 located at the periphery of the pixel area A1.

[0069] Reference Figure 5 In step S2, a shallow trench isolation STI and a deep trench isolation DTI are then formed on one side of the semiconductor substrate 100. Specifically, the following processes may be included.

[0070] like Fig. 6A As shown, a pad oxide layer 101 and a first hard mask layer 102 are stacked on the surface of a semiconductor substrate 100. The pad oxide layer 101 includes, for example, a certain thickness of silicon oxide, and the first hard mask layer 102 includes, for example, a certain thickness of silicon nitride.

[0071] Figure 6BSchematic diagram of the cross section after a shallow trench is formed in a semiconductor substrate. Figure 6B As shown, the position of the shallow trench isolation STI can be defined by a photolithography process, and a shallow trench ST penetrating the first hard mask layer 102, the pad oxide layer 101 and a portion of the semiconductor substrate 100 can be formed by one or more etchings, wherein the depth D1 of the shallow trench ST is approximately 100nm to 400nm, for example, approximately 200nm.

[0072] Figure 6C It is a schematic cross-sectional view after the shallow trench filling layer is formed. Figure 6C As shown, an oxide layer (not shown) is formed along the inner surface of the shallow trench ST, and then a shallow trench filling layer 103 is deposited. The shallow trench filling layer 103 fills the shallow trench ST and forms a certain thickness on the first hard mask layer 102. The shallow trench filling layer 103 may include silicon oxide or other isolation dielectrics. Optionally, before the oxide layer is formed along the inner surface of the shallow trench ST, the portion of the shallow trench ST located in the first hard mask layer 102 and the pad oxide layer 101 is widened, so that after the first hard mask layer 102 and the pad oxide layer 101 are subsequently removed, the leakage risk of the active area of ​​the semiconductor substrate 100 defined by the shallow trench ST can be reduced.

[0073] Fig.6D FIG. 1 is a schematic cross-sectional view of the shallow trench filling layer after planarization. Fig.6D As shown, the shallow trench filling layer 103 is planarized (eg, CMP) to expose the upper surface of the first hard mask layer 102 , and the remaining shallow trench filling layer 103 is filled in the shallow trench ST to form a shallow trench isolation STI.

[0074] Fig. 6E FIG. 4 is a schematic cross-sectional view after forming the second hard mask layer. Fig. 6E As shown, the second hard mask layer 104 (for example, silicon nitride) covers the shallow trench isolation STI and the first hard mask layer 102, and the total thickness of the first hard mask layer 102 and the second hard mask layer 104 is about Then, the position of the deep trench isolation DTI is defined by a photolithography process, and a deep trench DT is formed through the second hard mask layer 104, the first hard mask layer 102, the pad oxide layer 101 and a portion of the semiconductor substrate 100 by one or more etchings, and the depth D2 of the deep trench DT is greater than the depth D1 of the shallow trench ST. The depth D2 of the deep trench DT is, for example, in the range of 1.5 μm to 2.5 μm, and may further exceed 1.8 μm, for example, about 2 μm, and the opening width D3 of the deep trench DT is, for example, about 80 nm.

[0075] Fig. 6E The cross section shown is, for example, Figure 3 The plane diagram shown is taken from the AA' line. Figure 3and Fig. 6E Part of the deep trench DT is formed in the pixel area A1 of the semiconductor substrate 100 to separate the pixel area A1 to form a plurality of substrate units 110, and part of the shallow trench isolation STI is formed in each substrate unit 110, each substrate unit 110 includes a photosensitive area 110a and a charge reading area 110b separated by the shallow trench isolation STI. The deep trench DT extends from the pixel area A1 to the trench electrode lead-out area A2, as shown in FIG. Figure 3 As shown, the width of the deep trench DT located in the trench electrode lead-out region A2 is, for example, greater than the width of the deep trench DT located in the pixel region A1. The trench electrode lead-out region A2 may be disposed on one side or multiple sides of the pixel region A1.

[0076] Fig. 6F It is a schematic diagram of the cross section after the linear oxide layer is formed. Fig. 6F As shown, a linear oxide layer 105 is formed on the inner surface of the deep trench DT, and the linear oxide layer 105 covers the semiconductor substrate 100 exposed by the deep trench DT. Prior to this, the portion of the deep trench DT located in the second hard mask layer 104, the first hard mask layer 102 and the pad oxide layer 101 may be widened. Annealing may then be performed to repair lattice defects generated in the semiconductor substrate 100 during the formation of the deep trench DT, and the annealing temperature may be, for example, about 1100°C.

[0077] Figure 6G Schematic diagram of the cross section after the trench conductive layer is formed. Figure 6G As shown, a conductive material is deposited in the deep trench DT and on the second hard mask layer 104 to form a trench conductive layer 106, and the trench conductive layer 106 fills the deep trench DT and forms a certain thickness on the second hard mask layer 104. The trench conductive layer 106 can be made of a conductive material with good light-shielding performance. Optionally, the trench conductive layer 106 includes one or a combination of two or more of tungsten, tungsten silicide, titanium, titanium nitride and doped polysilicon. In this embodiment, the trench conductive layer 106 is, for example, doped polysilicon. After the deposition is completed, annealing can be performed to recrystallize the doped polysilicon to obtain a suitable grain size.

[0078] Figure 6H FIG. 4 is a schematic cross-sectional view of the trench conductive layer after planarization. Figure 6H As shown, the trench conductive layer 106 is planarized (eg, CMP) to expose the upper surface of the second hard mask layer 104 , and the remaining trench conductive layer 106 is filled in the deep trench DT.

[0079] Next, the trench conductive layer 106 of the pixel area A1 is etched back to below the surface of the semiconductor substrate 100 to form an etched-back space at the top of the deep trench DT of the pixel area A1. Figure 6I-1 and Figure 6I-2They are cross-sectional schematic diagrams of the pixel area and the trench electrode lead-out area after the trench conductive layer is etched back. Specifically, Figure 6I-1 For example, from Figure 3 The plan view shown is taken at the AA' line position. Figure 6I-2 For example, from Figure 3 The plane diagram shown is taken from the BB' line. Figure 6I-1 As shown, by etching back the trench conductive layer 106 of the pixel area A1, the thickness of the trench conductive layer 106 of the pixel area A1 is reduced, so that a portion of the depth of the deep trench DT of the pixel area A1 is not filled, forming an etching back space. After etching back, the upper surface of the trench conductive layer 106 of the pixel area A1 is lower than the upper surface of the semiconductor substrate 100. Figure 6I-2 As shown, in the trench electrode lead-out region A2, the trench conductive layer 106 still extends to the opening of the deep trench DT. The remaining trench conductive layer 106 is the trench electrode E1.

[0080] Figure 6J-1 and Figure 6J-2 They are schematic cross-sectional views of the pixel region and the trench electrode lead-out region after forming a deep trench filling layer. Figure 6J-1 and Figure 6J-2 As shown, a deep trench filling layer 107 is deposited, and the deep trench filling layer 107 covers the trench conductive layer 106 of the pixel area A1 and the trench electrode lead-out area A2 and forms a certain thickness on the second hard mask layer 104. The deep trench filling layer 107 may include silicon oxide or other isolation media. Here, the linear oxide layer 105 and the deep trench filling layer 107 are collectively referred to as the first isolation media. The trench electrode E1 is buried in the first isolation media and is insulated from the semiconductor substrate 100.

[0081] Figure 6K-1 and Figure 6K-2 The schematic cross-sectional views of the pixel area and the trench electrode lead-out area after the deep trench filling layer is planarized are shown respectively. Figure 6K-1 and Figure 6K-2 As shown, the deep trench filling layer 107 is planarized (such as CMP) to expose the upper surface of the second hard mask layer 104. After the above steps, a deep trench isolation DTI embedded in the semiconductor substrate 100 is formed on one side of the semiconductor substrate 100, wherein in the pixel area A1, the deep trench isolation DTI includes a linear oxide layer 105 filled in the deep trench DT, a portion of the trench electrode E1 and the deep trench filling layer 107, and in the trench electrode lead-out area A2, the deep trench isolation DTI includes a linear oxide layer 105 formed in the deep trench DT and a portion of the trench electrode E1, and the trench electrode E1 extends from the pixel area A1 to the trench electrode lead-out area A2.

[0082] Reference Figure 5In step S3, a gate dielectric layer, a floating gate FG, an inter-gate dielectric layer and a control gate CG extending from the photosensitive region 110a to the charge reading region 110b are stacked on the surface of the substrate unit 110, and a source region and a drain region are formed in the charge reading region 110b, respectively, on both sides of the corresponding control gate CG. The specific description is as follows.

[0083] Figure 6L-1 and Figure 6L-2 The cross-sectional schematic diagrams are respectively the pixel area and the trench electrode lead-out area after the hard mask layer is removed. Figure 6L-1 as well as Figure 6L-2 As shown, the second hard mask layer 104 and the first hard mask layer 102 are removed. After the removal, the deep trench isolation DTI protrudes from the surface of the semiconductor substrate 100 and is higher than the shallow trench isolation STI. The deep trench isolation DTI of the pixel area A1 is arranged around the periphery of each substrate unit 110. Afterwards, ion implantation can be performed to form a body region (not shown) in the charge reading area 110b. The ion implantation is, for example, a P-type implantation. Afterwards, the pad oxide layer 101 is removed, and a gate dielectric layer 108 is formed on the surface of the semiconductor substrate 100 after the removal.

[0084] Figure 6M-1 and Figure 6M-2 They are cross-sectional schematic diagrams of the pixel region and the trench electrode lead-out region after the floating gate material layer is formed. Figure 6M-1 and Figure 6M-2 As shown, polysilicon is then deposited to form a floating gate material layer 109 . The floating gate material layer 109 fills the gap between the shallow trench isolation STI and the deep trench isolation DTI and is higher than the deep trench isolation DTI by a certain thickness.

[0085] Figure 6N-1 and Figure 6N-2 They are cross-sectional schematic diagrams of the pixel area and the trench electrode lead-out area after the floating gate material layer is planarized. Figure 6N-1 and Figure 6N-2 As shown, the floating gate material layer 109 is planarized to expose the deep trench filling layer 107 of the pixel area A1 and the trench electrode E1 of the trench electrode lead-out area A2, and the remaining floating gate material layer 109 is separated by the deep trench isolation DTI.

[0086] Figure 6O-1 and Figure 6O-2 They are cross-sectional schematic diagrams of the pixel region and the trench electrode lead-out region after the inter-gate dielectric layer is formed. Figure 6O-1 and Figure 6O-2As shown, the deep trench filling layer 107 is etched back, so that the height of the deep trench isolation DTI of the pixel area A1 is reduced (still not lower than the surface of the semiconductor substrate 100), and a groove T1 is formed corresponding to the gap between the substrate units 110. Then, an inter-gate dielectric layer 111 is conformally formed on the semiconductor substrate 100, and then the inter-gate dielectric layer 111 of the trench electrode lead-out area A2 is removed to expose the floating gate material layer 109. The inter-gate dielectric layer 111 is, for example, an ONO layer including a lower silicon oxide layer, a silicon nitride layer, and an upper silicon oxide layer.

[0087] Figure 6P-1 and Figure 6P-2 They are cross-sectional schematic diagrams of the pixel region and the trench electrode lead-out region after the control gate material layer is formed. Figure 6P-1 and Figure 6P-2 As shown, doped polysilicon is deposited on the semiconductor substrate 100 to form a control gate material layer 112. Before forming the control gate material layer 112, the floating gate material layer 109 of the trench electrode lead-out region A2 may be retained or removed.

[0088] Figure 6Q-1 and Figure 6Q-3 It is a schematic cross-sectional view of the pixel region after forming the control gate and the floating gate. Figure 6Q-1 For example, from Figure 3 The plan view shown is taken at the AA' line position. Figure 6Q-3 For example, from Figure 3 The plan view shown is taken at the CC' line position. Figure 6Q-2 It is a schematic cross-sectional view of the trench electrode lead-out region after the trench electrode connecting block is formed. Figure 6Q-2 For example, from Figure 3 The plane diagram shown is taken from the BB' line. Figure 3 , Figure 6Q-1 , Figure 6Q-2 and Figure 6Q-3 As shown, a photolithography process is performed, and a floating gate FG and a control gate CG are formed on each substrate unit 110 through one or more etchings, and the control gate material layer 112 of the trench electrode lead-out area A2 is etched to form a trench electrode connecting block E1-T in the trench electrode lead-out area A2.

[0089] Specifically, an anisotropic etching process can be used to sequentially etch the control gate material layer 112, the inter-gate dielectric layer 111 and the floating gate material layer 109 of the pixel area A1, so that the remaining control gate material layer 112 forms a plurality of word lines (WL) in the pixel area A1. The word lines are located on more than two substrate units 110 and the deep trench isolation DTI therebetween, and are spaced apart by the inter-gate dielectric layer 111 and cover the floating gate FG. The word lines serve as the control gate CG.

[0090] The trench electrode connection block E1-T is formed in the trench electrode lead-out area A2 and is connected to the trench electrode E1. The trench electrode connection block E1-T is isolated from the control gate CG of the pixel area A1. A voltage can be applied to the trench electrode E1 using the trench electrode connection block E1-T. It should be noted that Figure 3 Multiple ends of the deep trench DT in the middle pixel area A1 extend laterally to the trench electrode lead-out area A2, but the present invention is not limited to this. Since the deep trenches DT in the pixel area A1 can be interconnected, in some embodiments, the structure of the deep trench DT extending laterally to the peripheral area A2 can be set as needed, for example, one end of the deep trench DT in the pixel area A1 extends to the trench electrode lead-out area A2.

[0091] Reference Figure 3 In the substrate unit 110, the width of the control gate CG of the photosensitive area 110a is, for example, greater than the width of the control gate CG of the charge reading area 110b. In the charge reading area 110b, a portion of the gate dielectric layer 108 is exposed on both sides of the control gate CG by etching. On this basis, the exposed gate dielectric layer 108 can be further removed, and sidewalls can be formed on the sides of the gate dielectric layer 108, the floating gate FG, the inter-gate dielectric layer 111, and the control gate CG. Then, source and drain ions are implanted in the exposed charge reading area 110b on both sides of the control gate CG to form a source region S and a drain region D.

[0092] Reference Figure 5 In step S4, the semiconductor substrate 100 is thinned from the other side to expose the deep trench isolation DTI, and a substrate electrode E2 is formed on the other side, the substrate electrode E2 is in contact with each substrate unit 110 and isolated from the trench electrode E1. A voltage can be applied to each substrate unit 110 using the substrate electrode E2.

[0093] Figure 6R It is a schematic cross-sectional view after thinning the semiconductor substrate from the other side. Figure 6R The cross section shown is, for example, Figure 3 The plane diagram shown is taken from the AA' line. Figure 6R As shown, the semiconductor substrate 100 is thinned from the side away from the control gate CG to expose the deep trench isolation DTI, for example, to expose the trench electrode E1 in the deep trench DT. Part of the trench electrode E1 may be removed during the thinning process. At this time, the semiconductor substrate 100 of the pixel area A1 is penetrated by the deep trench isolation DTI, thereby forming a complete physical isolation between the substrate units 110.

[0094] like Figure 6SAs shown, photolithography and etching processes are performed on the thinned surface of the semiconductor substrate 100 to form a first groove T2 at the exposed deep trench isolation DTI, and the inner surface of the first groove T2 exposes the trench electrode E1 and the substrate unit 110 around the trench electrode. The cross section of the first groove T2 is, for example, an inverted trapezoid.

[0095] like Figure 6T As shown, a dielectric material is deposited in the first groove T2 and on the surface of the substrate unit 110 to form a second isolation dielectric 113 , which fills the first groove T2 and covers the surface of the substrate unit 110 .

[0096] like Figure 6U As shown, a second groove T3 is formed corresponding to the first groove T2 through a photolithography process and an etching process, the bottom of the second groove T3 is located at the upper part of the first groove T2, and the side surface of the second groove T3 exposes the substrate unit 110 around the deep trench isolation DTI. The bottom surface of the second groove T3 exposes the second isolation medium 113 covering the trench electrode E1, and the bottom surface of the second groove T3 can also expose the substrate unit 110 around the deep trench isolation DTI.

[0097] Here, the second isolation dielectric 113 may be made of a high dielectric constant material (dielectric constant k is greater than 3.9). The use of a high dielectric constant material can increase the barrier (interface passivation) at the interface between the first groove T2 and the semiconductor substrate 100, reduce the probability of photoelectrons being captured at the interface, and help improve the photoelectric conversion efficiency. The material of the high dielectric constant layer may include Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST) or TiO2, etc.

[0098] like Figure 6V As shown, a conductive material is filled in the second groove T3 to form a substrate electrode E2. The substrate electrode E2 may include one of titanium, titanium nitride, tantalum nitride, aluminum, copper alloy and aluminum alloy, or a combination thereof.

[0099] The vertical charge transfer imaging sensor and the method for manufacturing the vertical charge transfer imaging sensor described in the embodiments of the present invention have the following technical effects: the deep trench isolation DTI formed on one side of the semiconductor substrate 100 forms physical isolation between each pixel, which can ensure the photoelectric conversion efficiency of the vertical charge transfer imaging sensor, effectively avoid crosstalk between pixels, and is conducive to pixel miniaturization; the substrate electrode E2 is formed on the other side of the semiconductor substrate 100 (i.e., the side away from the control gate CG), and does not need to occupy the area of ​​the side of the control gate CG, which is conducive to pixel miniaturization; the trench electrode E1 in the deep trench isolation DTI provides an operable electrode end for the vertical charge transfer imaging sensor, and cooperates with other electrode ends in the sensor (such as electrode ends connected to the control gate, source region, drain region, and substrate electrode respectively), so as to realize a variety of operation modes. For example, the trench electrode E1 can be used in coupling with the substrate electrode E2. During the photosensitization process, by applying a positive bias voltage between the substrate electrode E2 and the trench electrode E1, the potential barrier at the interface between the deep trench isolation and the substrate unit can be increased, so that the probability of photoelectrons being captured at the interface is reduced, which helps to improve the photoelectric conversion efficiency and improve the dark current and white pixel problems. In addition, the positive bias voltage is flexible and adjustable, and the isolation medium between the trench electrode and the substrate unit can be made of a low dielectric constant material (dielectric constant is less than or equal to 3.9), which is low in cost. For another example, after completing a photosensitization and charge reading operation, a negative bias voltage can be applied between the substrate electrode and the trench electrode to reset (reset), releasing the charge captured in the deep trench isolation boundary area, which helps to improve the background noise during the next photosensitization and charge reading operation.

[0100] It should be noted that the embodiments in this specification are described in a progressive manner, and each part focuses on the differences from the previous part. The same and similar parts between the parts can be referenced to each other.

[0101] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A vertical charge transfer imaging sensor, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate comprises a pixel region; Shallow trench isolation and deep trench isolation are formed on one side of the semiconductor substrate, the deep trench isolation includes a trench electrode and a first isolation medium filled in a deep trench formed on one side of the semiconductor substrate, the first isolation medium insulates the trench electrode from the semiconductor substrate, the deep trench isolation defines a plurality of substrate units in the pixel area, each of the substrate units includes a photosensitive area and a charge reading area separated by the shallow trench isolation, and the trench electrode forms an electrode terminal; A floating gate, an inter-gate dielectric layer and a control gate are stacked on the surface of each substrate unit and extend to cover the photosensitive area and the charge reading area, and the substrate unit and the control gate respectively form two plates of a capacitor corresponding to the photosensitive area; as well as A substrate electrode is formed on the other side of the semiconductor substrate, wherein the substrate electrode contacts the electrode plate formed by each substrate unit and is isolated from the trench electrode.

2. The vertical charge transfer imaging sensor according to claim 1, wherein: The semiconductor substrate includes a trench electrode lead-out region located at the periphery of the pixel region, the trench electrode extends from the pixel region to the trench electrode lead-out region along the deep trench, and extends from the bottom to the top of the deep trench in the trench electrode lead-out region.

3. The vertical charge transfer imaging sensor of claim 2, wherein: Also includes: The trench electrode connecting block is formed in the trench electrode lead-out region and covers the trench electrode.

4. The vertical charge transfer imaging sensor of claim 1, wherein: In the pixel area, the first isolation medium filled in the deep trench includes a linear oxide layer and a deep trench filling layer, the linear oxide layer is between the trench electrode and the semiconductor substrate, and the deep trench filling layer covers the trench electrode and is located at the top of the deep trench.

5. The vertical charge transfer imaging sensor of claim 1, wherein: The substrate electrode is arranged at the other side of the semiconductor substrate corresponding to the deep trench of the pixel region, and a second isolation medium is provided between the substrate electrode and the trench electrode.

6. The vertical charge transfer imaging sensor of claim 5, wherein: The second isolation medium includes a high dielectric constant material.

7. The vertical charge transfer imaging sensor of claim 1, wherein: The control gates formed on the substrate units are connected to form a plurality of word lines, and each of the word lines spans across a plurality of the substrate units.

8. A method for manufacturing a vertical charge transfer imaging sensor, characterized in that: The production method comprises: Providing a semiconductor substrate, the semiconductor substrate comprising a pixel region; A shallow trench isolation and a deep trench isolation are formed on one side of the semiconductor substrate, wherein the deep trench isolation includes a deep trench penetrating a portion of the semiconductor substrate and a trench electrode and a first isolation medium filled in the deep trench, wherein the first isolation medium insulates the trench electrode from the semiconductor substrate, the deep trench isolation defines a plurality of substrate units in the pixel region, each of the substrate units includes a photosensitive region and a charge reading region separated by the shallow trench isolation, and the trench electrode forms an electrode terminal; A gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate are stacked on the surface of each substrate unit, wherein the floating gate, the inter-gate dielectric layer and the control gate extend to cover the photosensitive area and the charge reading area, and the substrate unit and the control gate respectively form two plates of a capacitor corresponding to the photosensitive area; and The semiconductor substrate is thinned from the other side to form a substrate electrode, wherein the substrate electrode is in contact with the plate formed by each substrate unit and isolated from the trench electrode.

9. The method of claim 8, wherein: Forming the shallow trench isolation and the deep trench isolation on one side of the semiconductor substrate includes: A pad oxide layer and a first hard mask layer are stacked on the surface of the semiconductor substrate, and the shallow trench isolation is formed, wherein the shallow trench isolation penetrates the first hard mask layer, the pad oxide layer and a portion of the semiconductor substrate; forming a second hard mask layer, wherein the second hard mask layer covers the first hard mask layer and the shallow trench isolation; forming the deep trench, wherein the deep trench penetrates the second hard mask layer, the first hard mask layer, the pad oxide layer and a portion of the semiconductor substrate; forming a linear oxide layer and a trench conductive layer in the deep trench, wherein the linear oxide layer covers the semiconductor substrate exposed by the deep trench, the trench conductive layer covers the linear oxide layer and fills the deep trench, and the top surface of the trench conductive layer is higher than the surface of the semiconductor substrate; Etching back the trench conductive layer in the pixel area to below the surface of the semiconductor substrate to form an etched-back space at the top of the deep trench in the pixel area, and the remaining trench conductive layer is a trench electrode; and A deep trench filling layer is formed in the back-etching space, and the linear oxide layer and the deep trench filling layer serve as the first isolation medium.

10. The production method according to claim 8 or 9, characterized in that: The semiconductor substrate includes a trench electrode lead-out region located at the periphery of the pixel region, the trench electrode extends from the pixel region to the trench electrode lead-out region along the deep trench, and extends from the bottom to the top of the deep trench in the trench electrode lead-out region.

11. The production method according to claim 8 or 9, characterized in that: Forming the substrate electrode comprises: forming a first groove from the other side of the semiconductor substrate, wherein the first groove exposes the substrate unit; forming a second isolation medium on the other side, wherein the second isolation medium fills the first groove and covers the surface of the substrate unit; forming a second groove, wherein the bottom of the second groove is located at the upper part of the first groove, the side surface of the second groove exposes the substrate unit, and the trench electrode is covered by the second isolation medium; and The second groove is filled with a conductive material to form the substrate electrode.

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