Infrared detector chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor photoelectric devices, and provides an infrared detector chip, which comprises a substrate and an epitaxial structure grown on the substrate, the epitaxial structure comprises a mesa layer, the outer wall of the partial structure of the mesa layer far away from the substrate is covered with a first passivation layer, and the outer wall of the partial structure of the mesa layer far away from the substrate is covered with a second passivation layer. And a second passivation layer covers the outer wall of the other part, close to the substrate, of the mesa layer. The invention also provides a preparation method of the infrared detector chip. Compared with the traditional mode of adopting one passivation layer, the mode of adopting multiple passivation layers can effectively improve the depth and gradient of the passivation side wall and improve the growth uniformity of the passivation layers.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor optoelectronic devices, and in particular to an infrared detector chip and a preparation method thereof. Background Art

[0002] Antimonide superlattice materials based on III-V semiconductors have the advantages of wide-band precise adjustment, high quantum efficiency, good uniformity over a large area, high operating temperature and low preparation cost. They can simultaneously meet the requirements of the third-generation infrared detectors for high detection rate, large array, multi-band, low power consumption and low cost.

[0003] Infrared detectors detect and identify targets through the difference between infrared radiation and background radiation. When the infrared radiation of the target and the background are the same, the target cannot be effectively identified. In addition, when the dynamic target itself changes, the wavelength corresponding to its infrared radiation peak will move, which greatly reduces the detection accuracy of the infrared detection system and may even make it impossible to detect the target. This situation can be effectively avoided when using two-color detection. Compared with monochrome detectors, two-color detectors can provide stronger contrast to effectively identify targets. At the same time, they have the advantages of faster detection speed, wider detection band range, rich feature information, strong resolution, and anti-interference. It can reduce false alarm rate and improve detection accuracy. It has broad application prospects in guidance, early warning, search and tracking systems.

[0004] There are two signal output methods for dual-band detectors. One is to use two ohmic contact bumps to connect to each absorption layer respectively, and the dual-band can apply bias to output signals at the same time; the other is to use one ohmic contact bump to select the output signal through bias. The former is difficult to achieve a small-pitch focal plane array, and the manufacturing process is complicated. Therefore, the single bump bias selection method is currently the mainstream method for preparing dual-band infrared detector chips. For the single-bump dual-band superlattice infrared detection chip preparation technology, the table etching and sidewall passivation methods have a great influence on the device performance. Since the dual-band material is much thicker than the epitaxial layer of the single-band, which is basically twice that of the single-band, the sidewall exposure time is longer during the etching process, the probability of adsorbing various charged particles on the surface increases, and long-term etching will increase the etching damage of the long-band material; in addition, the passivation layer is more difficult to grow uniformly on the deep and steep side, and because the long-band and medium-band materials are composed of different materials, the sidewalls formed by etching have different optimal passivation methods and dielectric film selection. The above etching and passivation processes are prone to introduce surface states, resulting in sidewall inversion or oxidation, which in turn increases device sidewall leakage current and causes high device noise. Summary of the invention

[0005] The object of the present invention is to provide an infrared detector chip and a method for preparing the same, which can at least solve some of the defects in the prior art.

[0006] To achieve the above-mentioned purpose, an embodiment of the present invention provides the following technical solution: an infrared detector chip, comprising a substrate and an epitaxial structure grown on the substrate, the epitaxial structure comprising a mesa layer, a portion of the structural outer wall of the mesa layer away from the substrate is covered with a first passivation layer, and another portion of the structural outer wall of the mesa layer close to the substrate is covered with a second passivation layer.

[0007] Furthermore, the outer wall of the first passivation layer is covered with the second passivation layer.

[0008] Furthermore, the mesa layer includes a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer that are grown in sequence, the first passivation layer covers the outer wall of the long-band absorption layer and the outer wall of the upper contact layer, and the second passivation layer covers the outer wall of the mid-band absorption layer and the outer wall of the barrier layer.

[0009] Furthermore, the first passivation layer is a composite passivation film formed by a sulfide film and an Al2O3 film, and the second passivation layer is an Al2O3 film.

[0010] Furthermore, the long-wavelength band absorption layer is an InAs / GaSb superlattice absorption layer, and the mid-wavelength band absorption layer is an InAs / GaSb superlattice absorption layer or an InAs / InAsSb superlattice absorption layer.

[0011] Furthermore, an outer wall of the barrier layer is flush with an outer wall of the mid-waveband absorption layer, and an outer wall of the upper contact layer is flush with an outer wall of the long-waveband absorption layer.

[0012] Furthermore, the width of the barrier layer is greater than the width of the long-wavelength absorption layer, and the width of the long-wavelength absorption layer plus the width of the first passivation layer is equal to the width of the barrier layer.

[0013] Furthermore, the epitaxial structure includes a lower contact layer grown on the substrate, the mesa layer is grown on the lower contact layer, and the second passivation layer also covers the plane of the lower contact layer exposed outside the mid-band absorption layer.

[0014] The embodiment of the present invention provides another technical solution: a method for preparing an infrared detector chip, comprising the following steps:

[0015] S1, sequentially growing a lower contact layer, a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer on a substrate;

[0016] S2, etching the upper contact layer and the long-wavelength absorption layer to the barrier layer from the upper contact layer toward the substrate;

[0017] S3, performing a first passivation on the upper contact layer and the outer wall of the long-wavelength band absorption layer to form a first passivation layer;

[0018] S4, continue etching the barrier layer and the mid-band absorption layer to the lower contact layer;

[0019] S5, performing a second passivation on the outer wall of the first passivation layer, the outer wall of the barrier layer, the outer wall of the mid-band absorption layer, and the plane of the lower contact layer exposed outside the mid-band absorption layer to form a second passivation layer;

[0020] S6, opening a hole in the second passivation layer and growing a contact electrode.

[0021] Furthermore, the contact electrode is made of gold.

[0022] Compared with the prior art, the beneficial effect of the present invention is that by adopting a multi-layer passivation layer (i.e., step-by-step passivation) method, compared with the traditional method of adopting a single passivation layer (i.e., one-time passivation), the passivation sidewall depth and inclination can be effectively improved, and the uniformity of passivation layer growth can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the preparation steps of a traditional infrared detector chip;

[0024] Figure 2 A schematic diagram of the steps for preparing an infrared detector chip provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram showing a performance comparison between an infrared detector chip provided in an embodiment of the present invention and a traditional infrared detector chip. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] See also Figure 2An embodiment of the present invention provides an infrared detector chip, including a substrate and an epitaxial structure grown on the substrate, wherein the epitaxial structure includes a mesa layer, a portion of the mesa layer away from the substrate is covered with a first passivation layer on its outer wall, and another portion of the mesa layer close to the substrate is covered with a second passivation layer on its outer wall. In this embodiment, by adopting a multi-layer passivation layer (i.e., step-by-step passivation) method, compared with the traditional method of adopting a single passivation layer (i.e., single passivation), the passivation sidewall depth and inclination can be effectively improved, and the uniformity of the passivation layer growth can be improved. Specifically, conventional chips such as Figure 1 As shown, only one passivation is performed, and the exposure time of the outer wall of the epitaxial structure during the etching process is long, which will make the probability of surface adsorption of various charged particles higher and the surface oxidation degree higher, and the etching time of the epitaxial structure etched first will be too long, and the etching damage degree will become higher accordingly, which will eventually lead to poor side wall depth and inclination, and the uniformity of passivation layer growth is also low. The present application cleverly uses two passivations, supplemented by two etchings, which can reduce the exposure time of the etched epitaxial structure, reduce the probability of surface adsorption of various charged particles and the surface oxidation degree, and through the protection of the first passivation layer, the etching time of the epitaxial structure etched first can be shortened (divided into two etchings can also shorten the etching time of the epitaxial structure etched first), reduce its etching damage, thereby improving the passivation side wall depth and inclination, and improving the uniformity of passivation layer growth.

[0028] See also Figure 2 , the outer wall of the first passivation layer is covered with the second passivation layer. In this embodiment, during the second passivation, the second passivation layer can also be directly covered on the outside of the first passivation layer to simplify the growth process, and the thickness of the passivation layer on the outer wall of the part of the structure of the mesa layer away from the substrate can also be increased to improve chip performance.

[0029] See also Figure 2, the mesa layer includes a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer that are grown in sequence, the first passivation layer covers the outer wall of the long-band absorption layer and the outer wall of the upper contact layer, and the second passivation layer covers the outer wall of the mid-band absorption layer and the outer wall of the barrier layer. The epitaxial structure includes a lower contact layer, a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer that are grown in sequence on the substrate. In this embodiment, when the epitaxial structure uses a lower contact layer, a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer, the first passivation layer can cover the outer walls of the long-band absorption layer and the upper contact layer after etching, that is, after the upper contact layer and the long-band absorption layer are etched first, the first passivation layer is immediately covered on their outer walls, so that the exposure time of the outer wall of the long-band absorption layer can be reduced, and the etching time of the long-band material can be shortened. In another embodiment, the second passivation layer covers the outer wall of the first passivation layer, the outer wall of the barrier layer, the outer wall of the mid-band absorption layer, and the plane of the lower contact layer exposed outside the mid-band absorption layer. After the first passivation layer is completed, etching continues under the protection of the first passivation layer. After etching is completed, the second passivation layer is produced, and the second passivation layer protects the first passivation layer and other epitaxial structures after etching. Finally, the production of the infrared detector chip can be completed by performing the gold growth process. In the two passivations, different materials can be selected for passivation as needed. For example, the first passivation layer can be selected as a composite passivation film formed by a sulfide film and an Al2O3 film, and the second passivation layer can be selected as an Al2O3 film. As for how to choose the passivation material, it can be selected as needed. Preferably, when the chip has a long-band absorption layer and a medium-band absorption layer, and the long-band absorption layer is grown after the medium-band absorption layer, a sulfide film and an Al2O3 film can be used to form a composite passivation film to cover the outer wall of the long-band absorption layer, and an Al2O3 film can be used to cover the outer wall of the medium-band absorption layer. Different passivation methods are selected through long-band and medium-band tests to improve the side wall state and improve the quality of the passivation layer. Preferably, the long-band absorption layer is an InAs / GaSb superlattice absorption layer, and the medium-band absorption layer is an InAs / GaSb superlattice absorption layer or an InAs / InAsSb superlattice absorption layer.

[0030] See also Figure 2 , the outer wall of the barrier layer is flush with the outer wall of the mid-wavelength absorption layer, and the outer wall of the upper contact layer is flush with the outer wall of the long-wavelength absorption layer. Figure 2In step d, it can be seen that the outer walls of the upper contact layer and the long-band absorption layer are flush, and the outer wall of the barrier layer and the outer wall of the mid-band absorption layer are flush. Preferably, the width of the barrier layer is greater than the width of the long-band absorption layer, and the width of the long-band absorption layer plus the width of the first passivation layer is equal to the width of the barrier layer. The upper contact layer and the long-band absorption layer can be regarded as a whole, and the barrier layer and the mid-band absorption layer can be regarded as a whole. They form a boss structure, and the widths of the two are different, and the upper width is smaller than the lower width. This makes it easier to fill the first passivation layer and make the upper and lower parts flush, so as to obtain a chip with higher consistency.

[0031] See also Figure 2 An embodiment of the present invention provides a method for preparing an infrared detector chip, comprising the following steps: S1, sequentially growing a lower contact layer, a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer on a substrate; S2, etching the upper contact layer and the long-band absorption layer from the upper contact layer toward the substrate to the barrier layer; S3, performing a first passivation on the outer walls of the upper contact layer and the long-band absorption layer to form a first passivation layer; S4, continuing to etch the barrier layer and the mid-band absorption layer to the lower contact layer; S5, performing a second passivation on the outer wall of the first passivation layer, the outer wall of the barrier layer, the outer wall of the mid-band absorption layer and the plane of the lower contact layer exposed outside the mid-band absorption layer to form a second passivation layer; S6, opening a hole in the second passivation layer and growing a contact electrode. In this embodiment, the process of two etchings and two passivations is shown. The step-by-step etching method is used for chip preparation, which can effectively reduce the exposure time in the long-wave region, reduce the probability of surface adsorption of various charged particles and the degree of surface oxidation, shorten the etching time of long-wave materials, and reduce their etching damage. The step-by-step passivation method is used for chip preparation, which can effectively improve the passivation sidewall depth and inclination, improve the uniformity of passivation layer growth, and can select different passivation methods through long-wave and medium-wave tests to improve the sidewall state and improve the quality of the passivation layer. The above steps correspond to Figure 2 The four figures a, b, c, d, e and f in the figure show the entire logic manufacturing steps of the chip, which is different from the manufacturing process of traditional chips. Preferably, the material of the contact electrode is gold.

[0032] The following is a specific implementation method:

[0033] In order to compare the advantages of the present invention, a two-inch dual-band superlattice material is cut in half, the first half is recorded as sample a, and the conventional chip processing method (such as the attached Figure 1 ) to prepare the device; the second is recorded as sample b, according to the present invention (such as the attached Figure 2) proposed a chip processing method to prepare the device, the mesa etching adopts the inductively coupled plasma etching technology, the passivation 1 adopts the method of growing a sulfide film and an Al2O3 film to form a composite passivation film, and the passivation 2 adopts the method of growing a single-layer Al2O3 film.

[0034] After processing, the device is bonded to the circuit substrate through wires, packaged in a vacuum dewar, and tested at liquid nitrogen temperature. Through testing, the corresponding curves of dark current density and bias voltage of the devices prepared by the above two different chip processing technologies are shown in the attached figure. Figure 3 As shown, the effect of the new technology on suppressing the dark current of the device can be evaluated. From the curve, it can be seen that the dark current density of the solution of the present invention is smaller.

[0035] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An infrared detector chip, comprising a substrate and an epitaxial structure grown on the substrate, characterized in that: The epitaxial structure comprises a mesa layer, a portion of the structure outer wall of the mesa layer away from the substrate is covered with a first passivation layer, and another portion of the structure outer wall of the mesa layer close to the substrate is covered with a second passivation layer.

2. The infrared detector chip according to claim 1, characterized in that: The outer wall of the first passivation layer is covered with the second passivation layer.

3. The infrared detector chip according to claim 1, characterized in that: The mesa layer includes a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer that are grown in sequence, the first passivation layer covers the outer wall of the long-band absorption layer and the outer wall of the upper contact layer, and the second passivation layer covers the outer wall of the mid-band absorption layer and the outer wall of the barrier layer.

4. The infrared detector chip according to claim 3, characterized in that: The first passivation layer is a composite passivation film formed by a sulfide film and an Al2O3 film, and the second passivation layer is an Al2O3 film.

5. The infrared detector chip according to claim 3, characterized in that: The long-waveband absorption layer is an InAs / GaSb superlattice absorption layer, and the medium-waveband absorption layer is an InAs / GaSb superlattice absorption layer or an InAs / InAsSb superlattice absorption layer.

6. An infrared detector chip as claimed in claim 3, characterized in that: The outer wall of the barrier layer is flush with the outer wall of the mid-waveband absorption layer, and the outer wall of the upper contact layer is flush with the outer wall of the long-waveband absorption layer.

7. An infrared detector chip as claimed in claim 6, characterized in that: The width of the barrier layer is greater than the width of the long-wavelength absorption layer, and the width of the long-wavelength absorption layer plus the width of the first passivation layer is equal to the width of the barrier layer.

8. The infrared detector chip according to claim 1, characterized in that: The epitaxial structure includes a lower contact layer grown on the substrate, the mesa layer is grown on the lower contact layer, and the second passivation layer also covers the plane of the lower contact layer exposed outside the mid-band absorption layer.

9. A method for preparing an infrared detector chip, characterized in that: The steps include: S1, sequentially growing a lower contact layer, a mid-band absorption layer, a barrier layer, a long-band absorption layer and an upper contact layer on a substrate; S2, etching the upper contact layer and the long-wavelength absorption layer to the barrier layer from the upper contact layer toward the substrate; S3, performing a first passivation on the upper contact layer and the outer wall of the long-wavelength band absorption layer to form a first passivation layer; S4, continue etching the barrier layer and the mid-band absorption layer to the lower contact layer; S5, performing a second passivation on the outer wall of the first passivation layer, the outer wall of the barrier layer, the outer wall of the mid-band absorption layer, and the plane of the lower contact layer exposed outside the mid-band absorption layer to form a second passivation layer; S6, opening a hole in the second passivation layer and growing a contact electrode.

10. The method for preparing the infrared detector chip according to claim 9, characterized in that: The contact electrode is made of gold.

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