LED, manufacturing method thereof and display panel

Abstract

The invention relates to an LED, a manufacturing method thereof and a display panel. The LED manufacturing method comprises the following steps: providing an island-shaped epitaxial structure; depositing a photoresist layer on the island-shaped epitaxial structure, and performing patterning treatment on the photoresist layer to expose part of the surface of the island-shaped epitaxial structure; evaporating a first sub-electrode on the surface of the exposed island-shaped epitaxial structure; a passivation layer is deposited on the island-shaped epitaxial structure; wherein the passivation layer is used for coating the first sub electrode; carrying out patterning processing on the passivation layer so as to expose the first sub-electrode; manufacturing a second sub-electrode on the exposed first sub-electrode; wherein the first sub-electrode and the second sub-electrode form an electrode of the LED. According to the manufacturing method, on one hand, the lower-layer semiconductor structure can be protected from being excessively etched through the first sub-electrode, and on the other hand, the formed first sub-electrode can also be directly used as a part of a chip electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LED and a manufacturing method thereof, and a display panel. Background Art

[0002] Micro LED display technology refers to a display technology that uses self-luminous micron-sized LEDs as light-emitting pixel units and assembles them on a driving panel to form a high-density LED array. Due to the small size, high integration and self-luminescence of Micro LED chips, Micro LEDs have greater advantages in brightness, resolution, contrast, energy consumption, service life, response speed and thermal stability compared to LCD and OLED in terms of display. It is considered to be the mainstream direction of future display technology and has extremely high application potential in VR / AR, high-definition, flexible, wearable and other display fields.

[0003] According to the Micro LED chip process flow, a wafer needs to complete step etching, isolation groove etching, passivation layer etching, electrode evaporation, cutting and cleaving processes to obtain a Micro LED chip. In the passivation layer etching stage, the existing etching process may have the following problems: 1. The thickness of the yellow photoresist is uneven, and some areas have the problem of incomplete passivation etching, resulting in an increase in voltage (VF) 2. In order to ensure that the passivation layer is etched cleanly, it is often necessary to set a sufficient over-etching amount. If the over-etching amount is set too much, the semiconductor layer under the passivation layer may be thin, with little etching residue or completely etched away, thereby affecting the photoelectric performance of the product. At the same time, there is no good detection method in the above etching process to monitor whether the passivation layer is etched cleanly or whether it is over-etched too much. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide an LED and a method for manufacturing the same, and a display panel, aiming to solve the problem of incomplete etching of the passivation layer leading to voltage increase and over-etching leading to little etching residue or complete etching.

[0005] A method for manufacturing an LED, comprising:

[0006] Providing an island epitaxial structure;

[0007] Depositing a photoresist layer on the island epitaxial structure, and patterning the photoresist layer so that a portion of the surface of the island epitaxial structure is exposed;

[0008] Vapor depositing a first sub-electrode on the exposed surface of the island epitaxial structure;

[0009] Depositing a passivation layer on the island epitaxial structure; wherein the passivation layer covers the first sub-electrode;

[0010] performing patterning on the passivation layer so that the first sub-electrode is exposed; and

[0011] A second sub-electrode is fabricated on the exposed first sub-electrode; wherein the first sub-electrode and the second sub-electrode constitute electrodes of the LED.

[0012] The above-mentioned LED manufacturing method, by evaporating a layer of first sub-electrode on the island-shaped epitaxial structure, and the electrode is usually made of metal or alloy material, and then by virtue of the blocking effect of the first sub-electrode (equivalent to a hard mask), during the subsequent passivation layer patterning process, the underlying semiconductor layer of the first sub-electrode can be protected from over-etching and incomplete etching, thereby playing an etching barrier role; at the same time, the first sub-electrode can also be directly used as a part of the chip electrode, and constitute the chip electrode together with the second sub-electrode.

[0013] Optionally, the first sub-electrode includes a single-layer metal structure or a multi-layer metal stacking structure.

[0014] Optionally, the first sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

[0015] Optionally, the second sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

[0016] Optionally, the method for manufacturing the island epitaxial structure comprises:

[0017] Providing an epitaxial layer; the epitaxial layer includes a substrate, a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer;

[0018] depositing a current spreading layer on the second conductive semiconductor layer;

[0019] Step etching and channel etching are performed on the epitaxial layer including the current spreading layer to form the island epitaxial structure; wherein the first sub-electrode is formed on the surface of the current spreading layer and the first conductive type semiconductor layer.

[0020] Based on the same inventive concept, the present application also provides an LED, which is manufactured using the aforementioned LED manufacturing method.

[0021] The above-mentioned LED is manufactured by adopting the above-mentioned LED manufacturing method, and the above-mentioned LED manufacturing method is to evaporate a layer of first sub-electrode on the island-shaped epitaxial structure, and the electrode is usually made of metal or alloy material. Then, by virtue of the blocking effect of the first sub-electrode (equivalent to a hard mask), during the subsequent passivation layer patterning process, the lower semiconductor layer of the first sub-electrode can be protected from over-engraving and incomplete etching, thereby avoiding voltage increase caused by incomplete etching or over-engraving affecting the photoelectric performance of the product; thereby greatly improving the photoelectric performance and stability of the LED.

[0022] Optionally, the first sub-electrode includes a single-layer metal structure or a multi-layer metal stacking structure.

[0023] Optionally, the first sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

[0024] Optionally, the second sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

[0025] Based on the same inventive concept, the present application also provides a display panel, which includes a driving circuit and a light-emitting device electrically connected to the driving circuit; wherein the light-emitting device adopts the LED described above.

[0026] The light-emitting device in the display panel adopts the aforementioned LED, and the LED manufactured by the aforementioned LED manufacturing method has greatly improved photoelectric performance and stability. Ultimately, the stability and photoelectric performance of the display panel including the LED are also greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic flow chart of a method for manufacturing an LED in an embodiment;

[0028] Figure 2 for Figure 1 Flow chart of sub-steps of step S100;

[0029] Figure 3-Figure 6 For the corresponding Figure 2 Schematic diagram of structural changes in the method steps;

[0030] Figure 7-Figure 13 For the corresponding Figure 1 Schematic diagram of the structural changes in the method steps.

[0031] Description of reference numerals:

[0032] 10-island epitaxial structure; 100-substrate; 200-first conductive semiconductor layer; 300-active layer; 400-second conductive semiconductor layer; 500-current spreading layer; PR1-photoresist layer; 20-passivation layer; MT-first sub-electrode; PD-second sub-electrode; PR2-photoresist layer; H1-first opening; H2-second opening. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., can be used here to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0038] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0039] Micro LED display technology refers to a display technology that uses self-luminous micron-sized LEDs as light-emitting pixel units and assembles them on a driving panel to form a high-density LED array. Due to the small size, high integration and self-luminescence of Micro LED chips, Micro LEDs have greater advantages in brightness, resolution, contrast, energy consumption, service life, response speed and thermal stability compared to LCD and OLED in terms of display. It is considered to be the mainstream direction of future display technology and has extremely high application potential in VR / AR, high-definition, flexible, wearable and other display fields.

[0040] According to the Micro LED chip process flow, a wafer needs to complete step etching, isolation groove etching, passivation layer etching, electrode evaporation, cutting and cleaving processes to obtain a Micro LED chip. In the passivation layer etching stage, the existing etching process may have the following problems: 1. The thickness of the yellow photoresist is uneven, and some areas have the problem of incomplete passivation etching, resulting in an increase in voltage (VF) 2. In order to ensure that the passivation layer is etched cleanly, it is often necessary to set a sufficient over-etching amount. If the over-etching amount is set too much, the semiconductor layer under the passivation layer may be thin, with little etching residue or completely etched away, thereby affecting the photoelectric performance of the product. At the same time, there is no good detection method in the above etching process to monitor whether the passivation layer is etched cleanly or whether it is over-etched too much.

[0041] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.

[0042] Please refer to Figure 1 , is a flowchart of the steps of an LED manufacturing method provided in the present application. The method may include: S100-S600.

[0043] Step S100, providing an island epitaxial structure;

[0044] Step S200, depositing a photoresist layer on the island epitaxial structure, and patterning the photoresist layer so that a portion of the surface of the island epitaxial structure is exposed;

[0045] Step S300, evaporating a first sub-electrode on the exposed surface of the island epitaxial structure;

[0046] Step S400, depositing a passivation layer on the island epitaxial structure; wherein the passivation layer covers the first sub-electrode;

[0047] Step S500, patterning the passivation layer to expose the first sub-electrode; and

[0048] Step S600, manufacturing a second sub-electrode on the exposed first sub-electrode; wherein the first sub-electrode and the second sub-electrode constitute electrodes of the LED.

[0049] The above-mentioned LED manufacturing method, by evaporating a layer of first sub-electrode on the island-shaped epitaxial structure, and the electrode is usually made of metal or alloy material, and then by virtue of the blocking effect of the first sub-electrode (equivalent to a hard mask), during the subsequent passivation layer patterning process, the underlying semiconductor layer of the first sub-electrode can be protected from over-etching and incomplete etching, thereby playing an etching barrier role; at the same time, the first sub-electrode can also be directly used as a part of the chip electrode, and constitute the chip electrode together with the second sub-electrode.

[0050] Specifically, you can refer to Figure 7-Figure 13 . This is a schematic diagram of the structural changes of the LED manufacturing method embodiment provided by the present application. Figure 7 , which is an example diagram of the island epitaxial structure 10 provided in the present application. Figure 7In the embodiment, the island epitaxial structure 10 may include a substrate 100, a first conductive semiconductor layer 200, an active layer 300, a second conductive semiconductor layer 400 and a current spreading layer 500. In other embodiments, the island epitaxial structure 10 may only include a substrate 100, a first conductive semiconductor layer 200, an active layer 300 and a second conductive semiconductor layer 400. The island epitaxial structure 10 may further include other specific functional layers according to the specific light-emitting wavelength and device characteristics of the LED. For example, when the LED mainly emits wavelengths in the blue-green band, in addition to the substrate 100 mainly using gallium nitride semiconductor materials, the island epitaxial structure 10 may further include an ohmic contact layer, a hole blocking layer, an electron blocking layer, a buffer layer, a stress release layer, etc. The above-mentioned ohmic contact layer, hole blocking layer, electron blocking layer, buffer layer, and stress release layer can be arranged with reference to the arrangement position of the existing blue-green LED, and this application will not be further described. When the LED mainly emits red light, in addition to the substrate 100 using gallium arsenide material, the island-shaped epitaxial structure 10 may further include a bonding layer, a buffer layer, a stress release layer, etc. Among them, the bonding layer is mainly involved in the process of replacing the gallium arsenide substrate. For details, please refer to the existing red light LED chip substrate replacement process, and this application will not be further elaborated on this. It can be understood that the epitaxial part in the island-shaped epitaxial structure 10 of the present application should not be simply understood as a traditional epitaxial layer (a functional layer mainly grown by physical or chemical vapor deposition), and it is also possible to further attach other functional layers to the traditional epitaxial layer on the basis of the traditional epitaxial layer by bonding, spin coating, etc.

[0051] For further information, see Figure 2 The island-shaped epitaxial structure 10 can be manufactured by the following steps S110-S130, specifically:

[0052] Step S110, providing an epitaxial layer; the epitaxial layer includes a substrate, a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer;

[0053] Step S120, depositing a current spreading layer on the second conductive type semiconductor layer;

[0054] Step S130, performing step etching and channel etching on the epitaxial layer including the current spreading layer to form the island epitaxial structure; wherein the first sub-electrode is formed on the surface of the current spreading layer and the first conductive semiconductor layer.

[0055] Specifically, you can refer to Figure 3-Figure 6. The epitaxial layer provided in the present application mainly includes a substrate 100, a first conductive semiconductor layer 200, an active layer 300 and a second conductive semiconductor layer 400. The first conductive semiconductor layer 200, the active layer 300 and the second conductive semiconductor layer 400 are sequentially stacked on the substrate 100. Among them, the substrate 100 can be a transparent substrate, and the material of the transparent substrate includes inorganic materials or III-V semiconductor materials. Inorganic materials include silicon carbide (SiC), germanium (Ge), sapphire (Sapphire), lithium aluminate (LiAlO2), zinc oxide (ZnO), glass or quartz. III-V semiconductor materials include indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), and aluminum nitride (AlN) materials. The substrate 100 should have sufficient strength to mechanically support the epitaxial layer and be able to transmit light emitted from the epitaxial layer. The thickness of the substrate 100 can be selected to be 50μm or more. In addition, in order to facilitate the subsequent possible bonding process, the substrate 100 needs to be mechanically processed (thinned), and the thickness of the selected substrate 100 is generally not more than 300 μm.

[0056] The main difference between the first conductive semiconductor layer 200 and the second conductive semiconductor layer 400 is the different concentration of carriers (holes, electrons). Specifically, the first conductive semiconductor layer 200 can have electrons as the majority carriers and holes as the minority carriers. In other words, the first conductive semiconductor layer 200 is mainly conductive by electrons; while the second conductive semiconductor layer 400 can have holes as the majority carriers and electrons as the minority carriers. In other words, the second conductive semiconductor layer 400 is mainly conductive by holes. Conversely, the first conductive semiconductor layer 200 can also have holes as the majority carriers and electrons as the minority carriers, that is, the first conductive semiconductor layer 200 is mainly conductive by holes; while the second conductive semiconductor layer 400 can also have electrons as the majority carriers and holes as the minority carriers, that is, the second conductive semiconductor layer 400 is mainly conductive by electrons. Further, the reason for the difference in carrier concentration between the first conductive semiconductor layer 200 and the second conductive semiconductor layer 400 is mainly due to the different doping types. For example, the first conductive semiconductor layer 200 conducts electricity through electrons and the second conductive semiconductor layer 400 conducts electricity through holes: to achieve this purpose, the first conductive semiconductor layer 200 can use nitrogen, phosphorus, arsenic and tellurium as the dopant of the five-group element, in addition, silicon and germanium are also confirmed as the dopant of the first conductive semiconductor layer 200; and the second conductive semiconductor layer 400 can use boron, aluminum, gallium, indium and other three-group elements as the dopant, in addition, magnesium and carbon are also confirmed as the dopant of the second conductive semiconductor layer 400. It can be understood that the specific doping process and doping concentration can be understood by referring to the existing process, which is not the focus of this application and will not be further described in this application.

[0057] The active layer 300 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW) structure.

[0058] Exemplarily, taking the first conductive semiconductor layer 200 as an N-type semiconductor layer and the second conductive semiconductor layer 400 as a P-type semiconductor layer as an example, the N-type semiconductor layer or the P-type semiconductor layer may be a III-V compound semiconductor material such as GaN, AlGaN, InGaN, AlInP, GaInP, AlGaInP, etc. The active layer 300 may be a multiple quantum well structure (Multiple Quantum Well, MQW). Specifically, the quantum wells or quantum layers of the multiple quantum well structure may be InGaN, AlGaN, InN, InAlN, AlInGaN, etc., and the quantum barriers alternately stacked with the quantum well layers may be GaN, AlN, AlGaN, AlInGaN, InAlN, etc.; the multiple quantum well structure may include one or two or three or four or five or six or six or seven or eight quantum wells (or at least one quantum hole); the wavelength emitted by the above active layer 300 may be a wavelength of a blue light band, a wavelength of a green light band, or a wavelength of a red light band, which is not specifically limited in the embodiments of the present application.

[0059] like Figure 4As shown, the current spreading layer 500 can be grown on the second conductive semiconductor layer 400 using techniques such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE). The current spreading layer 500 can include only conductive materials, or can include conductive materials and insulating materials at the same time. Among them, when including conductive materials and insulating materials at the same time, the conductive materials and insulating materials can be arranged at intervals or at intervals + stacked. The scheme of the interval + stacked arrangement can refer to the existing scheme of combining the current blocking layer and the current spreading layer. Further, the conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), zinc oxide (ZnO), indium zinc oxide (IZO), diamond-like carbon film (DLC) or gallium zinc oxide (GZO); the insulating material includes but is not limited to polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8, epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), glass (Glass), aluminum oxide (Al2O3), silicon oxide (SiO x ), titanium oxide (TiO x )、Tantalum oxide (Ta2O5), Silicon nitride (SiN x ) or spin-on glass (SOG). In this specific embodiment, the current spreading layer 500 can be selected from indium tin oxide, that is, ITO.

[0060] For further information, please refer to Figure 5 , step etching and channel etching are performed on the epitaxial layer including the current spreading layer 500 to form an island epitaxial structure 10. Step etching is also known as MESA etching, and channel etching is also known as ISO etching; MESA etching mainly performs patterning on the epitaxial layer portion through the photoresist layer PR1 to expose the first conductive type semiconductor layer 200 close to the substrate 100 side, and then the current spreading layer 500 can be further shaped and fused by the photoresist layer PR1 to obtain the following: Figure 6 The intermediate structure shown in FIG. Finally, on this basis, ISO etching is used to produce the following Figure 7 The island-shaped epitaxial structure 10 is shown.

[0061] Next, you can continue to refer to Figure 8 and Fig. 9 After obtaining the island-shaped epitaxial structure 10 that meets the requirements, a photoresist layer PR2 can be further deposited on the island-shaped epitaxial structure 10, and the photoresist layer PR2 is patterned (exposure, development, etching, etc.) to expose the surface of the current spreading layer 500 and part of the surface of the first conductive semiconductor layer 200, that is, to form a Figure 8 The first opening H1 shown in the figure may be circular in shape. In some other embodiments, the first opening H1 may be square, annular, or finger-shaped. In addition, the shape and number of the first opening H1 are not particularly limited. It may be provided with only one opening. If multiple openings are provided, the current can be dispersed more evenly. In addition, in some other embodiments, when multiple openings are provided, each opening may be distributed in an equidistant or unequally spaced manner according to actual needs, and is not limited to the embodiments disclosed in the present invention.

[0062] Then, continue to refer to Fig.10 , a first sub-electrode MT is evaporated on the surface of the exposed current spreading layer 500 and the surface of the first conductive semiconductor layer 200, and the first sub-electrode MT is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten. At the same time, the first sub-electrode MT may include a single-layer metal structure or a multi-layer metal stacking structure. Exemplarily, when the first sub-electrode MT is a single-layer metal structure, it may be only chromium, and its thickness should at least be able to ensure that it acts as a hard mask in the subsequent etching process. When the first sub-electrode MT is a multi-layer metal stacking structure, it may be any stacking combination of aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten, or alloys containing these materials are also included. When further considering the electrode's anti-push-pull performance and anti-tin stringing ability, copper can also be considered as part of the multi-layer metal stacking structure, for example, replacing the aluminum layer in the traditional multi-layer metal stacking structure with a copper-aluminum alloy.

[0063] See also Fig.11After the evaporation of the first sub-electrode MT is completed, the photoresist layer PR2 can be removed by a specific solution, and then a passivation layer 20 is deposited on the basis of the first sub-electrode MT. The passivation layer 20 covers the first sub-electrode MT. The passivation layer 20 can be manufactured by ALD (Atomic Layer Deposition) process. The passivation layer 20 mainly plays an insulating and protective role. The passivation layer 20 includes but is not limited to polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8, epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), glass (Glass), aluminum oxide (Al2O3), silicon oxide (SiOx), titanium oxide (TiO2), tantalum oxide (Ta2O5), silicon nitride (SiNx) or spin-on glass (SOG).

[0064] See also Fig.12 After the passivation layer 20 is made, the position of the passivation layer 20 corresponding to the first sub-electrode MT can be further patterned to form a second opening H2. The second opening H2 exposes the first sub-electrode MT. The shape of the second opening H2 can be the same as the shape of the first opening H1, which can be circular, square, annular, or finger-shaped. The present application does not further limit this. When the passivation layer 20 is patterned (mainly etched) in the conventional way, since the thickness of the current spreading layer 500 under the passivation layer 20 is usually very thin, in order to ensure that the passivation layer 20 is etched cleanly, the set over-etching amount will cause a part of the current spreading layer 500 to be etched away, making the already thin current spreading layer 500 even thinner, affecting the photoelectric performance of the device. In the face of this problem, the present application divides the electrode of the original device into two parts and forms them separately. On the one hand, it can protect the functional layer under the electrode from being affected by etching, and on the other hand, it can also reduce the probability of subsequent detection, repair, and even scrapping. It can be understood that in other embodiments, the functional layer under the first sub-electrode MT may be an ohmic contact layer, a current blocking layer, etc. in addition to the current spreading layer 500 mentioned above, and the present application does not make further limitations on this.

[0065] You can continue to read Fig.13, the second sub-electrode PD is formed by continuing to evaporate on the exposed surface of the first sub-electrode MT, and the second sub-electrode PD and the first sub-electrode MT constitute the electrode part of the LED device, that is, the LED realizes the input of current through the second sub-electrode PD and the first sub-electrode MT. Specifically, the second sub-electrode PD can be at least one selected from chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten. The second sub-electrode PD can also be a single-layer metal or a multi-layer metal stacking structure. Exemplarily, when the second sub-electrode PD is a single-layer metal structure, it can be only gold, that is, the surface metal of the LED electrode is gold. When the second sub-electrode PD is a multi-layer metal stacking structure, it can be any stacking combination of aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten, or alloys containing these materials are also included. When further considering the push-pull resistance and tin-proof string-down capability of the electrode, copper can also be considered as part of the multi-layer metal stacking structure, for example, replacing the aluminum layer in the traditional multi-layer metal stacking structure with a copper-aluminum alloy.

[0066] It can be understood that since the second sub-electrode PD and the first sub-electrode MT constitute the electrode part of the LED device, the specific selection of the second sub-electrode PD should be the same as the selection of the first sub-electrode MT, which should at least meet the selection rules of traditional LED electrodes. In terms of the selection of the number of layers, traditional LED electrodes are usually multi-layer structures. Therefore, based on this premise, the first sub-electrode MT of the present application can be a single-layer metal structure, and the second sub-electrode PD can be a multi-layer metal stacking structure; the first sub-electrode MT can be a multi-layer metal structure, and the second sub-electrode PD can be a single-layer metal stacking structure; the first sub-electrode MT and the second sub-electrode PD can also be multi-layer metal stacking structures at the same time. In terms of specific material selection, under the premise that the bottom metal of the LED electrode is chromium and the surface metal is gold, those skilled in the art can refer to the prior art and based on the aforementioned disclosure of electrode materials in this application to select and adjust the middle part of the LED electrode (between chromium and gold), and this application does not make further limitations on this.

[0067] Based on the same inventive concept, the present application also provides an LED, which is manufactured using the aforementioned LED manufacturing method.

[0068] The above-mentioned LED is manufactured by adopting the above-mentioned LED manufacturing method, and the above-mentioned LED manufacturing method is to evaporate a layer of first sub-electrode on the island-shaped epitaxial structure, and the electrode is usually made of metal or alloy material. Then, by virtue of the blocking effect of the first sub-electrode (equivalent to a hard mask), during the subsequent passivation layer patterning process, the lower semiconductor layer of the first sub-electrode can be protected from over-engraving and incomplete etching, thereby avoiding voltage increase caused by incomplete etching or over-engraving affecting the photoelectric performance of the product, thereby greatly improving the photoelectric performance and stability of the LED.

[0069] Specifically, the LED of the present application may be Mini LED or Micro LED, wherein Mini LED mainly refers to LEDs with a size between 50 microns and 200 microns, and Micro LED mainly refers to LEDs with a size less than 50 microns.

[0070] Furthermore, the LED electrode portion of the present application includes a first sub-electrode MT and a second sub-electrode PD, and the LED realizes current input through the second sub-electrode PD and the first sub-electrode MT. The first sub-electrode MT is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten. At the same time, the first sub-electrode MT may include a single-layer metal structure or a multi-layer metal stacking structure. Exemplarily, when the first sub-electrode MT is a single-layer metal structure, it may be only chromium, and its thickness should at least be able to ensure that it acts as a hard mask in the subsequent etching process. When the first sub-electrode MT is a multi-layer metal stacking structure, it may be any stacking combination of aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten, or alloys containing these materials are also included. When further considering the electrode's push-pull resistance and anti-tin stringing capability, copper can also be considered as part of the multi-layer metal stacking structure, for example, replacing the aluminum layer in the traditional multi-layer metal stacking structure with a copper-aluminum alloy.

[0071] Specifically, the second sub-electrode PD may be at least one selected from chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten. The second sub-electrode PD may also be a single-layer metal or a multi-layer metal stacking structure. Exemplarily, when the second sub-electrode PD is a single-layer metal structure, it may be only gold, that is, the surface metal of the LED electrode is gold. When the second sub-electrode PD is a multi-layer metal stacking structure, it may be any stacking combination of aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten, or alloys containing these materials are also included. When further considering the electrode's anti-push-pull performance and anti-tin stringing ability, copper can also be considered as part of the multi-layer metal stacking structure, for example, replacing the aluminum layer in the traditional multi-layer metal stacking structure with copper-aluminum alloy.

[0072] It can be understood that since the second sub-electrode PD and the first sub-electrode MT constitute the electrode part of the LED device, the specific selection of the second sub-electrode PD should be the same as the selection of the first sub-electrode MT, which should at least meet the selection rules of traditional LED electrodes. In terms of the selection of the number of layers, traditional LED electrodes are usually multi-layer structures. Therefore, based on this premise, the first sub-electrode MT of the present application can be a single-layer metal structure, and the second sub-electrode PD can be a multi-layer metal stacking structure; the first sub-electrode MT can also be a multi-layer metal structure, and the second sub-electrode PD can be a single-layer metal stacking structure; the first sub-electrode MT and the second sub-electrode PD can also be multi-layer metal stacking structures at the same time. In terms of specific material selection, under the premise that the bottom metal of the LED electrode is chromium and the surface metal is gold, those skilled in the art can refer to the prior art and based on the inventive concept of the present application to select and adjust the middle part of the LED electrode (between chromium and gold), and the present application does not make further limitations on this.

[0073] Furthermore, in addition to the aforementioned first sub-electrode MT, second sub-electrode PD and island-shaped epitaxial structure 10, the LED of the present application may further include other specific functional layers according to the specific light-emitting wavelength and device characteristics of the LED. For example, when the LED mainly emits wavelengths in the blue-green band, in addition to the substrate 100 mainly using gallium nitride semiconductor materials, the LED may further include an ohmic contact layer, a hole blocking layer, an electron blocking layer, a buffer layer, a stress release layer, etc. The above-mentioned ohmic contact layer, hole blocking layer, electron blocking layer, buffer layer, and stress release layer can be set with reference to the arrangement position of the existing blue-green LED, and this application will not further elaborate on this. When the LED mainly emits red light, in addition to the substrate 100 using gallium arsenide material, the LED may further include a bonding layer, a buffer layer, a stress release layer, etc. Among them, the bonding layer is mainly involved in the process of replacing the gallium arsenide substrate, and the specific reference can be made to the existing red light LED chip substrate replacement process, and this application will not further elaborate on this. It can be understood that the epitaxial part in the LED of the present application should not be simply understood as a traditional epitaxial layer (a functional layer mainly grown epitaxially by physical or chemical vapor deposition). It is also possible to further add other functional layers to the traditional epitaxial layer through bonding, spin coating, etc. on the basis of the traditional epitaxial layer.

[0074] Based on the same inventive concept, the present application also provides a display panel, which includes a driving circuit and a light-emitting device electrically connected to the driving circuit; wherein the light-emitting device adopts the LED described above.

[0075] The light-emitting device in the display panel adopts the aforementioned LED, and the LED manufactured by the aforementioned LED manufacturing method has greatly improved photoelectric performance and stability. Ultimately, the stability and photoelectric performance of the display panel including the LED are also greatly improved.

[0076] Specifically, the driving circuit of the present application may be an active matrix circuit (AM) or a passive matrix circuit (PM) according to different driving modes. The display panel may be a Mini LED display panel, a Micro LED display panel, etc., or a backlight module applied to a passive light-emitting display device, and the passive light-emitting display device may be a liquid crystal display device.

[0077] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for manufacturing an LED, characterized in that: include: Providing an island-shaped epitaxial structure; Depositing a photoresist layer on the island epitaxial structure, and patterning the photoresist layer so that a portion of the surface of the island epitaxial structure is exposed; Vapor depositing a first sub-electrode on the exposed surface of the island epitaxial structure; Depositing a passivation layer on the island epitaxial structure; wherein the passivation layer covers the first sub-electrode; performing patterning on the passivation layer so that the first sub-electrode is exposed; and A second sub-electrode is fabricated on the exposed first sub-electrode; wherein the first sub-electrode and the second sub-electrode constitute electrodes of the LED.

2. The LED manufacturing method according to claim 1, characterized in that: The first sub-electrode includes a single-layer metal structure or a multi-layer metal stacking structure.

3. The LED manufacturing method according to claim 1, characterized in that: The first sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

4. The LED manufacturing method according to claim 1, characterized in that: The second sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

5. The LED manufacturing method according to any one of claims 1 to 4, characterized in that: The method for manufacturing the island epitaxial structure comprises: Providing an epitaxial layer; the epitaxial layer includes a substrate, a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer; depositing a current spreading layer on the second conductive semiconductor layer; Step etching and channel etching are performed on the epitaxial layer including the current spreading layer to form the island epitaxial structure; wherein the first sub-electrode is formed on the surface of the current spreading layer and the first conductive type semiconductor layer.

6. An LED, characterized in that: The LED is manufactured by the LED manufacturing method according to any one of claims 1 to 5.

7. The LED according to claim 6, characterized in that The first sub-electrode includes a single-layer metal structure or a multi-layer metal stacking structure.

8. The LED according to claim 6, characterized in that The first sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

9. The LED according to claim 8, characterized in that The second sub-electrode is selected from at least one of chromium, aluminum, titanium, platinum, gold, nickel, beryllium, and tungsten.

10. A display panel, characterized in that: The display panel comprises a driving circuit and a light emitting device electrically connected to the driving circuit; wherein the light emitting device is an LED as claimed in any one of claims 6 to 9.

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