Light-emitting element

Abstract

The invention provides a light-emitting element which ensures good conduction between an electrode and a semiconductor and reduces light absorption of a semiconductor material. A light-emitting element includes a semiconductor structure (10) having a first region (10a) in which a p-side semiconductor layer and an active layer are disposed and a second region (10b) other than the first region, a first n-side semiconductor layer disposed in the first region and the second region, and a p-side electrode (30) disposed in the first n-side semiconductor layer and in the second n-side semiconductor layer in plan view. The second n-side semiconductor layer is disposed on a surface of the first n-side semiconductor layer on the opposite side from the p-side semiconductor layer side so as to overlap the first n-side semiconductor layer in at least a portion of the second region, the second n-side semiconductor layer has a smaller band gap energy than the first n-side semiconductor layer, and the first n-side semiconductor layer has an opening (hn) in which the first n-side semiconductor layer has a smaller band gap energy than the first n-side semiconductor layer. An n-side electrode is electrically connected to the second n-side semiconductor layer.

Description

Technical Field

[0001] The disclosed invention relates to a light emitting element. Background Art

[0002] As a red light-emitting element composed of AlGaInP semiconductor materials, for example, a light-emitting element having an n-side electrode and a p-side electrode disposed on one surface and a structure for extracting light from a surface opposite to the surface on which the electrodes are disposed is proposed in Patent Document 1. Specifically, Patent Document 1 proposes a light-emitting element having the following structure: in a light-emitting element having a transparent substrate bonded to the light extraction surface side, a transparent film having a lower refractive index than that of the transparent substrate is disposed on the surface of the light extraction surface side of the transparent substrate, and the surface of the transparent film is roughened. In this light-emitting element, since the surface of the transparent film is roughened, the light distribution angle and the luminous efficiency are increased regardless of the material of the transparent substrate, and since it is composed of a low refractive index material, a total reflection angle is generated, and the luminous efficiency is higher.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Literature : Japanese Patent Application Publication No. 2018-064006 Summary of the invention

[0006] Problems that the invention will solve

[0007] An object of the present disclosure is to provide a light emitting element that can reduce light absorption by a semiconductor material while ensuring good conduction between an electrode and a semiconductor.

[0008] Technical means to solve problems

[0009] The light emitting element of the present disclosure includes:

[0010] A semiconductor structure comprising an n-side semiconductor layer, an active layer, and a p-side semiconductor layer, wherein the n-side semiconductor layer comprises a first n-side semiconductor layer and a second n-side semiconductor layer, and in a thickness direction, the active layer is disposed between the n-side semiconductor layer and the p-side semiconductor layer;

[0011] an n-side electrode electrically connected to the n-side semiconductor layer;

[0012] a p-side electrode electrically connected to the p-side semiconductor layer;

[0013] The active layer emits red light with a peak wavelength in a range of 620 nm to 700 nm.

[0014] The semiconductor structure has a first region and a second region in a plan view.

[0015] The first region is a region where the p-side semiconductor layer and the active layer are arranged, and the second region is a region other than the first region.

[0016] The first n-side semiconductor layer is disposed in the first region and the second region.

[0017] The second n-side semiconductor layer is arranged on a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer so as to overlap with the first n-side semiconductor layer in at least a portion of the second region in a plan view.

[0018] the second n-side semiconductor layer has a band gap energy smaller than that of the first n-side semiconductor layer,

[0019] The first n-side semiconductor layer disposed in the second region has an opening that exposes the second n-side semiconductor layer.

[0020] The n-side electrode is electrically connected to the second n-side semiconductor layer in the opening.

[0021] Effects of the Invention

[0022] The light emitting element disclosed in the present invention can ensure good conduction between the electrode and the semiconductor while reducing light absorption by the semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A It is a plan view showing the light emitting element according to Embodiment 1 of the present disclosure.

[0024] Figure 1B is a diagram showing the light emitting element of Embodiment 1 of the present disclosure. Figure 1A Cross-sectional view of the IB-IB line.

[0025] Figure 1C is a diagram showing the light emitting element of Embodiment 1 of the present disclosure. Figure 1A A cross-sectional view of the IC-IC line.

[0026] Figure 2 It is a plan view showing a first region and a second region of a semiconductor structure constituting the light emitting element according to Embodiment 1 of the present disclosure.

[0027] Figure 3 It is a plan view showing a p-side electrode of the light emitting element according to Embodiment 1 of the present disclosure.

[0028] Figure 4 This is a plan view showing an opening of one insulating film constituting the light emitting element according to Embodiment 1 of the present disclosure.

[0029] Figure 5This is a plan view showing an opening of another insulating film constituting the light emitting element according to Embodiment 1 of the present disclosure.

[0030] Figure 6 It is a plan view showing a wiring layer constituting the light emitting element according to Embodiment 1 of the present disclosure.

[0031] Figure 7 It is a plan view showing an n-side pad electrode and a p-side pad electrode constituting the light emitting element according to Embodiment 1 of the present disclosure.

[0032] Figure 8 It is a top view showing a light emitting element according to Embodiment 2 of the present disclosure.

[0033] Fig. 9 This is a plan view showing a first region, a second region, and a p-side electrode of a light-emitting element according to Embodiment 2 of the present disclosure.

[0034] Fig.10 It is a plan view showing an opening portion of an insulating film constituting a light emitting element according to Embodiment 2 of the present disclosure.

[0035] Fig.11 It is a plan view showing a wiring layer, an n-side pad electrode, a p-side pad electrode, and an opening of an insulating film constituting the light emitting element according to Embodiment 2 of the present disclosure.

[0036] Fig.12 It is a cross-sectional view showing a light emitting element according to Embodiment 3 of the present disclosure.

[0037] FIG. 13( a ) is a cross-sectional view showing one step of a method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0038] FIG13(b) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0039] FIG13(c) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0040] FIG13(d) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0041] FIG13(e) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0042] FIG13(f) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0043] FIG13(g) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0044] FIG13(h) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0045] FIG13(i) is a cross-sectional view showing one step of a method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0046] FIG13(j) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0047] FIG13(k) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0048] FIG13( l ) is a cross-sectional view showing one step of a method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0049] FIG13(m) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0050] FIG13(n) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0051] FIG13(o) is a cross-sectional view showing one step of the method for manufacturing the light emitting element according to Embodiment 1 of the present disclosure.

[0052] Description of Reference Numerals

[0053] 1 Light-emitting element

[0054] 10Semiconductor structures

[0055] 10a First Area

[0056] 10b Second Area

[0057] 12n-side semiconductor layer

[0058] 12a First n-side semiconductor layer

[0059] 12b Second n-side semiconductor layer

[0060] 14p-side semiconductor layer

[0061] 16 Active layer

[0062] 20n side electrode

[0063] 30p side electrode

[0064] 40 Dielectric Multilayer Film

[0065] 45a, 45b Insulation film

[0066] hn, h1, h2, h3, h4 opening

[0067] 50n side pad electrode

[0068] 60p side pad electrode

[0069] 70 wiring layer

[0070] 80 Holding unit

[0071] 100 Growth substrate

[0072] 102 Base Layer

[0073] 110 resin

[0074] 120 support plate DETAILED DESCRIPTION

[0075] (Implementation method 1)

[0076] Figure 1A to Figure 7 An embodiment of the light-emitting element of the present disclosure is shown in a cross-sectional view or a top view, respectively. Figure 1A It is a top view of the light emitting element of this embodiment. Figure 1B is along Figure 1A Cross-sectional view of the IB-IB line. Figure 1C is along Figure 1A A cross-sectional view of the IC-IC line. Figure 2 In the figure, only the first region and the second region described later are shown to clarify their positional relationship when viewed from above. As shown in these figures, the light emitting element 1 of the present embodiment has: a semiconductor structure 10, an n-side electrode 20, and a p-side electrode 30. The semiconductor structure includes: an n-side semiconductor layer 12 having a first n-side semiconductor layer 12a and a second n-side semiconductor layer 12b, a p-side semiconductor layer 14, and an active layer 16 located between the n-side semiconductor layer 12 and the p-side semiconductor layer 14. In addition, the light emitting element 1 includes: a dielectric multilayer film 40, insulating films 45a, 45b, an n-side pad electrode 50, a p-side pad electrode 60, and a wiring layer 70. The wiring layer 70 is used to connect the n-side electrode 20 and the p-side electrode 30 to the n-side pad electrode 50 and the p-side pad electrode 60, respectively. The light emitting element 1 has a holding portion 80 that supports the semiconductor structure 10 on the surface opposite to the surface on which the n-side pad electrode 50 and the p-side pad electrode 60 are arranged. Light emitted from the active layer 16 of the light emitting element 1 is extracted mainly from the side where the holding portion 80 is arranged.

[0077] The semiconductor structure 10 has a first region 10a and a second region 10b in a plan view. The first region 10a is a region where a p-side semiconductor layer 14 and an active layer 16 are arranged. The region other than the first region 10a, i.e., the second region 10b, is a region in the semiconductor structure 10 where only an n-side semiconductor layer 12 is arranged. In the present embodiment, the second region 10b has a peripheral portion 10b1 arranged at the outer edge of the light-emitting element 1 and a central portion 10b2 arranged approximately in the center of the light-emitting element 1 in a plan view. The light-emitting element 1 of the present embodiment has the following structure: in the n-side semiconductor layer 12, the first n-side semiconductor layer 12a is arranged in the first region 10a and the second region 10b, and at least a portion of the second n-side semiconductor layer 12b is arranged in the second region 10b. Figure 1A As shown, in this embodiment, the second n-side semiconductor layer 12b is arranged in the central portion 10b2 of the second region 10b. In addition, when viewed from the first n-side semiconductor layer 12a, the second n-side semiconductor layer 12b is arranged on the side opposite to the p-side semiconductor layer 14, that is, on the side close to the support substrate 80b described later.

[0078] The first n-side semiconductor layer 12a has an opening hn in the central portion 10b2 of the second region 10b, and the second n-side semiconductor layer 12b is exposed at the opening hn. Here, component x is exposed from component y, or component y exposes component x, which means that a part of component x is covered by component y, and another part of component x is not covered by component y, and it is allowed that the part not covered by component y is also covered by another component. In this embodiment, the n-side electrode 20 is electrically connected to the second n-side semiconductor layer 12b at the opening hn, and the n-side electrode 20 is also electrically connected to the n-side pad electrode 50 via the wiring layer 70.

[0079] In the present embodiment, the active layer 16 emits red light with a peak wavelength in the range of 620 nm to 700 nm. The semiconductor material constituting the semiconductor structure capable of emitting such red light has a tendency to absorb more light from the active layer 16 as the band gap energy is smaller. On the other hand, from the perspective of reducing the contact resistance between the semiconductor material and the metal, that is, reducing the forward voltage Vf of the light-emitting element, it is sometimes disadvantageous to constitute the n-side semiconductor layer 12 only with a semiconductor material having a higher band gap energy. Therefore, in the present embodiment, the second n-side semiconductor layer 12b is used as a semiconductor layer having a band gap energy smaller than that of the first n-side semiconductor layer 12a, and the entire second n-side semiconductor layer 12b is arranged in the second region 10b that does not overlap with the active layer 16 in a plan view. In addition, the n-side electrode 20 is arranged in contact with the second n-side semiconductor layer 12b, and the n-side electrode 20 is electrically connected to the second n-side semiconductor layer 12b. According to this structure, the semiconductor material can reduce the interference of the light from the active layer. Although the semiconductor material easily absorbs red light, it is advantageous in terms of the contact resistance with the n-side electrode 20. As a result, the absorption of red light can be reduced without increasing the forward voltage Vf of the light-emitting element 1, thereby improving the luminous efficiency of the light-emitting element 1. That is, in the light-emitting element 1, it is possible to ensure good electrical conduction between the n-side electrode 20 and the semiconductor material while reducing the absorption of light by the semiconductor material. In addition, in this embodiment, the central portion 10b2 of the second region 10b where the second n-side semiconductor layer 12b is arranged is surrounded by the first region 10a in a plan view. Through this configuration, the deviation of the current density distribution in the light-emitting element 1 can be reduced.

[0080] In this embodiment, in a plan view, not all of the second n-side semiconductor layer 12b may be in the second region 10b, but a portion of the second n-side semiconductor layer 12b may be disposed in the first region 10a. In addition, in a plan view, a plurality of second regions 10b may be disposed in a shape surrounded by the first region 10a. For example, the second region 10b may have a plurality of Figure 1A The second region 10b shown is a substantially rectangular region. Alternatively, the second region 10b may include a plurality of central portions 10b2 in a plan view and regions radially extending from the central portion 10b2.

[0081] In a plan view, the outer edge of the second n-side semiconductor layer 12b is preferably in a shape corresponding to the outer edge of the second region 10b, and the entire outer edge of the second n-side semiconductor layer 12b is arranged in the second region 10b. By making the shape of the second n-side semiconductor layer 12b correspond to the shape of the second region 10b, and taking into account the current density distribution and the position of the light-emitting region, etc., it is easier to arrange the first region 10a and the second region 10b.

[0082] Hereinafter, this embodiment will be described in detail.

[0083] 1. Semiconductor structures

[0084] The semiconductor structure 10 includes an n-side semiconductor layer 12 including a first n-side semiconductor layer 12a and a second n-side semiconductor layer 12b, a p-side semiconductor layer 14, and an active layer 16 disposed between the n-side semiconductor layer 12 and the p-side semiconductor layer 14. Figure 1B , Figure 1C , the semiconductor structure 10 is shown with the p-side semiconductor layer 14 as the lower side and the light extraction surface (the surface on the holding portion 80 side) as the upper side. In the present embodiment, the semiconductor structure 10 is rectangular in plan view, but may be other shapes, such as square, circle, trapezoid, triangle, polygon with five or more sides, etc. In addition, when the shape of the semiconductor structure 10 in plan view is a polygon with multiple corners, the corners of the polygon may be rounded.

[0085] The semiconductor material constituting the semiconductor structure 10 is selected so that the active layer 16 emits red light with a peak wavelength in the range of 620 nm to 700 nm. In this embodiment, as the semiconductor material constituting the p-side semiconductor layer 14, the active layer 16, and the first n-side semiconductor layer 12a, a material including, for example, an AlGaInP-based material can be used. The AlGaInP-based material is, for example, (Al x Ga 1－x ) y In 1－y P, (0≦x≦1, 0≦y≦1). The peak wavelength of red light is adjusted by changing the ratio of Al to Ga in the semiconductor material constituting the active layer 16. In the present embodiment, for example, a material satisfying 0.1≦x≦0.5 and 0.1≦y≦0.5 in the above formula can be used as a material constituting the active layer 16 (as one of the layers when the active layer 16 has a multilayer structure).

[0086] The p-side semiconductor layer 14 may be composed of a plurality of layers. Figure 1B , Figure 1COn the lower side, the p-side semiconductor layer 14 may have: a p-side contact layer, a p-side cladding layer and a p-side intermediate layer. The p-side contact layer is used to ensure electrical connection with the p-side electrode 30 and to expand the current. For example, GaP-based semiconductor materials (a type of AlGaInP-based material, a material that does not contain Al and In) can be used in the p-side contact layer. The thickness of the p-side contact layer can be greater than 0.1μm and less than 1μm. The cladding layer is used to promote the recombination of electrons and holes in the active layer 16. For example, AlInP-based semiconductor materials can be used in the cladding layer. The thickness of the p-side cladding layer can be greater than 0.1μm and less than 1μm. The p-side intermediate layer is used to reduce the diffusion of impurities in the p-side semiconductor layer 14 into the active layer. For example, AlGaInP-based semiconductor materials can be used in the p-side intermediate layer. The thickness of the p-side intermediate layer can be greater than 0.1μm and less than 0.5μm.

[0087] The active layer 16 may have a multi-quantum well structure, and the multi-quantum well structure has a plurality of well layers and a plurality of barrier layers. In this case, a GaInP-type material may be used in the well layer, and an AlGaInP-type material may be used in the barrier layer. The thickness of one well layer may be greater than 1 nm and less than 10 nm. The thickness of one barrier layer may be greater than 10 nm and less than 50 nm. The well layer and the barrier layer may be alternately and repeatedly configured so that the number of well layers is less than 5 and less than 20. The overall thickness of the active layer 16 may be, for example, greater than 5 μm and less than 10 μm.

[0088] The first n-side semiconductor layer 12a of the n-side semiconductor layer 12 may be composed of a plurality of layers. In this case, the material of each layer is selected according to the function to be implemented. Figure 1B , Figure 1C On the lower side, the n-layer may have, in order: an n-side intermediate layer, an n-side cladding layer, and a current diffusion layer. The n-side intermediate layer is used to reduce the movement of impurities in the n-side semiconductor layer 12 to the active layer 16. For example, AlGaInP semiconductor materials can be used in the n-side intermediate layer. The thickness of the n-side intermediate layer can be greater than 0.1 μm and less than 0.5 μm. The n-side cladding layer is used to promote the recombination of electrons and holes in the active layer 16, just like the above-mentioned p-side cladding. For example, AlInP semiconductor materials can be used in the n-side cladding. The thickness of the n-side cladding can be greater than 0.1 μm and less than 1 μm. The current diffusion layer is used to diffuse current. For example, AlGaInP semiconductor materials can be used in the current diffusion layer. The thickness of the current diffusion layer can be greater than 1 μm and less than 3 μm.

[0089] The thickness of the first n-side semiconductor layer 12a in the second region 10b may be, for example, 1 μm or more and 2 μm or less. By setting the thickness of the first n-side semiconductor layer 12a to 1 μm or more, it is possible to reduce damage in the semiconductor structure 10. By setting the thickness of the first n-side semiconductor layer 12a to 2 μm or less, it is possible to reduce light absorption by the first n-side semiconductor layer 12a.

[0090] The second n-side semiconductor layer 12b contains a semiconductor material with a smaller band gap energy than the first n-side semiconductor layer 12a. For example, when the first n-side semiconductor layer 12a is a layer containing an AlGaInP-based material, the second n-side semiconductor layer 12b can be configured to contain an AlGaAs-based material. z Ga 1－z As (0≦z≦1) is represented by the formula. In the present embodiment, GaAs (in the formula, Z=1) is preferably used from the viewpoint of reducing the contact resistance.

[0091] The band gap energy of AlGaInP-based materials is about 1.91 eV to 2.23 eV, and the band gap energy of AlGaAs-based materials is about 1.42 eV to 2.16 eV. For example, the band gap energy of GaAs is about 1.4 eV. Since the contact resistance between AlGaAs-based materials and metals is generally lower than the contact resistance between AlGaInP-based materials and metals, when the first n-side semiconductor layer 12a is composed of AlGaInP-based materials, the p-side semiconductor layer 14 preferably uses AlGaAs-based materials.

[0092] The thickness of the second n-side semiconductor layer 12b can be, for example, not less than 0.05 μm and not more than 0.5 μm. By setting the thickness of the second n-side semiconductor layer 12b to not less than 0.05 μm, the sheet resistance of the second n-side semiconductor layer 12b can be reduced. By setting the thickness of the second n-side semiconductor layer 12b to not more than 0.5 μm, the absorption of light by the second n-side semiconductor layer 12b can be reduced.

[0093] In a plan view, the area of ​​the second n-side semiconductor layer 12b may be, for example, not less than 3% and not more than 10% of the area of ​​the light emitting element 1. By setting it within such a range, it is possible to ensure electrical connection between the second n-side semiconductor layer 12b and the n-side electrode 20 while reducing light absorption by the second n-side semiconductor layer 12b.

[0094] The semiconductor structure 10 has a region where the p-side semiconductor layer 14 and the active layer 16 are arranged. The region where the p-side semiconductor layer 14 and the active layer 16 are not arranged in the first n-side semiconductor layer 12a is a region where the first n-side semiconductor layer 12a is exposed from the p-side semiconductor layer 14 and the active layer 16. In the present embodiment, in a plan view, the region where the p-side semiconductor layer 14 and the active layer 16 are arranged in the semiconductor structure 10 is referred to as the first region 10a, and the region other than the first region 10a is referred to as the second region 10b. Figure 2 As shown, the second region 10b surrounds the first region 10a in a plan view. The second region 10b has a peripheral portion 10b1 located near the outer edge of the light emitting element 1 and a central portion 10b2 located substantially in the center of the light emitting element 1 .

[0095] The first region 10a is the region where light emission mainly occurs in the light emitting element 1, and the first region 10a is preferably as large as possible to ensure the amount of light emission. On the other hand, the central portion 10b2 of the second region 10b where the second n-side semiconductor layer 12b is arranged is the portion where the n-side electrode 20 is electrically connected to the n-side semiconductor layer 12. Figure 1A As shown, in the substantially rectangular light emitting element 1 in a plan view, the first region 10a may be configured to occupy, for example, 70% or more of the area of ​​the light emitting element 1, and the second region 10b may be configured to occupy, for example, 10% or more and 30% or less of the area of ​​the light emitting element 1. In addition, in a plan view, the area of ​​the second n-side semiconductor layer 12b may be configured to occupy, for example, 10% or more and 20% or less of the area of ​​the second region 10b.

[0096] When the light emitting element 1 is in a rectangular shape with a short side of 100 μm to 2000 μm and a long side of 100 μm to 2000 μm, a substantially rectangular central portion 10b2 with a short side of 1 μm to 10 μm and a long side of 50 μm to 1500 μm and a peripheral portion 10b1 with a width of 1 μm to 15 μm from the outer edge of the light emitting element 1 may be used as the second region 10b. In this case, the second n-side semiconductor layer 12b may be in a rectangular shape with a short side of 1 μm to 10 μm and a long side of 50 μm to 1500 μm.

[0097] like Figure 1B , Figure 1C As shown, the first n-side semiconductor layer 12a has an opening hn located in the central portion 10b2 of the second region 10b. In the opening hn, the second n-side semiconductor layer 12b is exposed from the first n-side semiconductor layer 12a. The opening hn may have a shape and an area that exposes 60% or more and 90% or less of the surface of the second n-side semiconductor layer 12b in a plan view, for example.

[0098] like Figure 1B , Figure 1C As shown, in the surface of the first n-side semiconductor layer 12a on the side opposite to the p-side semiconductor layer 14, the surface where the first n-side semiconductor layer 12a and the second n-side semiconductor layer 12b do not overlap in a plan view is a rough surface. This is to reduce the total reflection of light from the active layer 16, thereby improving the light extraction efficiency. The Ra (arithmetic mean roughness) of the first n-side semiconductor layer 12a as a rough surface can be, for example, above 0.05 μm. The rough surface of the first n-side semiconductor layer 12a can be, for example, a surface composed of convex or concave portions with irregular shapes and configurations, or a surface composed of convex or concave portions with regular shapes and configurations. Alternatively, the rough surface can also be a surface where both convex or concave portions with irregular shapes and configurations and convex or concave portions with regular shapes and configurations exist.

[0099] 2. N-side electrode

[0100] The n-side electrode 20 is arranged in the opening hn, contacts the second n-side semiconductor layer 12b exposed from the first n-side semiconductor layer 12a, and is electrically connected to the n-side semiconductor layer 12. As described later, the n-side electrode 20 is electrically connected to the wiring layer 70, and is electrically connected to the n-side pad electrode 50 via the wiring layer 70.

[0101] The n-side electrode 20 is located in the opening hn of the first n-side semiconductor layer 12a and in the opening h1 of the insulating film 45a described later. Figure 1B , Figure 1C The n-side electrode 20 overlaps with the second n-side semiconductor layer 12b in a plan view.

[0102] The n-side electrode 20 may be composed of a material containing at least one metal selected from Au, Ag, Al, Ni, Pd, Ge, Si, and Sn, for example, or may be composed of an alloy containing one or more of these metals as components. The n-side electrode 20 may have a stacked structure. More specifically, the n-side electrode 20 may have a stacked structure in which AuGe, Ni, Ti, Pt, and Ti are stacked in sequence from the second n-side semiconductor layer 12b side. The thickness of the n-side electrode 20 may be, for example, not less than 100 nm and not more than 500 nm.

[0103] 3. P-side electrode

[0104] exist Figure 1B , Figure 1C In the embodiment, the p-side electrode 30 is located at the bottom surface of the p-side semiconductor layer 14. Figure 3As shown, a plurality of p-side electrodes 30 are arranged on the semiconductor structure 10. The shape of the p-side electrode 30 in a plan view is, for example, circular. The p-side electrodes 30 are regularly arranged in a plan view so that the distances between the p-side electrodes 30 are the same. According to such a configuration, it is possible to reduce the deviation of the current density distribution of the light-emitting element 1 while reducing the absorption of light by the p-side electrode 30. In the case where the shape of the p-side electrode 30 in a plan view is circular, for example, the p-side electrode 30 having a diameter of 3 μm or more and 20 μm or less can be arranged at intervals of 30 μm or more and 100 μm or less (the distance between the centers of adjacent p-side electrodes 30). Alternatively, the p-side electrodes 30 may be arranged irregularly.

[0105] In another embodiment, the p-side semiconductor layer 14 may be Figure 1B , Figure 1C The entire lowermost surface is provided with the p-side electrode 30. In this case, the current can be diffused to a wider range via the p-side electrode 30, and the variation of the current density distribution can be further reduced.

[0106] The p-side electrode 30 can be composed of a material containing at least one metal selected from Au, Ag, Al, Ni, Pd, Ge, Si, In, and Sn, for example, or an alloy containing one or more of these metals as components. In the p-side electrode 30, a material containing In, Sn, and O and having conductivity can be used. The material containing In, Sn, and O can be so-called ITO. Since the electrode using the material containing In, Sn, and O has high light transmittance relative to the peak wavelength of light from the active layer 16, it can be suitably used for the p-side electrode 30. The p-side electrode 30 can have a stacked structure. The thickness of the p-side electrode 30 can be, for example, greater than 10 nm and less than 100 nm.

[0107] 4. Dielectric multilayer films and insulating films

[0108] The light emitting element 1 of the present embodiment has a structure in which an n-side pad electrode 50 and a p-side pad electrode 60 are arranged on the same surface side of the semiconductor structure 10. In the present embodiment, in order to arrange the n-side pad electrode 50 and the p-side pad electrode 60 in a desired position and shape regardless of the positions of the n-side electrode 20 and the p-side electrode 30, a dielectric multilayer film 40, insulating films 45a and 45b, and a wiring layer 70 described later are used to ensure electrical insulation between the n-side electrode 20 and the p-side electrode 30 and electrical connection between these electrodes and the n-side pad electrode 50 and the p-side pad electrode 60.

[0109] A dielectric multilayer film 40 and insulating films 45a and 45b are arranged on the semiconductor structure 10. The dielectric multilayer film 40 is a DBR (Distributed Bragg Reflector) film in which high-refractive-index dielectrics and low-refractive-index dielectrics are alternately stacked. The dielectric multilayer film 40 is, for example, a film in which a combination of a high-refractive-index dielectric and a low-refractive-index dielectric is a Nb2O5 layer and a SiO2 layer, a TiO2 layer and a SiO2 layer, and the combination is more than 10 groups and less than 30 groups, and is repeatedly stacked. In a combination of a high-refractive-index dielectric and a low-refractive-index dielectric, the thickness of each dielectric can be more than 100nm and less than 200nm. Except for the area where the n-side electrode 20 and the p-side electrode 30 are electrically connected to the wiring layer 70, in a top view, the dielectric multilayer film 40 covers the semiconductor structure 10. Figure 1B , Figure 1C It should be noted that a structure in which an insulating film is arranged instead of the dielectric multilayer film 40 may be provided instead of the dielectric multilayer film 40 .

[0110] The insulating film 45a is disposed on the dielectric multilayer film 40. Figure 1B , Figure 1C The insulating film 45a has an opening h1 that overlaps with the opening hn of the first n-side semiconductor layer 12a in a plan view, and an opening h2 that overlaps with the p-side electrode 30 disposed on the p-side semiconductor layer 14. The n-side electrode 20 is disposed in the opening h1, and the p-side electrode 30 is electrically connected to the wiring layer 70 in the opening h2. Figure 2 , Figure 4 As shown in FIG. 1 , the opening h1 is arranged to overlap with the central portion 10b2 of the second region 10b in a plan view. Figure 1A As shown, the opening h2 is arranged in a circular shape similar to the p-side electrode 30 at a position corresponding to the p-side electrode 30 .

[0111] The insulating film 45b electrically insulates the n-side wiring portion 70a connected to the n-side electrode 20 and the p-side wiring portion 70b connected to the p-side electrode 30 in the wiring layer 70. Figure 1A , Figure 1B , Figure 5 As shown, the insulating film 45b has an opening h3 and an opening h4, and the n-side pad electrode 50 is electrically connected to the wiring layer 70 at the opening h3, and the p-side pad electrode 60 is electrically connected to the wiring layer 70 at the opening h4. In the portion other than the opening h3 and the opening h4, the insulating film 45b is located between the n-side pad electrode 50 and the p-side pad electrode 60 and the wiring layer 70, and the n-side pad electrode 50 is electrically insulated from the p-side pad electrode 60. In a plan view, the area of ​​the opening h3 is, for example, 5000 μm 2Above and 10000μm 2 In a plan view, the area of ​​the opening h4 is, for example, 1000 μm 2 Above and 5000μm 2 the following.

[0112] The insulating films 45a and 45b can be made of a material selected from SiO2, SiN, SiON, etc. Since the SiO2 film used has high light transmittance with respect to the peak wavelength of the light emitted from the active layer 16, it is preferably used for the insulating films 45a and 45b. The thickness of the insulating films 45a and 45b can be 0.1 μm or more and 1 μm or less. Different materials can be used for the insulating films 45a and 45b, or the same material can be used.

[0113] 5. Wiring layer

[0114] The wiring layer 70 has the function of electrically connecting the n-side electrode 20 and the n-side pad electrode 50, and electrically connecting the p-side electrode 30 and the p-side pad electrode 60. Figure 1B , 1C as well as Figure 6 As shown, the wiring layer 70 includes an n-side wiring portion 70 a electrically connected to the n-side electrode 20 and a p-side wiring portion 70 b electrically connected to the p-side electrode 30 in a plan view.

[0115] The wiring layer 70 may be made of a material containing at least one metal selected from Au, Cu, and Al, for example, and may be made of an alloy containing one or more of these metals as components. Figure 1A , Figure 6 As shown, since the wiring layer 70 is arranged in a relatively wide area of ​​the semiconductor structure 10 in a plan view, it is preferable to use a material having a high reflectivity, especially with respect to the light emitted from the active layer 16, in the wiring layer 70. For example, Au is preferably used in the wiring layer 70. The thickness of the wiring layer 70 can be greater than 100 nm and less than 500 nm.

[0116] The positions of the dielectric multilayer film 40, the insulating films 45a, 45b, and the wiring layer 70 are not limited to the positions shown in the figure. As long as the connection between the n-side electrode 20 and the p-side electrode 30 and the n-side pad electrode 50 and the p-side pad electrode 60 is ensured, three or more insulating films may be arranged in the thickness direction, and a plurality of wiring layers 70 may be arranged in the thickness direction. In addition, the position and shape of the openings of the insulating films 45a, 45b are not particularly limited.

[0117] 6. Pad electrode

[0118] The n-side pad electrode 50 and the p-side pad electrode 60 are electrically connected to the external power supply. The n-side pad electrode 50 is electrically connected to the n-side wiring portion 70a at the opening h3 of the insulating film 45b, and the p-side pad electrode 60 is electrically connected to the p-side wiring portion 70b at the opening h4 of the insulating film 45b.

[0119] like Figure 1A , Figure 7 As shown, the n-side pad electrode 50 and the p-side pad electrode 60 have substantially the same rectangular shape in a plan view, and are arranged substantially symmetrically on the left and right of the light emitting element 1 in the drawing. In a plan view, the area of ​​the n-side pad electrode 50 and the area of ​​the p-side pad electrode 60 are, for example, respectively not less than 20% and not more than 40% of the area of ​​the light emitting element 1 in a plan view.

[0120] The n-side pad electrode 50 and the p-side pad electrode 60 may be made of a material containing at least one metal selected from Au, Ag, Pt, Ti, Ni, Ge, Rh, and Ru, for example, and may be made of an alloy, particularly a eutectic, containing one or more of these metals as components. Examples of eutectics used for the n-side pad electrode 50 and the p-side pad electrode 60 are Au-Sn eutectic and Ag-Sn eutectic. The thickness of the n-side pad electrode 50 and the p-side pad electrode 60 may be 100 nm or more and 500 nm or less, respectively.

[0121] 7. Maintaining part

[0122] The holding portion 80 can protect the semiconductor structure 10 and improve the mechanical strength of the light emitting element 1. After the semiconductor structure 10 is grown on the growth substrate, the holding portion 80 is removed and arranged on the surface of the n-side semiconductor layer 12 side of the light emitting element 1, that is, arranged in a manner of replacing the growth substrate. When light is extracted from the side of the n-side semiconductor layer 12, the amount of light extracted can be increased by arranging the holding portion 80 having high light transmittance with respect to the peak wavelength of light from the active layer 16.

[0123] In this embodiment, the holding portion 80 includes a bonding member 80a and a support substrate 80b. The bonding member 80a is, for example, SiO 2. The thickness of the bonding member 80a may be 0.5 μm or more and 2 μm or less.

[0124] In this embodiment, a sapphire substrate, a glass substrate, or the like can be used as the support substrate 80b. The sapphire substrate is suitable for use as the support substrate 80b because it has high mechanical strength and high light transmittance to light from the active layer 16. The thickness of the support substrate 80b can be greater than or equal to 500 μm and less than or equal to 1000 μm.

[0125] The structure and material of the holding portion 80 are not limited to the structure and material described above, and for example, may be a single-layer structure consisting of a layer composed only of SiO 2. When the holding portion 80 is a single-layer structure consisting of a layer composed only of SiO 2, the thickness of the holding portion 80 may be greater than 0.5 μm and less than 2 μm.

[0126] (Implementation method 2)

[0127] Next, implementation mode 2 is described. In the following description and Figure 8 to Figure 11 In the description, components described using the same reference numerals as those in Embodiment 1 are the same components described in Embodiment 1, and the description related to Embodiment 1 is applicable except for portions different from Embodiment 1.

[0128] An example of the arrangement of the first region 10a, the second region 10b, and the second n-side semiconductor layer 12b is described as Embodiment 2. Figure 8 to Figure 11 In the light-emitting element of Embodiment 2, Figure 8 , Fig. 9 As shown, the first region 10a of the semiconductor structure 10 is a region including the center C of the light emitting element 1 in a plan view, and the second n-side semiconductor layer 12b does not overlap with the center C of the light emitting element 1 in a plan view. The shape of the second region 10b has a peripheral portion 10b1 and an extension portion 10b3, and the extension portion 10b3 is arranged continuously with the peripheral portion 10b1 and extends from the peripheral portion 10b1 toward the center C of the light emitting element. The second n-side semiconductor layer 12b (at Figure 8 , Fig. 9 The light emitting element of Embodiment 2 is arranged in the same manner as that of Embodiment 1, that is, the central portion 10b2 of the second region 10b arranged substantially in the center of the light emitting element 1 in Embodiment 1 and the second n-side semiconductor layer 12b are arranged in the extending portion 10b3 in a plan view. Figure 8 , Fig. 9 The semiconductor structure 10 on the lower side is biased toward the long side. With the related structure, in a plan view, the first region 10a containing the active layer 16 is arranged in the central region of the light-emitting element, so that light is easily emitted from the central region of the light-emitting element. In a plan view, the area of ​​the second n-side semiconductor layer 12b can be greater than 50% and less than 70% of the area of ​​the extension portion 10b3. By setting it to this range, it is possible to ensure that the second n-side semiconductor layer 12b is electrically connected to the n-side electrode 20 while reducing the absorption of light by the second n-side semiconductor layer 12b.

[0129] The shape and size of the extension portion 10b3 in plan view may be the same as those of the central portion 10b2 of the second region 10b in the first embodiment. The shape and size of the peripheral portion 10b1 in plan view may be the same as those of the peripheral portion 10b1 of the second region 10b in the first embodiment.

[0130] In the second embodiment, the second region 10b and the second n-side semiconductor layer 12b are arranged on one side of the semiconductor structure 10 which is closer to one long side in a plan view, and as Figure 8 to Figure 10 As shown, the second embodiment is different from the first embodiment in the shapes and / or arrangements of the p-side electrode 30 , the opening hn , the n-side electrode 20 , the openings h1 , h2 , and h3 , and the wiring layer 70 .

[0131] like Fig. 9 As shown in FIG. 1 , in Embodiment 2, the shape of the p-side electrode 30 in a plan view is circular as in Embodiment 1. The p-side electrode 30 is arranged near the center C where the second region 10b does not exist, and as shown in FIG. Fig. 9 As shown in FIG. 1 , the n-side wiring portion 70 a is not arranged in the area surrounded by the dotted line. As described later, this is to arrange the n-side wiring portion 70 a in this portion when the n-side pad electrode 50 is arranged.

[0132] like Fig.10 As shown, the insulating film 45a is arranged on the dielectric multilayer film 40 (not shown) so as to cover the entire light emitting element except for the opening h1 and the opening h2 electrically connected to the wiring layer 70 and the n-side electrode 20 and the p-side electrode 30. In this embodiment, the opening h1 is arranged in a circular shape corresponding to the shape and arrangement of the p-side electrode 30, as in the first embodiment, and the opening h2 is arranged so as to overlap with the opening hn (not shown) arranged in the first n-side semiconductor layer 12a, as in the first embodiment.

[0133] like Fig. 9 , Fig.11 As shown in FIG. 1 , the n-side wiring portion 70a covers almost the entire extension portion 10b3 of the second region 10b in a plan view, and has an extension portion 70a1 extending toward one side of the first region 10a. As described later, the extension portion 70 is used for electrical connection with the n-side pad electrode 50. The p-side wiring portion 70b is connected to the n-side pad electrode 50 disposed in the first region 10a. Fig. 9 The p-side electrodes 30 shown are arranged so that their regions overlap.

[0134] The insulating film 45b has an opening h3 for electrically connecting the extending portion 70a1 of the n-side wiring portion 70a to the n-side pad electrode 50, and an opening h4 for electrically connecting the p-side electrode 30 to the p-side pad electrode 60. Fig.11In FIG. 1 , the shapes and arrangements of the openings h3 and h4 are indicated by dotted lines, and the n-side pad electrode 50 and the p-side pad electrode 60 are indicated by dot-dash lines.

[0135] The reason why the opening h3 is configured to overlap the extension portion 70a1 of the wiring layer 70 is to make the n-side pad electrode 50 have the same shape and configuration as in Embodiment 1 while the second n-side semiconductor layer 12b is biased to one side as shown in the figure. In Embodiment 2, if the opening h4 is to be configured to overlap the second n-side semiconductor layer 12b as in Embodiment 1, the n-side pad electrode 50 also needs to be biased to one side, or its size needs to be increased to overlap the second n-side semiconductor layer 12b.

[0136] In a plan view, the area of ​​the opening h4 of Embodiment 2 is larger than that of the opening h4 of Embodiment 1. The opening h4 is located closer to the center area of ​​the light-emitting element than the light-emitting element 1 of Embodiment 1. This is because in this embodiment, the second region 10b is not located in the central area of ​​the light-emitting element, and the p-side electrode 30 is also arranged in the central area of ​​the light-emitting element. By increasing the area of ​​the opening h4 in a plan view, the electrical connection between the wiring layer 70 and the p-side pad electrode 60 can be made more reliable, and thus the electrical connection between the p-side electrode 30 and the p-side pad electrode 60 can be made more reliable. For example, in a plan view, the area of ​​the opening h4 can be greater than 60% and less than 90% of the area of ​​the p-side pad electrode 60.

[0137] According to the present embodiment, as described above, the approximate center of the light-emitting element 1 can be used as the light-emitting region in a plan view. From the viewpoint of reducing the deviation of the current density distribution, in the present embodiment, the second region 10b where the second n-side semiconductor layer 12b is arranged can be arranged along two opposite sides of the semiconductor structure 10 in a plan view, or can be arranged along four sides of the semiconductor structure 10. Alternatively, in a plan view, it can be arranged at two corners located on the diagonal line of the semiconductor structure 10. Alternatively, Embodiment 1 is combined with Embodiment 2, and the second region 10b where the second n-side semiconductor layer 12b is located can be arranged in the approximate center of the conductor structure 10 and in a region close to the outer edge of the semiconductor structure 10. In this case, in a plan view, the area of ​​the second region 10b located in the approximate center of the semiconductor structure 10 can be smaller than the area of ​​the second region 10b arranged in a region close to the outer edge of the semiconductor structure 10.

[0138] (Implementation method 3)

[0139] In other embodiments, in order to reduce damage to the n-side semiconductor layer 12, the second n-side semiconductor layer 12b may be configured so that a portion of the first region 10a overlaps with the first region 10a in a plan view. Fig.12 The light emitting element of Embodiment 3 is mainly different from the light emitting element of Embodiment 1 in the arrangement of the second n-side semiconductor layer 12 b .

[0140] exist Fig.12 In the light emitting element 1 of the third embodiment shown, the second n-side semiconductor layer 12b is not only arranged in the entire second region 10b, but also arranged across the first region 10a. Since the second n-side semiconductor layer 12b is continuously arranged in the first region 10a and the second region 10b, the top view area of ​​the second n-side semiconductor layer 12b is increased, so that it is not easy to be damaged. From the point of view of reducing the absorption of light by the second n-side semiconductor layer 12b, the top view area of ​​the portion of the second n-side semiconductor layer 12b arranged in the first region 10a is preferably 20% or less of the top view area of ​​the entire second n-side semiconductor layer 12b.

[0141] In addition, the thickness of the portion of the second n-side semiconductor layer 12b arranged in the first region 10a is preferably smaller than the thickness of the portion arranged in the second region 10b. By reducing the thickness of the second n-side semiconductor layer 12b, the absorption of light can be reduced. The thickness of the portion of the second n-side semiconductor layer 12b arranged in the first region 10a can be, for example, 10% or more and 50% or less of the thickness of the portion of the second n-side semiconductor layer 12b arranged in the second region 10b. A step can be formed between the portion of the second n-side semiconductor layer 12b arranged in the first region 10a and the portion of the second n-side semiconductor layer 12b arranged in the second region 10b. Alternatively, the thickness of the second n-side semiconductor layer 12b can decrease from the boundary between the second region 10b and the first region 10a toward the first region 10a, in which case the second n-side semiconductor layer 12b has a trapezoidal cross-sectional shape as shown in the figure.

[0142] In addition, regarding the thickness of the second n-side semiconductor layer 12b, as long as at least a portion of the portion located in the first region 10a is smaller than the thickness of the portion located in the second region 10b, the other portion may be the same thickness as the portion located in the second region 10b. For example, in the illustrated embodiment, the position where the thickness of the second n-side semiconductor layer 12b starts to decrease is not strictly at the boundary between the first region 10a and the second region 10b, but may be a position offset to the first region 10a side or the second region 10b side.

[0143] (Implementation method 4)

[0144] As Embodiment 4, a method for manufacturing the light-emitting element of Embodiment 1 will be described with reference to FIGS. 13( a ) to ( o ).

[0145] As shown in FIG. 13 (a), a foundation layer 102 and a semiconductor structure 10 are formed on a growth substrate 100 composed of GaAs. The semiconductor structure 10 has: a second n-side semiconductor layer 12b, a first n-side semiconductor layer 12a, an active layer 16, and a p-side semiconductor layer 14. The foundation layer 102 is formed of, for example, a GaInP layer, and the second n-side semiconductor layer 12b is formed of a GaAs layer. The first n-side semiconductor layer 12a is formed to have: a current diffusion layer, an n-side cladding layer, and an n-side intermediate layer in order from the foundation layer 102 side. The current diffusion layer is formed of an AlGaInP layer, the n-side cladding layer is formed of an AlInP layer, and the n-side intermediate layer is formed of an AlGaInP layer. The active layer 16 is formed as an MQW layer having GaInP layers as barrier layers and GaInP layers as well layers alternately formed. The p-side semiconductor layer 14 is formed to have: a p-side intermediate layer, a p-side cladding layer, and a p-side contact layer in order from the active layer 16 side. The p-side intermediate layer is formed of an AlGaInP layer, the p-side cladding layer is formed of an AlInP layer, and the p-side contact layer is formed of a GaP layer. The layers constituting the semiconductor structure 10 of FIG. 13( a ) may be formed by conventional methods, such as MOCVD or MOVPE.

[0146] 13( b ), the p-side electrode 30 is formed on the p-side semiconductor layer 14 . The p-side electrode 30 is formed by, for example, forming an ITO layer on the p-side semiconductor layer 14 and removing a portion of the ITO layer by, for example, wet etching.

[0147] Next, as shown in FIG. 13C , the p-side semiconductor layer 14 , the active layer 16 , and a portion of the first n-side semiconductor layer 12 a are removed by reactive ion etching or the like, thereby forming a first region 10 a having the p-side semiconductor layer 14 and the active layer 16 , and a second region 10 b not having the p-side semiconductor layer 14 and the active layer 16 in the semiconductor structure 10 .

[0148] Next, as shown in FIG. 13( d ), a dielectric multilayer film 40 is formed. The dielectric multilayer film 40 is formed by selecting the material and thickness of each film and by a sputtering method or a CVD method, etc., so that it functions as a DBR film. After the dielectric multilayer film 40 is formed in a manner covering the semiconductor structure 10, a portion of the dielectric multilayer film 40 is removed by wet etching, dry etching, etc., so that the region of the first n-side semiconductor layer 12 a where the n-side electrode 20 is arranged and a portion of the p-side electrode 30 are exposed from the dielectric multilayer film 40. Thus, a dielectric multilayer film 40 having an opening h1 and an opening h2 where the n-side electrode 20 and the p-side electrode 30 are electrically connected to the wiring layer 70 is formed.

[0149] Next, as shown in FIG. 13( e ), an insulating film 45 a having openings h1 and h2 is formed on the dielectric multilayer film 40. The insulating film 45 a having the openings h1 and h2 is formed by removing a portion of the insulating film 45 a by wet etching or the like after the insulating film 45 a is formed to cover the dielectric multilayer film 40. The insulating film 45 a is formed by a sputtering method or a CVD method.

[0150] FIG13(f) shows a step of forming the n-side electrode 20. After a portion of the first n-side semiconductor layer 12a is removed by reactive ion etching or the like in the opening h1 to form the opening hn, the second n-side semiconductor layer 12b is exposed, and then the n-side electrode 20 is formed on the second n-side semiconductor layer 12b in the opening h1, and a portion of the n-side electrode 20 is formed to extend on the insulating film 45a. The n-side electrode 20 is formed, for example, by sputtering, vapor deposition, or the like.

[0151] FIG13(g) shows a step of forming a wiring layer 70 on the insulating film 45a. The wiring layer 70 is formed to be electrically connected to the n-side electrode 20 and the p-side electrode 30. The wiring layer 70 is formed in the opening h2 so as to be electrically connected to the p-side electrode 30 in the opening h2. The wiring layer 70 is formed so that the n-side wiring portion 70a and the p-side wiring portion 70b are electrically isolated from each other in a plan view. The wiring layer 70 is formed by a sputtering method, a vapor deposition method, or the like.

[0152] FIG13(h) shows a step of forming an insulating film 45b. The insulating film 45b is formed on the wiring layer 70. In a plan view, the insulating film 45b is formed so as to be in contact with the dielectric multilayer film 40 exposed from the wiring layer 70 between the n-side wiring portion 70a and the p-side wiring portion 70b. In addition, the insulating film 45b is partially removed by wet etching or the like so as to form a film having openings h3 and h4 that expose a portion of the wiring layer 70. The insulating film 45b is formed by a sputtering method or a CVD method.

[0153] FIG. 13( i ) shows a process of forming the n-side pad electrode 50 and the p-side pad electrode 60 . The n-side pad electrode 50 is formed so as to be electrically connected to the n-side wiring portion 70 a exposed from the insulating film 45 b. The p-side pad electrode 60 is formed so as to be electrically connected to the p-side wiring portion 70 b. The n-side pad electrode 50 and the p-side pad electrode 60 may be formed together as long as they each have the required shape and size. The n-side pad electrode 50 and the p-side pad electrode 60 are formed, for example, by sputtering, evaporation, or the like.

[0154] FIG. 13( j) shows a step of bonding a support plate 120 supporting the semiconductor structure 10 to the n-side pad electrode 50 and the p-side pad electrode 60 in a step of removing the growth substrate 100 described later. The bonding of the support plate can be performed by disposing a resin 110 having a viscous state on the side where the n-side pad electrode 50 and the p-side pad electrode 60 of the semiconductor structure 10 are formed, disposing the support plate 120 on the resin 110, and curing the resin 110. In this case, the resin 110 functions as an adhesive material. The resin 110 may be, for example, a polyimide-based resin or an epoxy-based resin, and the support plate 120 may be, for example, a sapphire substrate.

[0155] FIG13(k) shows a process of removing the growth substrate 100 to expose the second n-side semiconductor layer 12b. Specifically, the second n-side semiconductor layer 12b is exposed by removing the growth substrate 100 and the base layer 102 shown in FIG13(j). In the case where the growth substrate 100 is a GaAs substrate, the growth substrate 100 can be removed by etching using an ammonia-hydrogen peroxide mixture (a mixture of ammonia water, hydrogen peroxide water, and pure water). In this case, the base layer 102 becomes an etching stop layer, and the remaining base layer 102 is removed using hydrochloric acid. Alternatively, the base layer 102 can be removed using hydrochloric acid to remove the growth substrate 100.

[0156] FIG13(l) shows a process of removing the second n-side semiconductor layer 12b so that at least a portion of the second n-side semiconductor layer 12b remains in the central portion 10b2 of the second region 10b. For example, a mask is formed on the second n-side semiconductor layer 12b overlapping the central portion 10b2, and the second n-side semiconductor layer 12b exposed from the mask is removed, so that the second n-side semiconductor layer 12b remains in the central portion 10b2. In the case of the second n-side semiconductor layer 12b composed of a GaAs layer, the second n-side semiconductor layer 12b can be removed using hydrochloric acid.

[0157] FIG13(m) shows a process of roughening the surface of the first n-side semiconductor layer 12a on the side opposite to the p-side semiconductor layer 14. The roughening of the first n-side semiconductor layer 12a can be performed by wet etching using a mask. For example, a mask is formed on the second n-side semiconductor layer 12b, and the first n-side semiconductor layer 12a exposed from the mask is roughened by wet etching. It should be noted that the mask used in the process of leaving the second n-side semiconductor layer 12b can also be used in the roughening process.

[0158] FIG13(n) shows a process of forming the holding portion 80. For example, the bonding member 80a is formed by spin coating so as to cover the first n-side semiconductor layer 12a and the second n-side semiconductor layer 12b, and the bonding member 80a can be bonded to the support substrate 80b using the bonding member 80a as an adhesive. Alternatively, the holding portion 80 of the bonding member 80a can be formed by spin coating on one surface of the support substrate 80b and bonded to the n-side semiconductor layer 12. When SOG is used as the bonding member 80a, after bonding the support substrate 80b to the n-side semiconductor layer 12, the holding portion 80 is formed by heating and curing.

[0159] Fig. 13(o) shows a step of removing the support plate 120 bonded in the step shown in Fig. 13(j). The support plate 120 can be removed by dissolving the resin 110. Then, the light emitting element 1 can be manufactured by individualizing the light emitting elements.

[0160] The present invention includes the following aspects.

[0161] (Note 1)

[0162] A light emitting element, comprising:

[0163] A semiconductor structure comprising an n-side semiconductor layer, an active layer, and a p-side semiconductor layer, wherein the n-side semiconductor layer comprises a first n-side semiconductor layer and a second n-side semiconductor layer, and in a thickness direction, the active layer is disposed between the n-side semiconductor layer and the p-side semiconductor layer;

[0164] an n-side electrode electrically connected to the n-side semiconductor layer;

[0165] a p-side electrode electrically connected to the p-side semiconductor layer;

[0166] The active layer emits red light with a peak wavelength in the range of 620 nm to 700 nm.

[0167] The semiconductor structure has a first region and a second region in a plan view.

[0168] The first region is a region where the p-side semiconductor layer and the active layer are arranged, and the second region is a region other than the first region.

[0169] The first n-side semiconductor layer is disposed in the first region and the second region.

[0170] In a plan view, the second n-side semiconductor layer is arranged on a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer so as to overlap with the first n-side semiconductor layer in at least a portion of the second region.

[0171] the second n-side semiconductor layer has a band gap energy smaller than that of the first n-side semiconductor layer,

[0172] The first n-side semiconductor layer disposed in the second region has an opening portion exposing the second n-side semiconductor layer.

[0173] The n-side electrode is electrically connected to the second n-side semiconductor layer in the opening.

[0174] (Note 2)

[0175] In the light emitting element according to Supplementary Note 1, the second n-side semiconductor layer is not arranged in the first region in a plan view.

[0176] (Note 3)

[0177] In the light emitting element according to Supplementary Note 1 or 2, a portion of the second n-side semiconductor layer is arranged in the first region in a plan view.

[0178] (Note 4)

[0179] In the light emitting element according to any one of Supplementary Notes 1 to 3, in the second region, a thickness of the second n-side semiconductor layer is smaller than a thickness of the first n-side semiconductor layer.

[0180] (Note 5)

[0181] In the light emitting element according to any one of Supplementary Notes 1 to 4, the second region where the second n-side semiconductor layer is arranged is surrounded by the first region in a plan view.

[0182] (Note 6)

[0183] In the light emitting element according to any one of Supplementary Notes 1 to 5, the second n-side semiconductor layer is located in a central region of the light emitting element in a plan view.

[0184] (Note 7)

[0185] The light-emitting element according to any one of Appendixes 1 to 5, wherein the first region is a region including the center of the light-emitting element in a plan view,

[0186] The second n-side semiconductor layer does not overlap with the center of the light emitting element in a plan view.

[0187] (Note 8)

[0188] The light emitting element according to Supplementary Note 7, wherein the second region has a peripheral portion and an extension portion in a plan view, the extension portion is arranged continuously with the peripheral portion and extends from the peripheral portion toward the center of the light emitting element,

[0189] The second n-side semiconductor layer is arranged in the extending portion in a plan view.

[0190] (Note 9)

[0191] In the light emitting element according to Supplementary Note 8, in a plan view, an area of ​​the second n-side semiconductor layer is not less than 50% and not more than 70% of an area of ​​the extending portion.

[0192] (Note 10)

[0193] The light emitting element described in any one of appendices 1 to 9 is characterized in that, in a portion of the first n-side semiconductor layer that does not overlap with the second n-side semiconductor layer in a plan view, a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer is a rough surface.

[0194] (Note 11)

[0195] In the light emitting element according to any one of appendixes 1 to 10, in a plan view, an area of ​​the second n-side semiconductor layer is not less than 10% and not more than 20% of an area of ​​the second region.

[0196] (Note 12)

[0197] In the light emitting element according to any one of appendices 1 to 11, the first n-side semiconductor layer contains an AlGaInP-based material or contains a layer containing an AlGaInP-based material, and the second n-side semiconductor layer contains an AlGaAs-based material.

[0198] (Note 13)

[0199] In the light emitting element according to any one of appendixes 1 to 12, in a plan view, an area of ​​the second n-side semiconductor layer is not less than 3% and not more than 10% of an area of ​​the light emitting element.

[0200] Industrial Applicability

[0201] As a light-emitting element that effectively emits red light with a peak wavelength in the range of greater than 620nm and less than 700nm, the light-emitting element disclosed in the present invention is used, for example, as a light source for indicators or signalers, a light source for automobiles, a light source for LED displays, a backlight for liquid crystal displays, etc.

Claims

1. A light emitting element, characterized in that: include: A semiconductor structure comprising an n-side semiconductor layer, an active layer, and a p-side semiconductor layer, wherein the n-side semiconductor layer comprises a first n-side semiconductor layer and a second n-side semiconductor layer, and in a thickness direction, the active layer is disposed between the n-side semiconductor layer and the p-side semiconductor layer; an n-side electrode electrically connected to the n-side semiconductor layer; a p-side electrode electrically connected to the p-side semiconductor layer; The active layer emits red light with a peak wavelength in a range of 620 nm to 700 nm. The semiconductor structure has a first region and a second region in a plan view. The first region is a region where the p-side semiconductor layer and the active layer are arranged, and the second region is a region other than the first region. The first n-side semiconductor layer is disposed in the first region and the second region. In a plan view, the second n-side semiconductor layer is arranged on a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer so as to overlap with the first n-side semiconductor layer in at least a portion of the second region. the second n-side semiconductor layer has a band gap energy smaller than that of the first n-side semiconductor layer, The first n-side semiconductor layer disposed in the second region has an opening portion exposing the second n-side semiconductor layer. The n-side electrode is electrically connected to the second n-side semiconductor layer in the opening.

2. The light emitting element according to claim 1, characterized in that The second n-side semiconductor layer is not arranged in the first region in a plan view.

3. The light emitting element according to claim 1, wherein: In a plan view, a portion of the second n-side semiconductor layer is arranged in the first region.

4. The light emitting element according to any one of claims 1 to 3, characterized in that In the second region, a thickness of the second n-side semiconductor layer is smaller than a thickness of the first n-side semiconductor layer.

5. The light emitting element according to any one of claims 1 to 3, characterized in that: In a plan view, the second region where the second n-side semiconductor layer is arranged is surrounded by the first region.

6. The light emitting element according to any one of claims 1 to 3, characterized in that: The second n-side semiconductor layer is located in a central region of the light emitting element in a plan view.

7. The light emitting element according to any one of claims 1 to 3, characterized in that The first region is a region including the center of the light emitting element in a plan view. The second n-side semiconductor layer does not overlap with the center of the light emitting element in a plan view.

8. The light emitting element according to claim 7, characterized in that The second region has an outer peripheral portion and an extension portion in a plan view, the extension portion is arranged continuously with the outer peripheral portion and extends from the outer peripheral portion toward the center of the light emitting element. The second n-side semiconductor layer is arranged in the extending portion in a plan view.

9. The light emitting element according to claim 8, characterized in that In a plan view, an area of ​​the second n-side semiconductor layer is not less than 50% and not more than 70% of an area of ​​the extension portion.

10. The light emitting element according to any one of claims 1 to 3, characterized in that: In a portion of the first n-side semiconductor layer that does not overlap with the second n-side semiconductor layer in a plan view, a surface of the first n-side semiconductor layer opposite to the p-side semiconductor layer side is a rough surface.

11. The light emitting element according to any one of claims 1 to 3, characterized in that: In a plan view, an area of ​​the second n-side semiconductor layer is not less than 10% and not more than 20% of an area of ​​the second region.

12. The light emitting element according to any one of claims 1 to 3, characterized in that: The first n-side semiconductor layer contains an AlGaInP-based material or contains a layer containing an AlGaInP-based material, and the second n-side semiconductor layer contains an AlGaAs-based material.

13. The light emitting element according to any one of claims 1 to 3, characterized in that: In a plan view, an area of ​​the second n-side semiconductor layer is not less than 3% and not more than 10% of an area of ​​the light emitting element.

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