Display device

Abstract

A display device includes: a pixel circuit portion including a first oxide semiconductor layer; a first gate driver electrically connected to the pixel circuit portion, and including a second oxide semiconductor layer in the same layer as the first oxide semiconductor layer; and a first line portion electrically connected to the first gate driver, and defining at least one first dummy contact hole adjacent to the second oxide semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates generally to display devices. Background Art

[0002] The display device includes a display unit and a driver, and the driver generates a driving signal and provides the driving signal to the display unit. In order for the driver to generate the driving signal, the driver includes a transistor, and the semiconductor layer of the transistor can be a silicon semiconductor (amorphous silicon, polycrystalline silicon, etc.) or an oxide semiconductor.

[0003] Recently, in order to simplify the circuit structure of a driver and reduce power consumption, a driver having a CMOS (Complementary Metal Oxide Semiconductor) structure including a transistor formed of a silicon semiconductor and a transistor formed of an oxide semiconductor has been actively developed. Summary of the invention

[0004] An embodiment provides a display device.

[0005] According to one or more embodiments, a display device may include: a pixel circuit unit, including a first oxide semiconductor layer; a first gate driver, electrically connected to the pixel circuit unit, and the first gate driver includes a second oxide semiconductor layer in the same layer as the first oxide semiconductor layer; and a first line unit, electrically connected to the first gate driver, and the first line unit defines at least one first dummy contact hole adjacent to the second oxide semiconductor layer.

[0006] The first line portion may include at least one first clock line that overlaps the first dummy contact hole and is used to provide a clock signal to the first gate driver.

[0007] The display device may further include a second gate driver electrically connected to the pixel circuit portion, and the second gate driver includes a third oxide semiconductor layer in the same layer as the second oxide semiconductor layer.

[0008] The display device may further include a second line portion adjacent to the second gate driver, the second line portion being electrically connected to the second gate driver, and the second line portion defining at least one second dummy contact hole adjacent to the third oxide semiconductor layer.

[0009] The second line portion may include at least one second clock line overlapping the second dummy contact hole and used to provide a clock signal to the second gate driver.

[0010] The first gate driver may also include: at least one first inorganic insulating layer below the second oxide semiconductor layer; and at least one second inorganic insulating layer above the second oxide semiconductor layer, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the first line portion, and wherein the first dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the first line portion.

[0011] The pixel circuit portion further includes a first silicon semiconductor layer below the first oxide semiconductor layer, wherein the first gate driver further includes a second silicon semiconductor layer below the second oxide semiconductor layer, and wherein the first line portion includes an etch stopper at the same layer as the second silicon semiconductor layer.

[0012] The first dummy contact hole may expose the etch stopper.

[0013] The first line portion may further include at least one first clock line contacting the etch stopper through the first dummy contact hole and configured to provide a clock signal to the first gate driver.

[0014] The first gate driver may be divided into a plurality of first levels, wherein one or more contact holes penetrating the first inorganic insulating layer and the second inorganic insulating layer are defined in the plurality of first levels, and wherein the number of the first dummy contact holes per unit area of ​​the first line portion corresponds to the number of the contact holes per unit area of ​​each of the plurality of first levels.

[0015] The number of the first dummy contact holes per unit area of ​​the first line portion may be about 70% to about 130% of the number of the contact holes per unit area of ​​each of the plurality of first levels.

[0016] The display device may also include: a second gate driver divided into a plurality of second levels; and a second line portion electrically connected to the second gate driver, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the second gate driver and to the second line portion, wherein at least one second dummy contact hole is defined in the second line portion, and the at least one second dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping with the second line portion, and wherein the number of the second dummy contact holes per unit area of ​​the second line portion corresponds to the number of the contact holes per unit area of ​​each of the plurality of first levels.

[0017] The first line portion may include a straight line portion, and include a bent portion defining a third dummy contact hole.

[0018] The first gate driver may also include: at least one first inorganic insulating layer below the second oxide semiconductor layer; and at least one second inorganic insulating layer above the second oxide semiconductor layer, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the first line portion, and wherein the third dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the bent portion.

[0019] The first gate driver may be divided into a plurality of first levels, wherein at least one contact hole penetrating the first inorganic insulating layer and the second inorganic insulating layer is defined in the plurality of first levels, and wherein the number of the third dummy contact holes per unit area of ​​the bent portion corresponds to the number of the contact holes per unit area of ​​each of the plurality of first levels.

[0020] The pixel circuit portion may further include a first silicon semiconductor layer below the first oxide semiconductor layer, wherein the first gate driver further includes a second silicon semiconductor layer in the same layer as the first silicon semiconductor layer.

[0021] The display device may further include a second gate driver, which is electrically connected to the pixel circuit unit and includes a third oxide semiconductor layer that is on the same layer as the second oxide semiconductor layer, wherein the first gate driver is configured to provide a gate compensation signal to the pixel circuit unit, and wherein the second gate driver is configured to provide a gate bias signal to the pixel circuit unit.

[0022] The display device may further include a second gate driver, which is electrically connected to the pixel circuit unit and includes a third oxide semiconductor layer that is on the same layer as the second oxide semiconductor layer, wherein the first gate driver is configured to provide a gate compensation signal to the pixel circuit unit, and wherein the second gate driver is configured to provide an emission management signal to the pixel circuit unit.

[0023] According to one or more other embodiments, the display device may include: a first oxide semiconductor layer, overlapping with a display area; a second oxide semiconductor layer, which is in the same layer as the first oxide semiconductor layer, and the second oxide semiconductor layer overlaps with a circuit area adjacent to the display area; and at least one inorganic insulating layer, overlapping with the circuit area and a line area adjacent to the circuit area, and the at least one inorganic insulating layer defines at least one dummy contact hole, and wherein the dummy contact hole is adjacent to the second oxide semiconductor layer and is defined by the inorganic insulating layer.

[0024] The display device may further include at least one clock line overlapping the line area and overlapping the dummy contact hole.

[0025] The inorganic insulating layer may include: a first inorganic insulating layer below the second oxide semiconductor layer; and a second inorganic insulating layer above the second oxide semiconductor layer, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the line region, and wherein the dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the line region.

[0026] The display device may further include: a first silicon semiconductor layer overlapping the display area and being below the first oxide semiconductor layer; a second silicon semiconductor layer overlapping the circuit area and being below the second oxide semiconductor layer; and an etching stopper overlapping the line area and being on the same layer as the second silicon semiconductor layer.

[0027] The dummy contact hole may expose the etch stopper.

[0028] The display device may further include at least one clock line, the at least one clock line overlapping the line area, and the at least one clock line contacts the etch stopper through the dummy contact hole.

[0029] Therefore, the display device according to one or more embodiments of the present disclosure may include a gate driver and a line part. The gate driver may include a silicon semiconductor layer and an oxide semiconductor layer, and the line part may provide a clock signal to the gate driver.

[0030] A dummy contact hole may be formed in the line portion. Since the dummy contact hole is positioned adjacent to the oxide semiconductor layer, hydrogen contained in the inorganic insulating layer may diffuse through the dummy contact hole. Therefore, hydrogen does not diffuse into the oxide semiconductor layer, a negative shift in the threshold voltage of an N-channel metal oxide semiconductor (NMOS) transistor formed by the oxide semiconductor layer may be reduced or prevented, and the reliability of the NMOS transistor may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure together with the description.

[0032] Figure 1 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0033] Figure 2 It is shown that the Figure 1 A circuit diagram of a pixel circuit portion in a display device.

[0034] Figure 3 It is shown that the Figure 1 A circuit diagram of a first gate driver in a display device.

[0035] Figure 4 It is shown that the Figure 1 A circuit diagram of a second gate driver in a display device.

[0036] Figure 5 It is shown that the Figure 1 A circuit diagram of a third gate driver in a display device.

[0037] Figure 6 It is shown Figure 1 A plan view of a display device.

[0038] Figure 7 It is shown that the Figure 6 A cross-sectional view of a pixel structure in a display device.

[0039] Figure 8 It is shown that the Figure 6 A cross-sectional view of a first gate driver in a display device.

[0040] Fig. 9 It is shown that the Figure 6 A cross-sectional view of a second gate driver in a display device.

[0041] Fig.10 yes Figure 6 An enlarged view of the straight line portion A of FIG.

[0042] Fig.11 It is along Fig.10 A cross-sectional view taken along line II'.

[0043] Fig.12 It is along Fig.10 A cross-sectional view taken along line II-II'.

[0044] Fig.13It is along Fig.10 A cross-sectional view taken along line III-III'.

[0045] Fig.14 yes Figure 6 An enlarged view of the curved portion B.

[0046] Figures 15 to 20 It shows the manufacturing Figure 6 A cross-sectional view of a method for displaying a device.

[0047] Fig.21 is a plan view showing a display device according to one or more other embodiments of the present disclosure.

[0048] Fig. 22 yes Fig.21 An enlarged view of the straight line portion C of FIG. DETAILED DESCRIPTION

[0049] By referring to the detailed description of the embodiments and the accompanying drawings, it is easier to understand the aspects of some embodiments of the present disclosure and their implementation methods. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof indicate the same elements, and therefore, their repeated descriptions can be omitted.

[0050] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not (will not)" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure. In addition, the various features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0051] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0052] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are anticipated. Furthermore, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but rather include deviations in shapes due to, for example, manufacturing.

[0053] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0054] For ease of explanation, spatial relative terms such as "under ...", "below ...", "lower", "under ...", "under ...", "above ...", "upper", and "upper side" may be used herein to describe the relationship between an element or feature and another element (other elements) or another feature (other features) as shown in the figure. It will be understood that, in addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "under", "under" or "below" other elements or features will then be positioned as "above" the other elements or features. Therefore, the example terms "under ..." and "under ..." can cover both "above ..." and "below ..." orientations. The device can be positioned otherwise (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when a first component is described as being arranged "on" a second component, this means that the first component is arranged on the upper or lower side of the second component based on the direction of gravity, without being limited to its upper side.

[0055] In addition, the phrase "in a plan view" means observing an object portion from above, while the phrase "in a schematic cross-sectional view" means observing a schematic cross-section taken by vertically cutting an object portion from the side. The term "overlapping" or "overlapping with..." means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping" may include stacking, facing or facing, extending on..., covering or partially covering, or any other suitable term that a person of ordinary skill in the art will appreciate and understand. The expression "non-overlapping" may include meanings such as "separated from..." or "spaced apart from..." or "deviation from..." and any other suitable equivalent terms that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood as being indirectly opposite to each other although still facing each other.

[0056] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may be collectively referred to as direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, and / or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, and / or component, the layer, region, and / or component may be directly electrically connected or electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, and / or components. One or more intervening components may include switches, resistors, and / or capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, the statement of connection indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is on another component without intervening components.

[0057] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly" "below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "directly between..." or "adjacent to..." and "immediately adjacent to..." can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0058] For the purposes of this disclosure, when expressions such as "at least one of..." or "any one of..." or "one or more of..." precede a list of elements, the entire list of elements is modified rather than the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ as examples) or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more associated listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0059] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, part or part from another element, member, component, region, area, layer, part or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below can be referred to as the second element, component, region, layer or part. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish between elements of different categories or sets. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first set)", "second category (or second set)", etc.

[0060] In the example, the x-axis (first direction D1), the y-axis (second direction D2), and / or the z-axis (third direction D3) are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis (first direction D1), the y-axis (second direction D2), and the z-axis (third direction D3) can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0061] The terms used in this article are only used for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used in this article, unless the context clearly states otherwise, the singular "one" and "one (kind / person)" are also intended to include plural forms, and the plural form is also intended to include the singular form. It will be further understood that when used in this specification, the terms "including", "having" and "comprising" illustrate the existence of stated features, integral bodies, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups.

[0062] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order.

[0063] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to illustrate the inherent deviations of measured or calculated values ​​that would be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. As used herein, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "approximately" include the stated values ​​and mean within an acceptable range of deviations of the particular value determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0064] In some embodiments, known structures and devices may be described in the accompanying drawings for one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of various embodiments. Those skilled in the art will appreciate that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein (optionally, they can be driven by firmware and / or software). In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or by dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules can be physically divided into two or more interacting separate blocks, units and / or modules. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that unless explicitly defined as such in this article, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0066] Figure 1 is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0067] refer to Figure 1 , the display device 1000 according to one or more embodiments of the present disclosure may include a display part DP, a data driver DDV, a first gate driver GDV1 , a second gate driver GDV2 , a third gate driver GDV3 , and a controller CON.

[0068] A plurality of pixel circuit sections may be formed in the display section DP. For example, the pixel circuit section may include a first pixel circuit section PC1 and a second pixel circuit section PC2. Each of the first pixel circuit section PC1 and the second pixel circuit section PC2 may be electrically connected to a data driver DDV, a first gate driver GDV1, a second gate driver GDV2, and a third gate driver GDV3. Each of the first pixel circuit section PC1 and the second pixel circuit section PC2 may receive a data voltage DATA, a gate compensation signal GC, a gate bias signal GB, and an emission management signal EM.

[0069] The data driver DDV may generate the data voltage DATA according to the control of the controller CON.

[0070] The first gate driver GDV1 may generate a gate compensation signal GC according to the control of the controller CON. The gate compensation signal GC may include a gate-on voltage for turning on the transistor and a gate-off voltage for turning off the transistor.

[0071] The first gate driver GDV1 may include first stages STG1. The first stages STG1 may sequentially output gate compensation signals GC. In one or more embodiments, each of the first stages STG1 may output the gate compensation signal GC to the first and second pixel circuit parts PC1 and PC2.

[0072] The second gate driver GDV2 may generate a gate bias signal GB according to the control of the controller CON. The gate bias signal GB may include a gate-on voltage and a gate-off voltage.

[0073] The second gate driver GDV2 may include second stages STG2. The second stages STG2 may sequentially output gate bias signals GB. In one or more embodiments, each of the second stages STG2 may output gate bias signals GB to the first pixel circuit portion PC1 and the second pixel circuit portion PC2.

[0074] The third gate driver GDV3 may generate an emission management signal EM according to the control of the controller CON. The emission management signal EM may include a gate-on voltage and a gate-off voltage.

[0075] The third gate driver GDV3 may include third stages STG3. The third stages STG3 may sequentially output emission management signals EM. In one or more embodiments, each of the third stages STG3 may output emission management signals EM to the first pixel circuit portion PC1 and the second pixel circuit portion PC2.

[0076] Figure 2 It is shown that the Figure 1 A circuit diagram of a pixel circuit portion in a display device. Figure 3 It is shown that the Figure 1 A circuit diagram of a first gate driver in a display device. Figure 4 It is shown that the Figure 1 A circuit diagram of a second gate driver in a display device. Figure 5 It is shown that the Figure 1 A circuit diagram of a third gate driver in a display device.

[0077] refer to Figure 2 , the first pixel structure PX1 may include a first pixel circuit portion PC1 and a first light emitting diode OLED1. The first pixel circuit portion PC1 may generate a driving current corresponding to the data voltage DATA, and the first light emitting diode OLED1 may emit light having a brightness corresponding to the driving current. The second pixel structure may have substantially the same circuit structure as the first pixel structure PX1.

[0078] The first pixel circuit part PC1 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , and a storage capacitor CST.

[0079] The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive the driving voltage ELVDD. During the disable period of the gate write signal GW, the storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor T1.

[0080] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the first transistor T1 may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1 may be connected to the second transistor T2 and may receive the data voltage DATA. The second terminal of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may generate a driving current based on a voltage difference between the gate terminal and the first terminal. For example, the first transistor T1 may be referred to as a driving transistor.

[0081] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 may receive a gate write signal GW. The second transistor T2 may be turned on or off in response to the gate write signal GW. For example, if the second transistor T2 is a P-channel metal oxide semiconductor (PMOS) transistor, if the gate write signal GW has a positive voltage level, the second transistor T2 may be turned off, and if the gate write signal GW has a negative voltage level, the second transistor T2 may be turned on. The first terminal of the second transistor T2 may receive a data voltage DATA. During the period in which the second transistor T2 is turned on, the second terminal of the second transistor T2 may provide the data voltage DATA to the first terminal of the first transistor T1. For example, the second transistor T2 may be referred to as a switching transistor.

[0082] The third transistor T3 may include a gate terminal, a lower gate terminal, a first terminal, and a second terminal. The gate terminal and the lower gate terminal of the third transistor T3 may receive a gate compensation signal GC. The first terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 may be connected to the gate terminal of the first transistor T1. The third transistor T3 may be turned on or off in response to the gate compensation signal GC. For example, if the third transistor T3 is an NMOS transistor, the third transistor T3 may be turned on if the gate compensation signal GC has a positive voltage level, and the third transistor T3 may be turned off if the gate compensation signal GC has a negative voltage level. During the period in which the third transistor T3 is turned on in response to the gate compensation signal GC, the third transistor T3 may be connected to the first transistor T1 in a diode manner. Therefore, the third transistor T3 may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be referred to as a compensation transistor.

[0083] The fourth transistor T4 may include a gate terminal, a lower gate terminal, a first terminal, and a second terminal. The gate terminal and the lower gate terminal of the fourth transistor T4 may receive a gate initialization signal GI. The first terminal of the fourth transistor T4 may be connected to the gate terminal of the first transistor T1. The second terminal of the fourth transistor T4 may receive a gate initialization voltage VINT. The fourth transistor T4 may be turned on or off in response to the gate initialization signal GI. For example, if the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 may be turned on if the gate initialization signal GI has a positive voltage level, and the fourth transistor T4 may be turned off if the gate initialization signal GI has a negative voltage level. During the period in which the fourth transistor T4 is turned on by the gate initialization signal GI, the gate initialization voltage VINT may be provided to the gate terminal of the first transistor T1. Therefore, the fourth transistor T4 may initialize the gate terminal of the first transistor T1 to the gate initialization voltage VINT. For example, the fourth transistor T4 may be referred to as a gate initialization transistor.

[0084] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fifth transistor T5 may receive an emission management signal EM. The first terminal of the fifth transistor T5 may receive a driving voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first transistor T1. If the fifth transistor T5 is turned on in response to the emission management signal EM, the fifth transistor T5 may provide the driving voltage ELVDD to the first transistor T1.

[0085] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the sixth transistor T6 may receive an emission management signal EM. The first terminal of the sixth transistor T6 may be connected to the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the first light emitting diode OLED1. If the sixth transistor T6 is turned on in response to the emission management signal EM, the sixth transistor T6 may provide a driving current to the first light emitting diode OLED1.

[0086] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the seventh transistor T7 may receive a gate bias signal GB. The first terminal of the seventh transistor T7 may be connected to the first light emitting diode OLED1. The second terminal of the seventh transistor T7 may receive an anode initialization voltage AINT. If the seventh transistor T7 is turned on in response to the gate bias signal GB, the seventh transistor T7 may provide the anode initialization voltage AINT to the first light emitting diode OLED1. Therefore, the seventh transistor T7 may initialize the first terminal of the first light emitting diode OLED1 to the anode initialization voltage AINT. For example, the seventh transistor T7 may be referred to as an anode initialization transistor.

[0087] The eighth transistor T8 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the eighth transistor T8 may receive a gate bias signal GB. The first terminal of the eighth transistor T8 may be provided with a bias voltage VOBS. The second terminal of the eighth transistor T8 may be connected to the first terminal of the first transistor T1. If the eighth transistor T8 is turned on in response to the gate bias signal GB, the eighth transistor T8 may transmit the bias voltage VOBS to the first transistor T1. Similar to the data voltage of the black gray level, the bias voltage VOBS may be about 5V to about 6V. Therefore, in low-frequency driving, the degradation of the first transistor T1 may be reduced or prevented.

[0088] The first light emitting diode OLED1 may include a first terminal and a second terminal. The first terminal of the first light emitting diode OLED1 may be connected to the sixth transistor T6, and the second terminal may be supplied with a common voltage ELVSS. The first light emitting diode OLED1 may emit light having brightness corresponding to the driving current.

[0089] In one or more embodiments, the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be PMOS transistors, and the third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0090] refer to Figure 3 , the first gate driver GDV1 may include a first stage STG1. Each of the first stages STG1 may include a first compensation circuit capacitor CC1, a second compensation circuit capacitor CC2, and a first compensation circuit transistor CT1, a second compensation circuit transistor CT2, a third compensation circuit transistor CT3, a fourth compensation circuit transistor CT4, a fifth compensation circuit transistor CT5, a sixth compensation circuit transistor CT6, a seventh compensation circuit transistor CT7, an eighth compensation circuit transistor CT8, a ninth compensation circuit transistor CT9, a tenth compensation circuit transistor CT10, and an eleventh compensation circuit transistor CT11. The first gate driver GDV1 may receive a start signal FLM, clock signals CLK and CLKB, a gate high voltage VGH, gate low voltages VGL and VGL2, and a reset signal ESR, and may output a gate compensation signal GC.

[0091] In one or more embodiments, the first compensation circuit transistor CT1, the third compensation circuit transistor CT3, the fourth compensation circuit transistor CT4, the sixth compensation circuit transistor CT6, the eighth compensation circuit transistor CT8, the ninth compensation circuit transistor CT9 and the tenth compensation circuit transistor CT10 can be PMOS transistors, and the second compensation circuit transistor CT2, the fifth compensation circuit transistor CT5, the seventh compensation circuit transistor CT7 and the eleventh compensation circuit transistor CT11 can be NMOS transistors.

[0092] refer to Figure 4 , the second gate driver GDV2 may include a second stage STG2. Each of the second stages STG2 may include a first bias circuit capacitor BC1, a second bias circuit capacitor BC2, and a first bias circuit transistor BT1, a second bias circuit transistor BT2, a third bias circuit transistor BT3, a fourth bias circuit transistor BT4, a fifth bias circuit transistor BT5, a sixth bias circuit transistor BT6, an eighth bias circuit transistor BT8, a ninth bias circuit transistor BT9, a tenth bias circuit transistor BT10, and an eleventh bias circuit transistor BT11. The second gate driver GDV2 may receive a start signal FLM, clock signals CLK and CLKB, a gate high voltage VGH, gate low voltages VGL and VGL2, and a reset signal ESR, and may output a gate bias signal GB.

[0093] In one or more embodiments, the first bias circuit transistor BT1, the third bias circuit transistor BT3, the fourth bias circuit transistor BT4, the sixth bias circuit transistor BT6, the eighth bias circuit transistor BT8, the ninth bias circuit transistor BT9 and the tenth bias circuit transistor BT10 may be PMOS transistors, and the second bias circuit transistor BT2, the fifth bias circuit transistor BT5 and the eleventh bias circuit transistor BT11 may be NMOS transistors.

[0094] refer to Figure 5, the third gate driver GDV3 may include a third stage STG3. Each of the third stages STG3 may include a first light emitting circuit capacitor EC1, a second light emitting circuit capacitor EC2, and a first light emitting circuit transistor ET1, a second light emitting circuit transistor ET2, a third light emitting circuit transistor ET3, a fourth light emitting circuit transistor ET4, a fifth light emitting circuit transistor ET5, a sixth light emitting circuit transistor ET6, an eighth light emitting circuit transistor ET8, a ninth light emitting circuit transistor ET9, a tenth light emitting circuit transistor ET10, and an eleventh light emitting circuit transistor ET11. The third gate driver GDV3 may receive a start signal FLM, clock signals CLK and CLKB, a gate high voltage VGH, gate low voltages VGL and VGL2, and a reset signal ESR, and may output an emission management signal EM.

[0095] In one or more embodiments, the first light emitting circuit transistor ET1, the third light emitting circuit transistor ET3, the fourth light emitting circuit transistor ET4, the sixth light emitting circuit transistor ET6, the eighth light emitting circuit transistor ET8, the ninth light emitting circuit transistor ET9 and the tenth light emitting circuit transistor ET10 may be PMOS transistors, and the second light emitting circuit transistor ET2, the fifth light emitting circuit transistor ET5 and the eleventh light emitting circuit transistor ET11 may be NMOS transistors.

[0096] In one or more embodiments, the second gate driver GDV2 (see Figure 4 ) and the third gate driver GDV3 may have substantially the same circuit structure.

[0097] Figure 6 It is shown Figure 1 A plan view of a display device.

[0098] refer to Figure 6 , the display device 1000 may be divided into a display area DA and a non-display area, and the non-display area may include a first circuit area CA1, a second circuit area CA2, a third circuit area CA3, a first line area LA1, a second line area LA2, and a third line area LA3.

[0099] The display portion DP including the pixel structure PX may be located in the display area DA. The first circuit area CA1 may be adjacent to the display area DA, and the first gate driver GDV1 may be located in the first circuit area CA1. In one or more embodiments, as shown in FIG. Figure 6 As shown in , the first gate driver GDV1 may be adjacent to left and right sides of the display part DP, respectively.

[0100] The first line area LA1 may be adjacent to the first circuit area CA1, and the first line portion LP1 may be located in the first line area LA1. The first line portion LP1 may be electrically connected to the first gate driver GDV1.

[0101] The second circuit area CA2 may be adjacent to the first line area LA1 located on the right side in the first direction D1, and the second gate driver GDV2 may be located in the second circuit area CA2. Figure 6 As shown in , the second direction D2 may intersect the first direction D1, and the third direction D3 may be substantially perpendicular to a plane defined by the first direction D1 and the second direction D2.

[0102] The second line area LA2 may be adjacent to the second circuit area CA2 in the first direction D1, and the second line portion LP2 may be located in the second line area LA2. The second line portion LP2 may be electrically connected to the second gate driver GDV2.

[0103] The third circuit area CA3 may be adjacent to the first line area LA1 located on the left side in a direction opposite to the first direction D1, and the third gate driver GDV3 may be located in the third circuit area CA3.

[0104] The third line area LA3 may be adjacent to the third circuit area CA3 in a direction opposite to the first direction D1, and the third line portion LP3 may be located in the third line area LA3. The third line portion LP3 may be electrically connected to the third gate driver GDV3.

[0105] Figure 7 It is shown that the Figure 6 A cross-sectional view of a pixel structure in a display device. Figure 8 It is shown that the Figure 6 A cross-sectional view of a first gate driver in a display device. Fig. 9 It is shown that the Figure 6 A cross-sectional view of a second gate driver in a display device.

[0106] refer to Figure 7 , also refer to Figure 6 The pixel structure PX located in the display area DA may include a pixel circuit portion PC and a light emitting diode OLED. The light emitting diode OLED may be located on the pixel circuit portion PC.

[0107] The pixel circuit unit PC may include a substrate SUB, a first lower metal layer BML1, a buffer layer BFR, a first silicon semiconductor layer 1110, a first gate insulating layer GI1, a first gate electrode 1210, a second gate insulating layer GI2, a second gate electrode 1310, a third gate electrode 1320, a first interlayer insulating layer ILD1, a first oxide semiconductor layer 1410, a third gate insulating layer GI3, a fourth gate electrode 1510, a second interlayer insulating layer ILD2, a first connection electrode 1610, a second connection electrode 1620, a third connection electrode 1630, a fourth connection electrode 1640, a first via insulating layer VIA1, a fifth connection electrode 1710 and a second via insulating layer VIA2.

[0108] The first gate insulating layer GI1 , the second gate insulating layer GI2 , and the first interlayer insulating layer ILD1 may be defined as a first inorganic insulating layer IIL1 , and the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 may be defined as a second inorganic insulating layer IIL2 .

[0109] The light emitting diode OLED may include a pixel electrode ADE, a pixel defining layer PDL, an emission layer EL, and a common electrode CTE.

[0110] The substrate SUB may include an insulating material such as glass, quartz, or plastic. In addition, the substrate SUB may be composed of a single layer or a plurality of layers by combining single layers.

[0111] The first lower metal layer BML1 may be located on the substrate SUB (as used herein, "located on..." may also be referred to as "located above..."). In one or more embodiments, the first lower metal layer BML1 may overlap with the first silicon semiconductor layer 1110. The first lower metal layer BML1 may include a metal, an alloy, a conductive metal oxide, a metal nitride, a transparent conductive material, and the like. For example, the first lower metal layer BML1 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

[0112] The buffer layer BFR may be located on the substrate SUB. The buffer layer BFR may reduce or prevent metal atoms or impurities from diffusing from the substrate SUB into the first silicon semiconductor layer 1110. In addition, the buffer layer BFR may control a heat supply rate during a crystallization process for forming the first silicon semiconductor layer 1110.

[0113] The first silicon semiconductor layer 1110 may be located on the buffer layer BFR. In one or more embodiments, the first silicon semiconductor layer 1110 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first silicon semiconductor layer 1110 may include polycrystalline silicon formed by crystallizing amorphous silicon.

[0114] The first gate insulating layer GI1 may cover the first silicon semiconductor layer 1110 and may be located on the buffer layer BFR. The first gate insulating layer GI1 may include an inorganic insulating material. For example, the first gate insulating layer GI1 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0115] The first gate electrode 1210 may be located on the first gate insulating layer GI1 and may overlap the first silicon semiconductor layer 1110. The first gate electrode 1210 may include a metal, an alloy, a conductive metal oxide, a metal nitride, a transparent conductive material, etc. For example, the first gate electrode 1210 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0116] The second gate insulating layer GI2 may cover the first gate electrode 1210 and may be located on the first gate insulating layer GI1. The second gate insulating layer GI2 may include an inorganic insulating material.

[0117] The second gate electrode 1310 may be located on the second gate insulating layer GI2, and may overlap the first gate electrode 1210. The second gate electrode 1310 may include a metal, an alloy, a conductive metal oxide, a metal nitride, a transparent conductive material, or the like.

[0118] The third gate electrode 1320 may be located on the second gate insulating layer GI2 and may include metal, alloy, conductive metal oxide, metal nitride, a transparent conductive material, or the like.

[0119] The first interlayer insulating layer ILD1 may cover the second gate electrode 1310 and the third gate electrode 1320 and may be located on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may include an inorganic insulating material.

[0120] The first oxide semiconductor layer 1410 may be located on the first interlayer insulating layer ILD1 and may overlap with the third gate electrode 1320. The first oxide semiconductor layer 1410 may include an oxide semiconductor. The oxide semiconductor may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, examples of oxide semiconductors that may be used as the first oxide semiconductor layer 1410 may include IGZO (InGaZnO), ITZO (InSnZnO), and the like. These may be used alone or in combination with each other.

[0121] The third gate insulating layer GI3 may be located on the first oxide semiconductor layer 1410. The third gate insulating layer GI3 may include an inorganic insulating material.

[0122] The fourth gate electrode 1510 may be located on the third gate insulating layer GI3 and may overlap the first oxide semiconductor layer 1410. The fourth gate electrode 1510 may include a metal, an alloy, a conductive metal oxide, a metal nitride, a transparent conductive material, or the like.

[0123] The second interlayer insulating layer ILD2 may cover the fourth gate electrode 1510 and may be located on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may include an inorganic insulating material.

[0124] The first connection electrode 1610 and the second connection electrode 1620 may be located on the second interlayer insulating layer ILD2 and may overlap the first silicon semiconductor layer 1110. The third connection electrode 1630 and the fourth connection electrode 1640 may be located on the second interlayer insulating layer ILD2 and may overlap the first oxide semiconductor layer 1410. The first connection electrode 1610, the second connection electrode 1620, the third connection electrode 1630, and the fourth connection electrode 1640 may include a metal, an alloy, a conductive metal oxide, a metal nitride, a transparent conductive material, or the like.

[0125] The first silicon semiconductor layer 1110, the first gate electrode 1210, the first connection electrode 1610, and the second connection electrode 1620 may correspond to the reference Figure 2 Any of the PMOS transistors described.

[0126] The third gate electrode 1320, the first oxide semiconductor layer 1410, the fourth gate electrode 1510, the third connection electrode 1630, and the fourth connection electrode 1640 may correspond to the reference Figure 2 Any of the NMOS transistors described.

[0127] The first via insulating layer VIA1 may cover the first connection electrode 1610, the second connection electrode 1620, the third connection electrode 1630, and the fourth connection electrode 1640, and may be located on the second interlayer insulating layer ILD2. The first via insulating layer VIA1 may include an organic insulating material. For example, the first via insulating layer VIA1 may include a photoresist, a polyacrylic resin (e.g., an acrylic resin), a polyimide resin, etc.

[0128] The fifth connection electrode 1710 may be located on the first via insulating layer VIA1, and may contact the first connection electrode 1610. The fifth connection electrode 1710 may include metal, alloy, conductive metal oxide, metal nitride, a transparent conductive material, or the like.

[0129] The second via insulating layer VIA2 may cover the fifth connection electrode 1710 and may be located on the first via insulating layer VIA1. The second via insulating layer VIA2 may include an organic insulating material.

[0130] The pixel electrode ADE may be located on the second via insulating layer VIA2 and may contact the fifth connection electrode 1710. The pixel electrode ADE may include metal, alloy, conductive metal oxide, metal nitride, a transparent conductive material, or the like.

[0131] The pixel defining layer PDL may be located on the pixel electrode ADE and may expose the pixel electrode ADE. The pixel defining layer PDL may include an organic insulating material.

[0132] The emission layer EL may be located on the pixel electrode ADE, and may include an organic light emitting material.

[0133] The common electrode CTE may be located on the emission layer EL, and may include metal, alloy, conductive metal oxide, metal nitride, transparent conductive material, or the like.

[0134] refer to Figure 8 , also refer to Figure 6 and Figure 7 , the first gate driver GDV1 located in the first circuit area CA1 may include a second lower metal layer BML2, a second silicon semiconductor layer 1120, a fifth gate electrode 1220, a sixth gate electrode 1330, a second oxide semiconductor layer 1420, a seventh gate electrode 1520, and a sixth connection electrode 1650, a seventh connection electrode 1660, an eighth connection electrode 1670, and a ninth connection electrode 1680. The substrate SUB, the buffer layer BFR, the first inorganic insulating layer IIL1, the second inorganic insulating layer IIL2, the first via insulating layer VIA1, and the second via insulating layer VIA2 may extend from the display area DA to the second line area LA2 and to the third line area LA3.

[0135] The second lower metal layer BML2 may be located at the same layer as the first lower metal layer BML1 , and may include metal, alloy, conductive metal oxide, metal nitride, a transparent conductive material, or the like.

[0136] The second silicon semiconductor layer 1120 may be located at the same layer as the first silicon semiconductor layer 1110 , and may include a silicon semiconductor.

[0137] The fifth gate electrode 1220 may be located at the same layer as the first gate electrode 1210 , and may overlap the second silicon semiconductor layer 1120 .

[0138] The sixth gate electrode 1330 may be located at the same layer as the third gate electrode 1320 .

[0139] The second oxide semiconductor layer 1420 may be located at the same layer as the first oxide semiconductor layer 1410 , and may include an oxide semiconductor.

[0140] The seventh gate electrode 1520 may be located at the same layer as the fourth gate electrode 1510 , and may overlap the second oxide semiconductor layer 1420 .

[0141] The sixth connection electrode 1650 and the seventh connection electrode 1660 may be located on the second interlayer insulating layer ILD2. A contact hole CNT penetrating the first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2 may be formed in the first gate driver GDV1. The sixth connection electrode 1650 and the seventh connection electrode 1660 may contact the second silicon semiconductor layer 1120 through the contact hole CNT.

[0142] The eighth connection electrode 1670 and the ninth connection electrode 1680 may be located on the second interlayer insulating layer ILD2 and may contact the second oxide semiconductor layer 1420 .

[0143] The second silicon semiconductor layer 1120, the fifth gate electrode 1220, the sixth connection electrode 1650, and the seventh connection electrode 1660 may correspond to the reference Figure 3 Any of the PMOS transistors described.

[0144] The sixth gate electrode 1330, the second oxide semiconductor layer 1420, the seventh gate electrode 1520, the eighth connection electrode 1670, and the ninth connection electrode 1680 may correspond to the reference Figure 3 Any of the NMOS transistors described.

[0145] refer to Fig. 9 , also refer to Figures 6 to 8The second gate driver GDV2 located in the second circuit area CA2 may include a third lower metal layer BML3, a third silicon semiconductor layer 1130, an eighth gate electrode 1230, a ninth gate electrode 1340, a third oxide semiconductor layer 1430, a tenth gate electrode 1530, and a tenth connection electrode 1691, an eleventh connection electrode 1692, a twelfth connection electrode 1693 and a thirteenth connection electrode 1694.

[0146] The third lower metal layer BML3 may be located at the same layer as the first lower metal layer BML1 and the second lower metal layer BML2 , and may include metal, alloy, conductive metal oxide, metal nitride, a transparent conductive material, or the like.

[0147] The third silicon semiconductor layer 1130 may be located at the same layer as the first silicon semiconductor layer 1110 and the second silicon semiconductor layer 1120 , and may include a silicon semiconductor.

[0148] The eighth gate electrode 1230 may be located at the same layer as the first gate electrode 1210 and the fifth gate electrode 1220 , and may overlap the third silicon semiconductor layer 1130 .

[0149] The ninth gate electrode 1340 may be located at the same layer as the third gate electrode 1320 and the sixth gate electrode 1330 .

[0150] The third oxide semiconductor layer 1430 may be located at the same layer as the first oxide semiconductor layer 1410 and the second oxide semiconductor layer 1420 , and may include an oxide semiconductor.

[0151] The tenth gate electrode 1530 may be located at the same layer as the fourth gate electrode 1510 and the seventh gate electrode 1520 , and may overlap the third oxide semiconductor layer 1430 .

[0152] The tenth connection electrode 1691 and the eleventh connection electrode 1692 may be located on the second interlayer insulating layer ILD2 and may contact the third silicon semiconductor layer 1130 .

[0153] The twelfth and thirteenth connection electrodes 1693 and 1694 may be located on the second interlayer insulating layer ILD2 and may contact the third oxide semiconductor layer 1430 .

[0154] The third silicon semiconductor layer 1130, the eighth gate electrode 1230, the tenth connection electrode 1691, and the eleventh connection electrode 1692 may correspond to the reference Figure 4 Any of the PMOS transistors described.

[0155] The ninth gate electrode 1340, the third oxide semiconductor layer 1430, the tenth gate electrode 1530, the twelfth connection electrode 1693, and the thirteenth connection electrode 1694 may correspond to the reference Figure 4 Any of the NMOS transistors described.

[0156] In one or more embodiments, the third gate driver GDV3 may have substantially the same circuit structure as the second gate driver GDV2 , and may have a symmetrical planar structure with the second gate driver GDV2 .

[0157] Fig.10 yes Figure 6 An enlarged view of the straight line portion A of FIG. Fig.11 It is along Fig.10 A cross-sectional view taken along line II'. Fig.12 It is along Fig.10 A cross-sectional view taken along line II-II'. Fig.13 It is along Fig.10 A cross-sectional view taken along line III-III'.

[0158] refer to Fig.10 , the first gate driver GDV1 may include first stages STG1 arranged side by side in a second direction D2 intersecting the first direction D1. Figure 8 The described at least one contact hole CNT may be formed in each of the first stages STG1 .

[0159] The first line portion LP1 may include at least one first clock line CLK1, and the first clock line CLK1 may extend in the second direction D2. Fig.10 As shown in , the first line portion LP1 may include two first clock lines CLK1 .

[0160] The first clock line CLK1 may be connected to each of the first stages STG1 , and may provide a clock signal to each of the first stages STG1 .

[0161] The second gate driver GDV2 may include second stages STG2 arranged side by side in the second direction D2.

[0162] The second line portion LP2 may include a reset signal line ESRL, a gate low voltage line VGLL, and at least one second clock line CLK2. Fig.10 As shown in , the second line portion LP2 may include two second clock lines CLK2 .

[0163] The second clock line CLK2 may be connected to each of the second stages STG2 , and may provide a clock signal to each of the second stages STG2 .

[0164] At least one first dummy contact hole DCNT1 may be formed in the first line portion LP1. In one or more embodiments, the first dummy contact hole DCNT1 may overlap with the first clock line CLK1. For example, the first dummy contact hole DCNT1 may be formed at substantially uniform intervals while avoiding a connection region where each of the first stages STG1 is connected to the first line portion LP1 (e.g., as much as possible).

[0165] The number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may correspond to the number of contact holes CNT compared to the plane area of ​​each of the first-level STG1 (the number of ... compared to the plane area of ​​... may be understood as: the number of ... / the plane area of ​​...). That is, the number of the first dummy contact holes DCNT1 per unit area of ​​the first line portion LP1 may correspond to the number of contact holes CNT per unit area of ​​each of the first-level STG1. For example, the plane area of ​​each of the first-level STG1 may be calculated as the product of the first length L1 and the second length L2. Each of the first-level STG1 may have the same structure and may be repeatedly arranged along the second direction D2, and the first length L1 may be defined as the vertical length of each of the first-level STG1. The second length L2 may be the horizontal length of each of the first-level STG1, and may be substantially equal to the horizontal length of the first gate driver GDV1. In addition, the plane area of ​​the first line portion LP1 may be calculated as the product of the first length L1 and the third length L3. The first line portion LP1 may include a plurality of lines arranged side by side in the first direction D1, and the third length L3 may be defined as a horizontal length from a leftmost line to a rightmost line in the first direction D1.

[0166] In one or more embodiments, the number of first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be substantially equal to the number of contact holes CNT compared to the plane area of ​​each of the first stages STG1. That is, the number of first dummy contact holes DCNT1 per unit area of ​​the first line portion LP1 may be substantially equal to the number of contact holes CNT per unit area of ​​each of the first stages STG1.

[0167] For example, the first length L1 of each of the first stages STG1 may be about 98.6 μm, and the second length L2 may be about 137 μm. In this case, the plane area of ​​each of the first stages STG1 may be about 13508.2 μm. 2In addition, the number of contact holes CNT formed in each of the first stages STG1 may be about 73. Therefore, the number of contact holes CNT compared to the plane area of ​​each of the first stages STG1 may be about 0.0054 / μm 2 .

[0168] The first length L1 of the first line portion LP1 may be about 98.6 μm, and the third length L3 may be about 17 μm. In this case, the plane area of ​​the first line portion LP1 may be about 1676.2 μm. 2 In addition, the number of the first dummy contact holes DCNT1 formed in the first line portion LP1 may be about 9. Therefore, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be about 0.0054 / μm 2 .

[0169] At least one second dummy contact hole DCNT2 may be formed in the second line portion LP2. In one or more embodiments, the second dummy contact hole DCNT2 may overlap the reset signal line ESRL, the gate low voltage line VGLL, and the second clock line CLK2. For example, the second dummy contact hole DCNT2 may be formed at equal intervals as much as possible while avoiding the connection area where each of the second stages STG2 is connected to the second line portion LP2.

[0170] The number of second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may correspond to the number of contact holes CNT compared to the plane area of ​​each of the first stage STG1. That is, the number of second dummy contact holes DCNT2 per unit area of ​​the second line portion LP2 may correspond to the number of contact holes CNT per unit area of ​​each of the first stage STG1.

[0171] For example, as described above, the number of contact holes CNT compared to the plane area of ​​each of the first stages STG1 may be about 0.0054 / μm 2 .

[0172] The first length L1 of the second line portion LP2 may be about 98.6 μm, and the fourth length L4 may be about 30 μm. In this case, the plane area of ​​the second line portion LP2 may be about 2958 μm. 2 In addition, the number of the second dummy contact holes DCNT2 formed in the second line portion LP2 may be about 16. Therefore, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may be about 0.0054 / μm 2 .

[0173] In one or more other embodiments, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be about 70% to about 130% of the number of the contact holes CNT compared to the plane area of ​​each of the first stages STG1. That is, the number of the first dummy contact holes DCNT1 per unit area of ​​the first line portion LP1 may be about 70% to about 130% of the number of the contact holes CNT per unit area of ​​each of the first stages STG1.

[0174] For example, as described above, the number of contact holes CNT compared to the plane area of ​​each of the first stages STG1 may be about 0.0054 / μm 2 .

[0175] As an example, the number of the first dummy contact holes DCNT1 formed in the first line portion LP1 may be about 7. In this case, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be about 0.0042 / μm 2 (e.g., approximately 77%).

[0176] As another example, the number of the first dummy contact holes DCNT1 formed in the first line portion LP1 may be about 8. In this case, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be about 0.0048 / μm 2 (e.g., approximately 88%).

[0177] As another example, the number of the first dummy contact holes DCNT1 formed in the first line portion LP1 may be about 10. In this case, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be about 0.0060 / μm 2 (eg, approximately 110%).

[0178] As another example, the number of the first dummy contact holes DCNT1 formed in the first line portion LP1 may be about 11. In this case, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first line portion LP1 may be about 0.0066 / μm 2 (e.g., approximately 122%).

[0179] In addition, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may be about 70% to about 130% of the number of the contact holes CNT compared to the plane area of ​​each of the first stages STG1 .

[0180] For example, as described above, the number of contact holes CNT compared to the plane area of ​​each of the first stages STG1 may be about 0.0054 / μm 2 .

[0181] As an example, the number of the second dummy contact holes DCNT2 formed in the second line portion LP2 may be about 13. In this case, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may be about 0.0044 / μm 2 (e.g., approximately 81%).

[0182] As another example, the number of the second dummy contact holes DCNT2 formed in the second line portion LP2 may be about 14. In this case, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may be about 0.0047 / μm 2 (e.g., approximately 88%).

[0183] As another example, the number of the second dummy contact holes DCNT2 formed in the second line portion LP2 may be about 18. In this case, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may be about 0.0061 / μm 2 (e.g., approximately 113%).

[0184] As another example, the number of the second dummy contact holes DCNT2 formed in the second line portion LP2 may be about 19. In this case, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second line portion LP2 may be about 0.0064 / μm 2 (e.g., approximately 119%).

[0185] However, the above numerical range (eg, about 70% to 130%) is only an example, and the number of each of the first and second dummy contact holes DCNT1 and DCNT2 compared to the area may be appropriately set based on the number of the contact holes CNT compared to the area.

[0186] In one or more embodiments, the reliability of each of the first stage STG1 can be determined to be good. In this case, as described above, the number of the first dummy contact holes DCNT1 and the number of the second dummy contact holes DCNT2 can be set to correspond to the number of contact holes CNT compared to the plane area of ​​each of the first stage STG1.

[0187] In one or more other embodiments, the reliability of each of the second level STG2 may be determined to be good. In this case, the number of the first dummy contact holes DCNT1 and the number of the second dummy contact holes DCNT2 may be set to correspond to the number of contact holes compared to the plane area of ​​each of the second level STG2.

[0188] refer to Fig.10 and Fig.11 , also refer to Figures 7 to 9 , the first line portion LP1 may further include a first etch stopper 1140. The first etch stopper 1140 may be located at the same layer as the first silicon semiconductor layer 1110, the second silicon semiconductor layer 1120, and the third silicon semiconductor layer 1130, and may include a silicon semiconductor. In one or more other embodiments, the first line portion LP1 may not include the first etch stopper 1140.

[0189] The first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2 may further extend to the first line portion LP1, and the first dummy contact hole DCNT1 may penetrate the first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2. Therefore, the first dummy contact hole DCNT1 may expose the first etch stopper 1140, and the first clock line CLK1 may contact the first etch stopper 1140.

[0190] In one or more embodiments, the first dummy contact hole DCNT1 may be adjacent to the second oxide semiconductor layer 1420. Therefore, hydrogen (H) contained in the second inorganic insulating layer IIL2 (e.g., the second interlayer insulating layer ILD2) may diffuse through the first dummy contact hole DCNT1. Therefore, hydrogen may not diffuse into the second oxide semiconductor layer 1420. Therefore, a negative shift in the threshold voltage of the NMOS transistor included in the first gate driver GDV1 may be reduced or prevented, and the reliability of the NMOS transistor may be improved.

[0191] refer to Fig.10 and Fig.12 , also refer to Figures 7 to 9 , the second line portion LP2 may further include a second etch stopper 1150. The second etch stopper 1150 may be located at the same layer as the first silicon semiconductor layer 1110, the second silicon semiconductor layer 1120, and the third silicon semiconductor layer 1130, and may include a silicon semiconductor.

[0192] The first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2 may further extend to the second line portion LP2, and the second dummy contact hole DCNT2 may penetrate the first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2. Therefore, the second dummy contact hole DCNT2 may expose the second etch stopper 1150, and the second clock line CLK2 may contact the second etch stopper 1150.

[0193] In one or more embodiments, the second dummy contact hole DCNT2 may be adjacent to the third oxide semiconductor layer 1430. Therefore, hydrogen contained in the second inorganic insulating layer IIL2 (e.g., the second interlayer insulating layer ILD2) may diffuse through the second dummy contact hole DCNT2. Therefore, hydrogen may not diffuse into the third oxide semiconductor layer 1430. Therefore, a negative shift in the threshold voltage of the NMOS transistor included in the second gate driver GDV2 may be reduced or prevented, and the reliability of the NMOS transistor may be improved.

[0194] refer to Fig.10 and Fig.13 For example, the fifth gate electrode 1220 of each of the first stages STG1 may extend to overlap the first clock line CLK1. In this case, the first dummy contact hole DCNT1 may be formed to avoid the fifth gate electrode 1220, and the first etch stopper 1140 may be exposed by each of the first dummy contact holes DCNT1.

[0195] Fig.14 yes Figure 6 An enlarged view of the curved portion B.

[0196] refer to Fig.14 , also refer to Figure 6 and Figure 7 , each of the first line portion LP1 and the second line portion LP2 may include a straight line portion SP (or a circuit portion) and a curved portion CP. Figure 6 As shown in , in order to transmit the gate signal to the pixel structure located above and below the display area DA, the first gate driver GDV1, the first line portion LP1, the second gate driver GDV2, and the second line portion LP2 may be bent at the upper and lower sides as if surrounding the display area DA. Fig.14 As shown in FIG. 1 , the curved portion CP may be defined in the first line portion LP1 and the second line portion LP2 . Fig.14The first gate driver GDV1, the first line portion LP1, the second gate driver GDV2 and the second line portion LP2 located at the lower side of the display device 1000 are shown, and the first gate driver GDV1, the first line portion LP1, the second gate driver GDV2 and the second line portion LP2 located at the upper side of the display device 1000 can also basically correspond to this by having a curved portion.

[0197] The third dummy contact hole DCNT3 may be formed in the curved portion CP of the first line portion LP1. The third dummy contact hole DCNT3 may be formed substantially the same as the first dummy contact hole DCNT1. For example, the third dummy contact hole DCNT3 may overlap the first clock line CLK1 and may penetrate the first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2.

[0198] In one or more embodiments, the number of the third dummy contact holes DCNT3 compared to the planar area of ​​the curved portion CP (e.g., per unit area) may correspond to the number of the contact holes CNT compared to the planar area of ​​each of the first stages STG1 (e.g., per unit area). For example, the planar area of ​​the curved portion CP may be approximately 926 μm 2 , and the number of the third dummy contact holes DCNT3 formed in the curved portion CP may be about 5. Therefore, the number of the third dummy contact holes DCNT3 compared to the plane area of ​​the curved portion CP may be about 0.0054 / μm 2 .

[0199] Alternatively, the number of the third dummy contact holes DCNT3 may be set to match the length of the curved portion CP which is proportional to the length of the straight portion SP. For example, if the length of the curved portion CP is about half of the length of the straight portion SP, the number of the third dummy contact holes DCNT3 may be set to about half of the number of the first dummy contact holes DCNT1. In addition, the fourth dummy contact hole DCNT4 may be formed in the curved portion CP of the second line portion LP2. The fourth dummy contact hole DCNT4 may be formed to be substantially the same as the second dummy contact hole DCNT2.

[0200] In addition, spaces SPP1 and SPP2 may be defined between the stages, and a fifth dummy contact hole DCNT5 may be formed in the spaces SPP1 and SPP2. The fifth dummy contact hole DCNT5 may be formed substantially the same as the first dummy contact hole DCNT1. For example, an active pattern serving as an etching stopper may be formed in the spaces SPP1 and SPP2, the fifth dummy contact hole DCNT5 may expose the active pattern, and the inside of the fifth dummy contact hole DCNT5 may be filled with the first via insulating layer VIA1.

[0201] The spaces SPP1 and SPP2 may include a first space SPP1 defined between the first stages STG1 and a second space SPP2 defined between the second stages STG2 .

[0202] The number of the fifth dummy contact holes DCNT5 compared to the plane area of ​​the first space SPP1 may correspond to the number of the contact holes CNT compared to the plane area of ​​each of the first stages STG1. Meanwhile, the plane area of ​​the first space SPP1 may not be constant depending on the curvature of the curved portion CP, the interval between the first stages STG1, etc. In this case, the average distance between the contact holes CNT may be calculated, and the fifth dummy contact hole DCNT5 may have a distance corresponding to the average distance.

[0203] Similarly, the number of the fifth dummy contact holes DCNT5 compared to the plane area of ​​the second space SPP2 may correspond to the number of the contact holes CNT compared to the plane area of ​​each of the first stages STG1. Meanwhile, the plane area of ​​the second space SPP2 may not be constant depending on the curvature of the curved portion CP, the interval between the second stages STG2, etc. In this case, the average distance between the contact holes CNT may be calculated, and the fifth dummy contact hole DCNT5 may have a distance corresponding to the average distance.

[0204] Therefore, the number of the fifth dummy contact holes DCNT5 formed in the first space SPP1 may be different from the number of the fifth dummy contact holes DCNT5 formed in the second space SPP2. For example, if the plane area of ​​the first space SPP1 may be smaller than the plane area of ​​the second space SPP2, the number of the fifth dummy contact holes DCNT5 formed in the first space SPP1 may be smaller than the number of the fifth dummy contact holes DCNT5 formed in the second space SPP2.

[0205] Figures 15 to 20 It shows the manufacturing Figure 6 A cross-sectional view of a method for displaying a device.

[0206] refer to Fig.15 , a first silicon semiconductor layer 1110, a second silicon semiconductor layer 1120, and a first etch stopper 1140 may be formed together on the buffer layer BFR. The first silicon semiconductor layer 1110 may be formed in the display area DA, the second silicon semiconductor layer 1120 may be formed in the first circuit area CA1, and the first etch stopper 1140 may be formed in the first line area LA1.

[0207] refer to Fig.16, a first inorganic insulating layer IIL1 may be formed on the first silicon semiconductor layer 1110, the second silicon semiconductor layer 1120, and the first etch stopper 1140. In detail, a first gate insulating layer GI1, a first gate electrode 1210, a fifth gate electrode 1220, a second gate insulating layer GI2, a second gate electrode 1310, a third gate electrode 1320, a sixth gate electrode 1330, and a first interlayer insulating layer ILD1 may be sequentially formed.

[0208] refer to Fig.17 , a first oxide semiconductor layer 1410 and a second oxide semiconductor layer 1420 may be formed on the first inorganic insulating layer IIL1. The first oxide semiconductor layer 1410 may be formed in the display area DA, and the second oxide semiconductor layer 1420 may be formed in the first circuit area CA1.

[0209] refer to Fig.18 , a second inorganic insulating layer IIL2 may be formed on the first oxide semiconductor layer 1410 and the second oxide semiconductor layer 1420. In detail, a third gate insulating layer GI3, a fourth gate electrode 1510, a seventh gate electrode 1520, and a second interlayer insulating layer ILD2 may be sequentially formed.

[0210] refer to Fig.19 , a contact process may be performed. For example, a contact hole CNT may be formed in the first circuit area CA1, and a first dummy contact hole DCNT1 may be formed in the first line area LA1. The contact hole CNT and the first dummy contact hole DCNT1 may be formed together. In addition, a contact hole CNT may be further formed in the display area DA and the first circuit area CA1.

[0211] refer to Fig. 20 , a first connection electrode 1610, a second connection electrode 1620, a third connection electrode 1630, a fourth connection electrode 1640, a sixth connection electrode 1650, a seventh connection electrode 1660, an eighth connection electrode 1670, and a ninth connection electrode 1680 and a first clock line CLK1 may be formed on the second interlayer insulating layer ILD2. The sixth connection electrode 1650 and the seventh connection electrode 1660 may contact the second silicon semiconductor layer 1120 through the contact hole CNT, and the first clock line CLK1 may contact the first etching stopper 1140 through the dummy contact hole DCNT1.

[0212] In addition, a first via insulating layer VIA1, a fifth connection electrode 1710, a second via insulating layer VIA2, a pixel electrode ADE, a pixel defining layer PDL (see FIG. 14 ) may be sequentially formed. Figure 7 ), the emission layer EL and the common electrode CTE.

[0213] According to the above method of manufacturing a display device, the first dummy contact hole DCNT1 may be formed by the same contact process as the contact process of the contact hole CNT. Therefore, a separate contact process for forming the first dummy contact hole DCNT1 may not be added.

[0214] Fig.21 is a plan view showing a display device according to one or more other embodiments of the present disclosure. Fig. 22 yes Fig.21 An enlarged view of the straight line portion C of FIG.

[0215] refer to Fig.21 , except for the first dummy area DMA1, the second dummy area DMA2, and the third dummy area DMA3, the display device 2000 according to one or more other embodiments of the present disclosure may be the same as the reference Figure 6 The display devices 1000 described are substantially the same.

[0216] In one or more embodiments, the first dummy area DMA1 may be located between the first circuit area CA1 and the first line area LA1. The second dummy area DMA2 may be located between the second circuit area CA2 and the second line area LA2. The third dummy area DMA3 may be located between the third circuit area CA3 and the third line area LA3.

[0217] However, the area where the first dummy area DMA1, the second dummy area DMA2 and the third dummy area DMA3 are located is not limited to the above area. For example, the first dummy area DMA1 may be located between the display area DA and the first circuit area CA1. Alternatively, the first dummy area DMA1 may be located between the first line area LA1 and the second circuit area CA2.

[0218] refer to Fig. 22 , also refer to Figure 7 , the first dummy contact hole DCNT1 may be formed in the first dummy area DMA1. For example, the first dummy contact hole DCNT1 may penetrate the first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2 extending to the first dummy area DMA1. In addition, as described above, the number of the first dummy contact holes DCNT1 compared to the plane area of ​​the first dummy area DMA1 may correspond to the number of the contact holes CNT compared to the plane area of ​​each of the first stages STG1.

[0219] The second dummy contact hole DCNT2 may be formed in the second dummy area DMA2. For example, the second dummy contact hole DCNT2 may penetrate the first inorganic insulating layer IIL1 and the second inorganic insulating layer IIL2 extending to the second dummy area DMA2. In addition, as described above, the number of the second dummy contact holes DCNT2 compared to the plane area of ​​the second dummy area DMA2 may correspond to the number of the contact holes CNT compared to the plane area of ​​each of the first stages STG1.

[0220] Since the first dummy contact hole DCNT1 is formed in the separate first dummy area DMA1, the dummy contact hole may not be formed in the first line portion LP1. Therefore, the reliability of the line located in the first line portion LP1 may be improved.

[0221] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the present disclosure is not limited to such embodiments, but includes the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A display device, wherein: The display device comprises: A pixel circuit portion including a first oxide semiconductor layer; a first gate driver electrically connected to the pixel circuit portion, the first gate driver including a second oxide semiconductor layer in the same layer as the first oxide semiconductor layer; and A first line portion is electrically connected to the first gate driver, and the first line portion defines at least one first dummy contact hole adjacent to the second oxide semiconductor layer.

2. The display device according to claim 1, wherein: The first line portion includes at least one first clock line, the at least one first clock line overlaps the first dummy contact hole, and the at least one first clock line is used to provide a clock signal to the first gate driver.

3. The display device according to claim 1, wherein: The display device further includes a second gate driver electrically connected to the pixel circuit portion, and the second gate driver includes a third oxide semiconductor layer in the same layer as the second oxide semiconductor layer.

4. The display device according to claim 3, wherein: The display device further includes a second line portion adjacent to the second gate driver, the second line portion being electrically connected to the second gate driver, and the second line portion defining at least one second dummy contact hole adjacent to the third oxide semiconductor layer.

5. The display device according to claim 4, wherein: The second line portion includes at least one second clock line, the at least one second clock line overlaps the second dummy contact hole, and the at least one second clock line is used to provide a clock signal to the second gate driver.

6. The display device according to claim 1, wherein: The first gate driver further includes: at least one first inorganic insulating layer below the second oxide semiconductor layer; and at least one second inorganic insulating layer, above the second oxide semiconductor layer, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the first line portion, and The first dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the first line portion.

7. The display device according to claim 6, wherein: The pixel circuit portion further includes a first silicon semiconductor layer below the first oxide semiconductor layer. Wherein, the first gate driver further includes a second silicon semiconductor layer below the second oxide semiconductor layer, and The first line portion includes an etching stopper located at the same layer as the second silicon semiconductor layer.

8. The display device according to claim 7, wherein: The first dummy contact hole exposes the etch stopper.

9. The display device according to claim 8, wherein: The first line portion further includes at least one first clock line, the at least one first clock line contacts the etch stopper through the first dummy contact hole, and the at least one first clock line is used to provide a clock signal to the first gate driver.

10. The display device according to claim 6, wherein: The first gate driver is divided into a plurality of first stages, wherein one or more contact holes penetrating the first inorganic insulating layer and the second inorganic insulating layer are defined in the plurality of first levels, and The number of the first dummy contact holes per unit area of ​​the first line portion corresponds to the number of the contact holes per unit area of ​​each of the plurality of first levels.

11. The display device according to claim 10, wherein: The number of the first dummy contact holes per unit area of ​​the first line portion is 70% to 130% of the number of the contact holes per unit area of ​​each of the plurality of first levels.

12. The display device according to claim 10, wherein: The display device further includes: A second gate driver is divided into a plurality of second stages; and a second line portion electrically connected to the second gate driver, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the second gate driver and to the second line portion, wherein at least one second dummy contact hole is defined in the second line portion, and the at least one second dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the second line portion, and The number of the second dummy contact holes per unit area of ​​the second line portion corresponds to the number of the contact holes per unit area of ​​each of the plurality of first levels.

13. The display device according to claim 1, wherein: The first line portion includes a straight line portion, and includes a bent portion defining a third dummy contact hole.

14. The display device according to claim 13, wherein: The first gate driver further includes: at least one first inorganic insulating layer below the second oxide semiconductor layer; and at least one second inorganic insulating layer, above the second oxide semiconductor layer, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the first line portion, and The third dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the bent portion.

15. The display device according to claim 14, wherein: The first gate driver is divided into a plurality of first stages, wherein at least one contact hole penetrating the first inorganic insulating layer and the second inorganic insulating layer is defined in the plurality of first levels, and wherein the number of the third dummy contact holes per unit area of ​​the bent portion corresponds to the number of the contact holes per unit area of ​​each of the plurality of first levels.

16. The display device according to claim 1, wherein: The pixel circuit portion further includes a first silicon semiconductor layer below the first oxide semiconductor layer, and The first gate driver further includes a second silicon semiconductor layer located in the same layer as the first silicon semiconductor layer.

17. The display device according to claim 1, wherein: The display device further includes a second gate driver electrically connected to the pixel circuit portion, and the second gate driver includes a third oxide semiconductor layer in the same layer as the second oxide semiconductor layer, The first gate driver is configured to provide a gate compensation signal to the pixel circuit unit, and The second gate driver is configured to provide a gate bias signal to the pixel circuit unit.

18. The display device according to claim 1, wherein: The display device further includes a second gate driver electrically connected to the pixel circuit portion, and the second gate driver includes a third oxide semiconductor layer in the same layer as the second oxide semiconductor layer, The first gate driver is configured to provide a gate compensation signal to the pixel circuit unit, and The second gate driver is configured to provide an emission management signal to the pixel circuit unit.

19. A display device, wherein: The display device comprises: a first oxide semiconductor layer overlapping the display area; a second oxide semiconductor layer, which is in the same layer as the first oxide semiconductor layer, and the second oxide semiconductor layer overlaps a circuit region adjacent to the display region; and at least one inorganic insulating layer overlaps the circuit area and a line area adjacent to the circuit area, and the at least one inorganic insulating layer defines at least one dummy contact hole, and The dummy contact hole is adjacent to the second oxide semiconductor layer and is defined by the inorganic insulating layer.

20. The display device according to claim 19, wherein: The display device further includes at least one clock line, and the at least one clock line overlaps the line area and overlaps the dummy contact hole.

21. The display device according to claim 19, wherein: The inorganic insulating layer comprises: a first inorganic insulating layer, below the second oxide semiconductor layer; and a second inorganic insulating layer, above the second oxide semiconductor layer, wherein the first inorganic insulating layer and the second inorganic insulating layer extend to the line region, and The dummy contact hole penetrates the first inorganic insulating layer and the second inorganic insulating layer overlapping the line region.

22. The display device according to claim 21, wherein: The display device further includes: a first silicon semiconductor layer overlapping the display area and below the first oxide semiconductor layer; a second silicon semiconductor layer overlapping the circuit region and below the second oxide semiconductor layer; and An etch stopper overlaps the line region, and the etch stopper is in the same layer as the second silicon semiconductor layer.

23. The display device according to claim 22, wherein: The dummy contact hole exposes the etch stopper.

24. The display device according to claim 23, wherein: The display device further includes at least one clock line, the at least one clock line overlaps the line area, and the at least one clock line contacts the etching stopper through the dummy contact hole.

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