Infrared detector and manufacturing method thereof

Abstract

The invention provides an infrared detector and a manufacturing method thereof, the infrared detector comprises a substrate, a conductive interconnection layer, a passivation layer, a bonding pad hole and a plurality of nanoholes, the substrate is provided with an MEMS array and an integrated circuit located on the periphery of the MEMS array, the conductive interconnection layer is located above the substrate and comprises a dielectric layer, at least one metal layer and a bonding pad, and the bonding pad hole is formed in the substrate. The bonding pad is located above the integrated circuit, the passivation layer is located above the conductive interconnection layer, the bonding pad hole and the nanohole are opened from the passivation layer and extend downwards, the bonding pad hole extends to expose at least one part of the bonding pad, the nanohole is located above the MEMS array and extends into the dielectric layer, and the nanohole and the bonding pad hole can be manufactured in the same step. The structure of the infrared detector is completely compatible with the CMOS technology, no extra cost is generated, the infrared absorption rate can be effectively improved through the nanopores, the thickness of the film layer of the infrared detector is reduced so as to reduce heat loss, and the working performance is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and in particular to an infrared detector and a manufacturing method thereof. Background Art

[0002] MEMS thermopile infrared detector is an electrically readout uncooled infrared detector. Its working principle is infrared radiation detection based on the Seebeck effect, and the infrared radiation detection signal is output to the circuit for processing to obtain the intensity, wavelength and other characteristics of the infrared light source. MEMS infrared detectors are widely used in various fields due to their low cost, small size and good stability. At present, MEMS infrared detectors are developing towards high performance, miniaturization, intelligence and compatibility with CMOS. The main disadvantages of traditional thermopile infrared detectors are that the infrared absorption efficiency of the infrared absorption layer material is low, the absorption rate of infrared light in different bands is quite different, and the thermocouple material is not compatible with CMOS, resulting in high production costs.

[0003] At present, one of the methods to improve the performance of MEMS infrared detectors is to improve the material or structure of the infrared absorption layer to improve the detector's absorption effect on infrared light of a specific wavelength, thereby achieving the technical effect of improving the device's response rate. Existing infrared thermopiles mainly improve the device's infrared absorption by preparing absorbers, thin layers of ferrous metal materials, interference films, etc. on their surfaces. However, on the one hand, the existing methods are difficult to prepare various complex absorption materials or absorbers, and the overall process structure is relatively complex and costly, which is not conducive to low-cost mass production. On the other hand, the production of absorbers or absorption materials is not compatible with the CMOS process, and the production cost cannot be reduced. Alternatively, the introduction of infrared absorption materials can be compatible with the CMOS process to a certain extent, but at the same time it will cause a loss of other working performance of the infrared detector.

[0004] Therefore, how to solve the problems of low infrared absorption rate, complex structure, high cost, and incompatibility with CMOS process in the infrared detectors in the prior art has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an infrared detector and a method for manufacturing the same, so as to solve the problems of low infrared absorption rate, complex structure, high cost and incompatibility with CMOS process in the prior art infrared detector.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides an infrared detector, comprising:

[0008] A substrate having a MEMS array and an integrated circuit located at the periphery of the MEMS array;

[0009] A conductive interconnect layer and a passivation layer, wherein the conductive interconnect layer is located above the substrate and covers the MEMS array and the integrated circuit, the conductive interconnect layer comprises a dielectric layer, at least one metal layer embedded in the dielectric layer, and a pad located on the dielectric layer, the pad is electrically connected to the metal layer and is located above the integrated circuit, and the passivation layer is located above the conductive interconnect layer and covers the pad;

[0010] At least one pad hole and a plurality of nanoholes for enhancing infrared absorption, wherein the pad hole opens from the passivation layer and extends downward to expose at least a portion of the pad, the plurality of nanoholes are located above the MEMS array and the plurality of nanoholes are arranged at intervals, and the nanoholes open from the passivation layer and extend downward into the dielectric layer.

[0011] Optionally, the arrangement of the plurality of nanopores includes at least one of a rectangular array arrangement and a staggered array arrangement.

[0012] Optionally, the nanopore is a regular polygon, and the side length of the nanopore ranges from 0.1 μm to 5 μm, the spacing between two adjacent nanopores ranges from 0.1 μm to 5 μm, and the ratio of the side length of the nanopore to the spacing between two adjacent nanopores ranges from 1:50 to 50:1.

[0013] Optionally, the MEMS array includes a plurality of thermal stack pixels arranged in an array, each of the thermal stack pixels includes a cavity and a thermoelectric pile, the cavity is buried in the substrate, a portion of the substrate located above the cavity constitutes a suspension layer, the thermoelectric pile is located above the substrate and the thermoelectric pile extends onto the suspension layer.

[0014] Optionally, a portion of the substrate surrounding the cavity constitutes a support frame, the suspension layer includes a central support film and a plurality of cantilever beams arranged around the central support film, and the cantilever beams are connected between the support frame and the central support film.

[0015] Optionally, each of the thermal stack pixels further comprises a plurality of main release grooves, wherein the main release grooves are located between two adjacent cantilever beams and vertically penetrate the suspension layer and communicate with the cavity.

[0016] Optionally, an angle is formed between a surface of the main release groove adjacent to the support frame and a surface of the main release groove adjacent to the cantilever beam, and the angle includes at least one of an arc angle, an obtuse angle and a right angle.

[0017] Optionally, each of the hot-end picture elements further comprises a plurality of auxiliary release grooves, wherein the auxiliary release grooves vertically penetrate the suspension layer and communicate with the cavity, and the auxiliary release grooves horizontally extend from the cantilever beam to the central support film, and the extension direction of the auxiliary release grooves is the same as the extension direction of the cantilever beam.

[0018] Optionally, the temperature differential thermal stack includes a plurality of sets of spaced-apart thermocouple pairs, the thermocouple pairs extending from the support frame via the cantilever beam toward the central support membrane, at least a portion of the thermocouple pairs extending onto the central support membrane, the thermocouple pairs including a cold end and a hot end relatively disposed, the cold end being located on the support frame.

[0019] Optionally, the hot ends of multiple groups of the thermocouple pairs are all located above the central supporting film, the cantilever beam includes a first cantilever region and a second cantilever region, the first cantilever region and the second cantilever region are arranged on both sides of the central axis of the horizontal extension direction of the auxiliary release groove, the hot ends of all the thermocouple pairs extending through the first cantilever region are located on a first straight line, and the hot ends of all the thermocouple pairs extending through the second cantilever region are located on a second straight line, and the first straight line coincides with or intersects with the second straight line.

[0020] Optionally, the temperature difference thermal stack includes at least one group of first thermocouple pairs and at least one group of second thermocouple pairs, the cantilever beam includes a central cantilever area and edge cantilever areas located on both sides of the central cantilever area, and the part of the auxiliary release groove located in the cantilever beam is located in the central cantilever area;

[0021] The first thermocouple pair extends through the central cantilever area and the hot end of the first thermocouple pair is located on the side of the auxiliary release groove facing the support frame, the hot end of the first thermocouple pair is located on a straight line and the straight line is perpendicular to the extension direction of the cantilever beam, the second thermocouple pair extends through the edge cantilever area and the hot end of the second thermocouple pair is located on the central support film, the width of the second thermocouple pair on the side of the straight line away from the central support film is equal to the width of the first thermocouple pair, and the width of the second thermocouple pair on the side of the straight line facing the central support film is greater than the width of the first thermocouple pair.

[0022] Optionally, each of the thermal pile picture elements further comprises a plurality of heating resistors arranged at intervals, and the plurality of heating resistors are located on the central supporting film and are sequentially connected in series.

[0023] Optionally, each of the thermal pile pixels further comprises a heat capacity enhancement body, wherein the heat capacity enhancement body is located at the central support film, and the heat capacity enhancement body is spaced apart from the thermocouple pair and the heating resistor.

[0024] The present invention also provides a method for manufacturing an infrared detector, comprising the following steps:

[0025] Providing a substrate, the substrate comprising a first region and a second region located outside the first region;

[0026] forming a MEMS array and an integrated circuit on the substrate, wherein the MEMS array is located in the first area and the integrated circuit is located in the second area;

[0027] forming a conductive interconnect layer and a passivation layer on the substrate in sequence, wherein the conductive interconnect layer covers the MEMS array and the integrated circuit, the conductive interconnect layer comprises a dielectric layer, at least one metal layer embedded in the dielectric layer, and a pad located on the dielectric layer, and the passivation layer covers the conductive interconnect layer;

[0028] At least one pad hole and a plurality of nanoholes for enhancing infrared absorption are formed, wherein the pad hole opens from the passivation layer and extends downward to expose at least a portion of the pad, the plurality of nanoholes are located above the MEMS array and the plurality of nanoholes are arranged at intervals, and the nanoholes open from the passivation layer and extend downward into the dielectric layer.

[0029] As described above, the infrared detector of the present invention includes a MEMS array and an integrated circuit located at the periphery of the MEMS array. The overall structure is simple and the signal-to-noise ratio is convenient to adjust. Among them, the upper part of the MEMS array has an infrared enhancement structure composed of a plurality of nanoholes, which can effectively improve the infrared absorption efficiency of the infrared detector, reduce the thermal conductivity of the film layer and reduce heat loss, and the infrared absorption rate can be effectively regulated by adjusting the arrangement, shape and size of the nanoholes and the thermocouple structure and arrangement of the temperature difference heat pile in the MEMS array. More importantly, the temperature difference heat pile and the infrared enhanced absorption structure in the MEMS array are fully compatible with the CMOS process and will not increase any additional costs. The infrared detector manufacturing method of the present invention can realize the simultaneous manufacturing of the MEMS array and the integrated circuit in the infrared detector, and can also realize the simultaneous manufacturing of the nanoholes and the pad holes. The entire manufacturing step is fully compatible with the CMOS process, and the infrared absorption enhancement structure in the infrared detector is realized without increasing any additional costs. The simple structure can realize low-cost mass production, which effectively improves the competitiveness of the infrared detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shown is a schematic diagram of the cross-sectional structure of the infrared detector of the present invention.

[0031] Figure 2 Shown is a schematic diagram of the top view of the structure of the infrared detector of the present invention.

[0032] Figure 3 It is a schematic diagram showing the overall structure of the infrared enhancement structure in the infrared detector of the present invention in the first embodiment.

[0033] Figure 4 It is a schematic diagram of the top view structure of the thermal pile pixel in the infrared detector of the present invention in the first embodiment.

[0034] Figure 5 It is a schematic diagram of the explosion structure of the thermal pile pixel in the infrared detector of the present invention in the first embodiment.

[0035] Figure 6 It shows a schematic plan layout of the suspension layer, support frame and cavity structure in the thermal pile pixel of the infrared detector of the present invention.

[0036] Figure 7 It is a schematic diagram of the top view of the structure after the nanohole is formed in the thermal pile pixel of the infrared detector of the present invention.

[0037] Figure 8 It is a schematic structural diagram of the angle between the main release groove of the thermal pile pixel and the support frame in the infrared detector of the present invention without chamfering.

[0038] Fig. 9 Display as Figure 8 Schematic diagram of the enlarged structure of the middle angle.

[0039] Fig.10 It is a schematic structural diagram showing the angle between the main release groove of the thermal pile pixel and the support frame in the infrared detector of the present invention after being rounded.

[0040] Fig.11 Display as Fig.10 Schematic diagram of the enlarged structure of the middle angle.

[0041] Fig.12 It is a schematic structural diagram showing the angle between the main release groove of the thermal pile pixel and the support frame in the infrared detector of the present invention after being chamfered.

[0042] Fig.13 Display as Fig.12 Schematic diagram of the enlarged structure of the middle angle.

[0043] Fig.14Shown is a schematic diagram of the nanohole array structure in which square nanoholes are arranged in a rectangular array in the infrared detector of the present invention.

[0044] Fig.15 It shows a schematic diagram of the nanohole array structure in which regular hexagonal nanoholes are arranged in a staggered array in the infrared detector of the present invention.

[0045] Fig.16 Display as Fig.14 Schematic diagram of the enlarged structure of region II.

[0046] Fig.17 Schematic diagram showing the infrared absorption effect of the infrared detector of the present invention and a general infrared detector

[0047] Fig.18 It is a schematic diagram of the top view structure of the thermal pile pixel in the infrared detector of the present invention in the second embodiment.

[0048] Fig.19 It is a schematic diagram of the top view structure of the thermal pile pixel in the infrared detector of the present invention in the third embodiment.

[0049] Fig. 20 A flow chart showing the steps of the method for manufacturing the infrared detector of the present invention.

[0050] Fig.21 A schematic diagram showing the cross-sectional structure after the well region is formed in the method for manufacturing the infrared detector of the present invention.

[0051] Fig. 22 A schematic diagram showing the cross-sectional structure after the isolation structure is formed in the method for manufacturing the infrared detector of the present invention.

[0052] Fig.23 A schematic diagram showing the cross-sectional structure after forming polysilicon thermocouple strips and polysilicon gates in the method for manufacturing the infrared detector of the present invention.

[0053] Fig.24 A schematic diagram showing the cross-sectional structure after a MOS tube is formed in the method for manufacturing the infrared detector of the present invention.

[0054] Fig.25 A schematic diagram showing the cross-sectional structure after the first metal layer is formed in the method for manufacturing the infrared detector of the present invention.

[0055] Fig.26 A schematic diagram showing the cross-sectional structure after forming a passivation layer in the method for manufacturing the infrared detector of the present invention.

[0056] Fig. 27 A schematic diagram showing the cross-sectional structure after forming pad holes and nanoholes in the method for manufacturing the infrared detector of the present invention.

[0057] Fig.28 A schematic diagram showing the cross-sectional structure after the release groove is formed in the method for manufacturing the infrared detector of the present invention.

[0058] Fig.29 A schematic diagram showing the cross-sectional structure after the cavity is formed in the method for manufacturing the infrared detector of the present invention.

[0059] Component number description

[0060] 1 Substrate

[0061] 11. First Area

[0062] 111 First Isolation Structure

[0063] 12 Second Area

[0064] 121 N-well

[0065] 122 P-well

[0066] 123 Second isolation structure

[0067] 13. First conductivity type polysilicon gate

[0068] 14 Second conductivity type polysilicon gate

[0069] 2 MEMS array

[0070] 20 Thermal Pile Pixels

[0071] 21 Cavity

[0072] 22 Thermocouple

[0073] 23 Thermocouple Pair

[0074] 23a The first thermocouple pair

[0075] 23b Second thermocouple pair

[0076] 231 First conductivity type polysilicon thermocouple strip

[0077] 232 Second conductivity type polysilicon thermocouple strip

[0078] 233 Cold End

[0079] 234, 234a, 234b Hot end

[0080] 24 Suspension layer

[0081] 241 Center support film

[0082] 242 Cantilever beam

[0083] 242a First cantilever area

[0084] 242b Second cantilever area

[0085] 242c Central cantilever area

[0086] 242d Edge cantilever area

[0087] 25 Support frame

[0088] 26 Main release groove

[0089] 27 Auxiliary release groove

[0090] 28 Heating resistor

[0091] 29 Heat capacity enhancement

[0092] 3 Integrated Circuits

[0093] 4 Conductive Interconnect Layer

[0094] 41 Dielectric layer

[0095] 411 First dielectric layer

[0096] 42 Metal Layer

[0097] 421 Metal Plug

[0098] 422 First Metal Layer

[0099] 43 pads

[0100] 5 Passivation layer

[0101] 6 pad holes

[0102] 7 Nanopore

[0103] Area I and II

[0104] Steps S1 to S4 DETAILED DESCRIPTION

[0105] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0106] See also Figures 1 to 29It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0107] Embodiment 1

[0108] This embodiment provides an infrared detector. Figure 1 , which is a schematic diagram of the cross-sectional structure of the infrared detector, including a substrate 1, a conductive interconnection layer 4, a passivation layer 5, a pad hole 6 and a plurality of nanoholes 7.

[0109] For details, please refer to Figure 2 , which is a schematic diagram of the top view of the infrared detector, wherein the substrate 1 is provided with a MEMS array 2 and an integrated circuit 3 located outside the MEMS array 2; please refer to Figure 1 The conductive interconnect layer 4 is located above the substrate 1 and covers the MEMS array 2 and the integrated circuit 3. The conductive interconnect layer 4 includes a dielectric layer 41, at least one metal layer 42 embedded in the dielectric layer 41, and a pad 43 located on the dielectric layer 41, and the pad 43 is located above the integrated circuit 3. The passivation layer 5 is located above the conductive interconnect layer 4 and the passivation layer 5 covers the pad 43. The pad hole 6 opens from the passivation layer 5 and extends downward to expose at least a portion of the pad 43. A plurality of nanoholes 7 are located above the MEMS array 2 and the plurality of nanoholes 7 are arranged at intervals. The nanohole 7 opens from the passivation layer 5 and extends downward into the dielectric layer 41.

[0110] As an example, the nanopore 7 and the pad hole 6 are made in the same step or in separate steps. In this embodiment, the nanopore 7 and the pad hole 6 are made in the same step (using the same mask for photolithography), which effectively saves process steps and reduces production costs while ensuring that the manufactured nanopore 7 can have a good effect on improving infrared absorption efficiency. Of course, in other embodiments, the nanopore 7 can be made after the pad hole 6 is made, or the nanopore 7 can be made before the pad hole 6, so as to achieve precise control of the formation process of the nanopore 6 to obtain a nanopore with an optimal depth.

[0111] Specifically, the infrared detector structure of this embodiment includes nanopores for improving infrared absorption efficiency. Since the overall thickness of the multi-layer dielectric layer in the standard integrated circuit process is relatively large, and the infrared absorption efficiency of the entire film layer needs to be improved, multiple nanopores are prepared on the upper surface of the multi-layer dielectric layer. The multiple nanopores and the passivation layer and part of the dielectric layer that they penetrate constitute an infrared absorption enhancement structure. Please refer to Figure 3 , showing a schematic diagram of the overall structure of the infrared absorption enhancement structure, which can effectively enhance the infrared absorption efficiency of the film layer, and the pad hole and the nanopore are obtained in the same manufacturing step, achieving full compatibility between the infrared absorption enhancement structure and the standard CMOS process, without requiring additional manufacturing costs, and even if the infrared absorption enhancement structure is added, the overall structure of the infrared detector is still relatively simple, and will not increase the difficulty of the manufacturing process, and low-cost mass production can be achieved. In addition, the MEMS array is also fully compatible with the CMOS process, and more structural layers can be obtained in the same process step during manufacturing (for example, the thermocouple pairs in the MEMS array and the gate electrodes in the integrated circuit are manufactured in the same step), further saving manufacturing costs. In addition, in addition to improving the infrared absorption effect, the nanopore can also reduce heat loss and further improve the performance of the infrared detector because it greatly reduces the thickness of the film layer on the surface of the infrared detector and reduces the thermal conductivity of the film layer.

[0112] As an example, see Figure 2 The MEMS array 2 includes a plurality of thermal stack pixels 20 arranged in an array, see Figure 4 , which is a schematic diagram of a top view structure of each of the thermal pile pixels in this embodiment. To facilitate understanding of the positional relationship between the various structures of the thermal pile pixels, please refer to Figure 5 , Figure 6 and Figure 7 ,in, Figure 5 Schematic diagram of the explosion structure shown as a hot pile pixel, Figure 6 It is a schematic diagram of a plan layout of the suspension layer, support frame and cavity in the thermal pile pixel (equivalent to omitting Figure 4 Thermocouples in the structure), Figure 7 The top view of the structure of the thermal pile pixel after the nanohole is formed is shown. Each of the thermal pile pixel 20 includes a cavity 21 and a temperature difference thermal pile 22. Figure 5 As shown, the cavity 21 is buried in the substrate 1. Figure 5 and Figure 6 As shown, the portion of the substrate 1 located above the cavity 21 constitutes a suspension layer 24 , the thermopile 22 is located above the substrate 1 and the thermopile 22 extends onto the suspension layer 24 .

[0113] As an example, Figure 6As shown, the portion of the substrate 1 surrounding the cavity 21 constitutes a support frame 25, and the suspension layer 24 includes a central support film 241 and a plurality of cantilever beams 242 arranged around the central support film 241, and the cantilever beams 242 are connected between the support frame 25 and the central support film 241.

[0114] As an example, Figure 4 As shown, the temperature difference heat pile 22 includes multiple groups of spaced thermocouple pairs 23, the thermocouple pairs 23 extend from the support frame 25 toward the central support film 241 via the cantilever beam 242, at least a portion of the thermocouple pairs 23 extend to the central support film 241, the thermocouple pairs 23 include a cold end 233 and a hot end 234 that are relatively arranged, and the cold end 233 is located on the support frame 25. In this embodiment, four cantilever beam structures are included, and multiple groups of thermocouple pairs are evenly arranged on each cantilever beam structure, and the central support film is a regular octagon. In other embodiments, the shape of the central support film, the number and positional relationship of the cantilever beams, and the number and structure of thermocouple pairs distributed thereon can be reasonably adjusted based on actual needs.

[0115] As an example, the corrosion depth of the cavity 21 ranges from 20 μm to 100 μm. In this embodiment, the corrosion depth of the cavity 21 is 100 μm, which can ensure that the overall volume of the thermal stack pixel 20 is relatively small, while achieving the maximum insulation effect to reduce heat loss and ensure good voltage response performance of the infrared detector.

[0116] As an example, the thermocouple pair 23 is composed of a first conductivity type polysilicon thermocouple bar 231 and a second conductivity type polysilicon thermocouple bar 232, and the first conductivity type is P type or N type, that is, the temperature difference thermal stack 22 is composed of P type polysilicon thermocouple bars and N type polysilicon thermocouple bars arranged alternately, and the two thermocouple bars in the same thermocouple pair 23 are connected in series, and the two adjacent thermocouple pairs are also connected in series, and the series connection is achieved by connecting through aluminum.

[0117] Specifically, in this embodiment, the thermocouple pairs 23 are all extended to the central support film 241, that is, the hot ends of all the thermocouple pairs 23 are located on the central support film 241. Further, all the thermocouple pairs 23 only extend into the edge area above the central support film 241 and then stop extending, and all the hot ends form a polygonal area to reserve a large space for the heat capacity enhancement body. In other embodiments, the extension degree of the thermocouple pairs 23 can be set based on actual needs to adjust the response voltage and resistance of the thermopile, and then adjust the signal-to-noise ratio of the infrared detector.

[0118] As an example, Figure 5 and Figure 6As shown, each of the thermal stack pixels 20 further includes a plurality of main release grooves 26 . The main release grooves 26 are located between two adjacent cantilever beams 242 and vertically penetrate the suspension layer 24 to communicate with the cavity 21 .

[0119] As an example, each of the thermal stack pixels 20 further includes a plurality of auxiliary release grooves 27, wherein the auxiliary release grooves 27 vertically penetrate the suspension layer and communicate with the cavity 21, and the auxiliary release grooves 27 extend horizontally from the cantilever beam 242 to the central support film 241, and the extension direction of the auxiliary release grooves 27 is the same as the extension direction of the cantilever beam 242. The number and structure of the main release grooves 26 and the auxiliary release grooves 27 are set according to the structure and number of the cantilever beam 242. In this embodiment, the main release grooves 26 and the auxiliary release grooves 27 are both 4, while in other embodiments, they may include less than 4 or more than 4.

[0120] Specifically, in this embodiment, the cavity 21 is mainly manufactured by the main release groove 26, and the auxiliary release groove 27 mainly plays an auxiliary role, which avoids the substrate part under the central support film 241 from remaining (that is, avoids the central support film 241 from being connected to a part of the substrate structure), while further improving the release rate of the cavity 21 and improving the manufacturing efficiency. That is, the cooperation between the main release groove 26 and the auxiliary release groove 27 ensures that the bulk silicon under the suspension layer 24 is completely released when the substrate is corroded by anisotropic etching liquid, thereby reducing heat loss and ensuring a good voltage response.

[0121] As an example, the distance range between the main release groove 26 and the cold end 233 is ( Figure 4 (a) is greater than 5 μm, and the distance between the main release groove 26 and the edge of the cavity 21 is in the range of (( Figure 4 b) is 5μm to 20μm. The above distance range can prevent the lateral etching error when the substrate 1 is anisotropically wet-etched based on the main release groove 26, resulting in the cold end 233 not being completely connected to the support frame 25, causing the output signal of the MEMS array 2 to be low, thereby causing damage to the working performance of the infrared detector. In this embodiment, the distance between the main release groove 26 and the cold end 233 is preferably set to 15μm, and the distance between the main release groove and the edge of the cavity is preferably set to 10μm.

[0122] As an example, a side of the main release groove 26 adjacent to the support frame 25 and a side of the main release groove 26 adjacent to the cantilever beam 242 form an angle ( Figure 6The angle includes at least one of a circular arc angle, an obtuse angle and a right angle. That is, after the main release groove 26 is formed, the angle between the side of the main release groove 26 facing the support frame 25 and the side of the main release groove 26 facing the cantilever beam 242 is an acute angle, see Figure 8 and Fig. 9 ,in Figure 8 This is the appearance of the angle without chamfering. Fig. 9 Display as Figure 8 The enlarged structural diagram of the angle in the figure needs to be chamfered to make the original acute angle become any of the arc angle, right angle or obtuse angle. Please refer to Figures 10 to 13 ,in, Fig.10 The angle is shown as a rounded shape after chamfering. Fig.11 Display as Fig.10 The enlarged structural diagram of the angle is shown in FIG. Fig.12 The angle is shown as a right angle after chamfering. Fig.13 Display as Fig.12 The enlarged structural diagram of the angle in FIG. 4 shows that the chamfering specification includes 4 μm (not limited to R4 μm when it is an arc angle). The chamfering process can effectively reduce the stress concentrated at the connection between the cantilever beam 242 and the support frame 24, improve the mechanical performance stability of the structure, thereby improving the yield of the product. In addition, it can also prevent the infrared detector structure from stress damage when subjected to external mechanical shock or thermal shock, thereby improving its service life.

[0123] As an example, see Figure 4 , the hot ends 234 of the plurality of thermocouple pairs 23 are all located above the central support film 241, the cantilever beam 242 includes a first cantilever region 242a and a second cantilever region 242b, the first cantilever region 242a and the second cantilever region 242b are arranged on both sides of the central axis of the auxiliary release groove 27 in the horizontal extension direction, and the hot ends 234 of all thermocouple pairs 23 extending through the first cantilever region 242a are located on a first straight line ( Figure 4 The hot ends 234 of all the thermocouple pairs 23 extending through the second cantilever region 242b are located on the second straight line ( Figure 4 It should be noted that when actually manufacturing the thermocouple strip, due to the small errors caused by the limitation of equipment and process, the hot ends of the thermocouple pairs are not completely located on the same straight line. The first straight line and the second straight line can be regarded as ultra-fine strip areas. The coincidence of the first straight line and the second straight line is equivalent to that the hot ends of all thermocouple pairs extending through the same cantilever beam are located in the same strip area.

[0124] As an example, see Figure 4 The thermal stack pixel 20 further includes a plurality of heating resistors 28 arranged at intervals, and the plurality of heating resistors 28 are located above the central support film 241 and are connected in series in sequence, and the heating resistors 28 are arranged at intervals from the thermocouple pair 23. The heating resistors 28 include P-type polysilicon or N-type polysilicon, and the heating resistors 28 are all located near the hot end 234 extending into the central support film 241 through each cantilever beam 242, preferably between the two hot ends 234 extending into the central support film 241 through two adjacent cantilever beams 242. The heating resistors 28 are used to heat the thermopile 22 to achieve the purpose of self-detection calibration of the thermopile 22, and to determine whether the thermopile 22 is working normally. In addition, in combination with special packaging, the technical effect of gas flow measurement can be achieved.

[0125] As an example, see Figure 4 The thermal stack pixel 20 further includes a heat capacity enhancement body 29, which is located above the central support film 241. The heat capacity enhancement body 29 is spaced apart from the thermocouple pair 23 and the heating resistor 28, that is, the other regions on the central support film 241 except for the thermocouple pair 23 and the heating resistor 28 extending into the central support film 241 are used to set the heat capacity enhancement body 29, and the heat capacity enhancement body 29 does not participate in the electrical connection circuit of the thermopile 22 and the heating resistor 28, and will not affect the electrical performance of the thermopile 22 and the heating resistor 28. The heat capacity enhancement body 29 located in the central area of ​​the central support film 241 can increase the heat capacity of the hot end 234 in the thermopile 22 to a certain extent, accumulate more heat to increase the temperature difference between the cold end 233 and the hot end 234 in the thermopile 22, and thus improve the voltage response performance of the thermopile 22. In this embodiment, the material of the heat capacity enhancement body 29 is polysilicon, which can be manufactured simultaneously with the polysilicon thermocouple bars (including the first conductive type polysilicon thermocouple bars 231 and the second conductive type polysilicon thermocouple bars 232), the heating resistor 28 and the polysilicon gate in the integrated circuit 3 through the CMOS standard process. In other embodiments, the heat capacity enhancement body 29 can be other suitable materials.

[0126] As an example, the arrangement of the plurality of nanopores 7 includes at least one of a rectangular array arrangement and a staggered array arrangement. Different arrangements have different effects on enhancing the infrared absorption efficiency. Fig.14, showing a schematic diagram of a nanopore array structure in which square nanopores are arranged in a rectangular array. In this embodiment, the plurality of nanopores are arranged in a rectangular array, which can ensure the structural consistency of the membrane layer having a plurality of nanopore portions and can ensure the yield. In other embodiments, the plurality of nanopores are arranged in a staggered array, for example, see Fig.15 , showing a schematic diagram of a nanopore array structure in which regular hexagonal nanopores are arranged in a staggered array. When a plurality of the nanopores are arranged in a staggered array, the density utilization rate can be improved, more nanopores are formed per unit density, and the infrared absorption effect is improved.

[0127] As an example, the nanopore 7 is a regular polygon, and the side length of the nanopore ( Fig.14 c) is in the range of 0.1 μm to 5 μm, preferably 0.25 μm to 4 μm, and the spacing between two adjacent nanopores 7 ( Fig.14 d) is in the range of 0.1 μm to 5 μm, preferably 0.25 μm to 4 μm, and the ratio of the side length of the nanopore 7 to the spacing between two adjacent nanopores 7 ( Fig.14 The c / d) range is 1:50 to 50:1, preferably 1:1 to 8:1, please refer to Fig.16 , displayed as Fig.14The enlarged structural diagram of the II region in the middle, it should be noted that, due to the different shapes and arrangements of the nanopores 7 in different embodiments, the spacing between the obliquely upward nanopores 7 will be quite different, therefore, the spacing between two adjacent nanopores 7 here refers to the spacing between the two nanopores 7 in the horizontal direction and the spacing between the two nanopores 7 in the vertical direction. That is, the opening of the nanopore 7 can be in the shape of a regular triangle, square, regular pentagon, regular hexagon, etc., whose angles can be bisected by 360° (regular polygon) or in the shape of a circle (when the nanopore is a circle, the diameter of the nanopore is within the above-mentioned side length range), so that it can ensure that sufficiently dense nanopores 7 are formed in the film layer to improve the infrared absorption efficiency, and the edge of the nanopore 7 is in a certain proportional relationship with the gap between two adjacent nanopores 7, and the infrared absorption effect of the infrared detector surface is adjusted and controlled by adjusting the ratio of the side length of the nanopore 7 to the spacing between adjacent nanopores 7. In addition, the spacing between adjacent nanopores 7 needs to be strictly maintained within the above range. If the spacing is too small, the photoresist adhesion will be poor, and it will be easy to separate from the surface of the passivation layer 5, affecting the structure and morphology of the nanopores 7. If the spacing is too large, the number of nanopores 7 formed per unit area will be limited, affecting the infrared absorption effect. In this embodiment, the side length or diameter of the nanopore 7 is 2μm, the spacing between two adjacent nanopores 7 is 0.5μm, and the ratio of the side length of the nanopore 7 to the spacing between two adjacent nanopores 7 is 4:1. The above parameter settings can achieve the best infrared absorption effect. Of course, in other embodiments, the opening of the nanopore 7 can also be rectangular and elliptical, etc., but the arrangement of the nanopores 7 needs to be reasonably designed to achieve the ideal infrared absorption effect.

[0128] For details, please refer to Fig.17 , showing a schematic diagram of the infrared absorption effect of the infrared detector and a general infrared detector, and showing a data curve of the absorption efficiency of different infrared detectors for different wavelengths, wherein Curve A shows the curve of the absorption rate of the infrared detector with nanopores as a function of wavelength, and Curve B shows the curve of the absorption rate of the infrared detector without nanopores as a function of wavelength. It can be seen from the figure that under reasonable test error conditions, the infrared absorption rate of the infrared detector with nanopores at different wavelengths is higher than the infrared absorption rate without nanopores at the same wavelength. When tested at 35℃~42℃, the absorption efficiency of the infrared detector with nanopores for infrared light with a wavelength of 9.2μm~9.4μm is as high as 94.97% ( Fig.17The area shown in the dashed box in the middle), while under the same conditions, the absorption rate of the infrared detector without nanopores is only 66.05%, and the difference in absorption rate is about 30%, indicating that the absorption rate of infrared light of this infrared detector has been significantly improved compared with that of general infrared detectors. From a structural perspective, the multiple nanopore structures improve the infrared absorption efficiency of the infrared detector on the one hand, and on the other hand, the production of nanopores greatly reduces the thickness of the film layer on the surface of the infrared detector, reduces the thermal conductivity of the film layer, thereby reducing heat loss and further improving the performance of the infrared detector.

[0129] The infrared detector of this embodiment includes a MEMS array and an integrated circuit located at the periphery of the MEMS array. The overall structure is simple and the signal-to-noise ratio is convenient to adjust. Among them, there is an infrared enhancement structure composed of multiple nanoholes above the MEMS array, which can effectively improve the infrared absorption efficiency of the infrared detector, reduce the thermal conductivity of the film layer and reduce heat loss. The infrared absorption rate can be effectively regulated by adjusting the arrangement, shape and size of the nanoholes and the thermocouple structure and arrangement of the temperature difference thermal pile in the MEMS array. More importantly, the temperature difference thermal pile and infrared enhanced absorption structure in the MEMS array are fully compatible with CMOS technology and will not increase any additional cost.

[0130] Embodiment 2

[0131] This embodiment provides an infrared detector. The difference between this embodiment and the first embodiment is that the extension degree of the thermocouple pair above the central support film is different. In the first embodiment, the thermocouple pair only extends to the edge area above the central support film, while in this embodiment, the thermocouple pair extends to the central area above the central support film. Figure 1 , showing the infrared detector, including a substrate 1, a conductive interconnection layer 4, a passivation layer 5, a pad hole 6 and a plurality of nanoholes 7.

[0132] As an example, see Fig.18 , which is a schematic diagram of the structure of the thermal pile pixel of this embodiment, wherein the hot ends 234 of the plurality of groups of the thermocouple pairs 23 are all located above the central support film, and the cantilever beam 242 includes a first cantilever region 242a and a second cantilever region 242b, wherein the first cantilever region 242a and the second cantilever region 242b are arranged on both sides of the central axis of the auxiliary release groove 27 in the horizontal extension direction, and the hot ends 234 of all the thermocouple pairs 23 extending through the first cantilever region 242a are located on a first straight line ( Fig.18 The hot ends 234 of all the thermocouple pairs 23 extending through the second cantilever region 242b are located on the second straight line ( Fig.18It should be noted that when the thermocouple strip is actually manufactured, the hot ends of the thermocouple pair are not completely located on the same straight line due to slight errors caused by equipment and process limitations. The first straight line and the second straight line can be regarded as ultra-fine strip areas.

[0133] Specifically, compared with the arrangement of the thermocouple pairs in Example 1, the hot ends of all the thermocouple pairs in this embodiment continue to extend toward the central area of ​​the central support membrane on the basis of the structure of Example 1, until they extend as far as possible from the extension path of each thermocouple pair to the most central area of ​​the central support membrane, which correspondingly leads to a reduction in the heat capacity enhancement body. In this embodiment, due to the number (four) and arrangement of the cantilever beams, all the hot ends form a "cross" area (equivalent to the angle formed by the intersection of the first straight line and the second straight line being a right angle), and the heat capacity enhancement body and the heating resistor are both located inside the "cross" area. Although the resistance value of the temperature difference thermal stack will increase with this arrangement, due to the increase in the temperature of the hot end located at the most central point, the temperature difference between the cold end and the hot end also increases accordingly, thereby greatly increasing the corresponding voltage, thereby obtaining an infrared detector structure with better infrared absorption effect. In other embodiments, the angle formed by the intersection of the first straight line and the second straight line can also be an acute angle or an obtuse angle, and the specific value of the angle varies with the number of the cantilever beams and the arrangement of the thermocouple pairs (such as the extent to which the thermocouple pairs extend above the central support membrane).

[0134] Embodiment 3

[0135] This embodiment provides an infrared detector, which is different from the first and second embodiments in that some of the thermocouple pairs in this embodiment do not extend into the central support film, and the hot ends of these thermocouple pairs are located on the cantilever beam, while all of the thermocouple pairs in the first and second embodiments extend into the central support film, so that the hot ends of all the thermocouple pairs are located on the central support film. Figure 1 , showing the infrared detector, including a substrate 1, a conductive interconnection layer 4, a passivation layer 5, a pad hole 6 and a plurality of nanoholes 7.

[0136] As an example, when the thermocouple pair 23 extends from the support frame 25 via the cantilever beam 242 toward the central support film 241 , at least a portion of the thermocouple pair 23 extends onto the central support film 241 . In this embodiment, a portion of the thermocouple pair 23 does not extend onto the central support film 241 .

[0137] As an example, see Fig.19, which is a schematic diagram of the top view of the structure of the thermal pile pixel of this embodiment, wherein the temperature difference thermal pile 22 includes at least one group of first thermocouple pairs 23a and at least one group of second thermocouple pairs 23b, the cantilever beam 242 includes a central cantilever area 242a and edge cantilever areas 242b located on both sides of the central cantilever area 242a, and the part of the auxiliary release groove 27 located in the cantilever beam 242 is located in the central cantilever area 242a. That is, since the auxiliary release groove 27 extends from the cantilever beam 242 to the central support film 241 in the horizontal direction, a portion of the auxiliary release groove 27 is located in the cantilever beam 242, and the remaining portion of the auxiliary release groove 27 is located in the central support film 241. When the cantilever beam 242 is divided into the central cantilever area 242a and the edge cantilever area 242b as described above, the portion of the auxiliary release groove 27 located in the cantilever beam 242 is located in the central cantilever area 242a rather than in the edge cantilever area 242b.

[0138] Further, the first thermocouple pair 23a extends through the central cantilever region 242a and the hot end 234a of the first thermocouple pair is located on the side of the auxiliary release groove 27 facing the support frame 25, and the hot end 234a of the first thermocouple pair 23a is located on a straight line ( Fig.19 The second thermocouple pair 23b extends through the edge cantilever region 242b and the hot end 234b of the second thermocouple pair is located on the central support film 241. The second thermocouple pair is located at a width ( Fig.19 w1) is equal to the width of the first thermocouple pair ( Fig.19 w), the second thermocouple pair is located at the width ( Fig.19It should be noted that the extension direction of the thermocouple pair is the length direction, and the direction perpendicular to the extension direction of the thermocouple pair is the width direction. In addition, since each thermocouple pair is composed of a first conductive type polysilicon thermocouple strip and a second conductive type polysilicon thermocouple strip, in actual manufacturing, in order to ensure the stability of device performance, the width of each thermocouple strip should be kept as the same as possible and the thermocouple strips should be arranged at equal intervals, and due to the need for miniaturization of the device volume, the distance between two adjacent thermocouple strips is reduced as much as possible (much smaller than the width of the thermocouple strip) so that a sufficient number of thermocouple strips can be integrated on a limited cantilever beam to form a temperature difference thermal pile. Therefore, the width of the first thermocouple pair mentioned above is equal to or different from the width of the second thermocouple pair on different sides of the straight line, which can be regarded as the result of the numerical relationship between the width of the thermocouple strip constituting the first thermocouple pair and the width of the thermocouple strip constituting the second thermocouple pair, that is, the width of the thermocouple strip constituting the second thermocouple pair on the side of the straight line away from the central support film is equal to the width of the thermocouple strip constituting the first thermocouple pair, and the width of the thermocouple strip constituting the second thermocouple pair on the side of the straight line toward the central support film is greater than the width of the thermocouple strip constituting the first thermocouple pair.

[0139] Specifically, multiple groups of thermocouple pairs extend on the same cantilever beam, part of the thermocouple pairs (the first thermocouple pairs) extend through the middle part of the cantilever beam and the remaining part of the thermocouple pairs (the second thermocouple pairs) extend through the edge part of the cantilever beam, the first thermocouple pair only extends to the side of the auxiliary release groove facing the support frame and then stops extending, so that its hot end is located on the cantilever beam instead of on the central support film, the length of the first thermocouple pair is shortened relative to the length of the second thermocouple pair, the hot ends of all the first thermocouple pairs are located on the same straight line and this straight line is perpendicular to the horizontal extension direction of the cantilever beam, the straight line divides the cantilever beam into two areas, and the first area includes both the first thermocouple pair and the second thermocouple pair. A portion of the pair, the widths of the first thermocouple pair and the second thermocouple pair to this portion are equal, in the second region, since the first thermocouple pair no longer extends toward the central support film, the position on the cantilever beam originally used for the first thermocouple pair to continue to extend is used to accommodate the second thermocouple pair, resulting in an increase in the width of the second thermocouple pair in this region, while the settings of the heating resistor and the heat capacity enhancement body remain unchanged, so that while the hot end of the second thermocouple pair ensures a high voltage response, the width of the second thermocouple pair is increased to reduce resistance, and although the hot end of the first thermocouple pair has a lower temperature, resulting in a decrease in temperature difference and a corresponding decrease in voltage, its length becomes shorter and the corresponding resistance value is greatly reduced, which can still ensure the signal-to-noise ratio of the infrared detector to a certain extent.

[0140] Embodiment 4

[0141] This embodiment provides a method for manufacturing an infrared detector, which is used to manufacture the infrared detector structure described in Embodiments 1 to 3 or other infrared detector structures. Fig. 20 , which is a flowchart of the steps of the production method, comprising the following steps:

[0142] S1: providing a substrate, wherein the substrate comprises a first region and a second region located outside the first region;

[0143] S2: forming a MEMS array and an integrated circuit on the substrate, wherein the MEMS array is located in the first area, and the integrated circuit is located in the second area;

[0144] S3: sequentially forming a conductive interconnect layer and a passivation layer on the substrate, wherein the conductive interconnect layer covers the MEMS array and the integrated circuit, the conductive interconnect layer comprises a dielectric layer, at least one metal layer embedded in the dielectric layer, and a pad located on the dielectric layer, and the passivation layer covers the conductive interconnect layer;

[0145] S4: forming at least one pad hole and a plurality of nanoholes for enhancing infrared absorption, wherein the pad hole opens from the passivation layer and extends downward to expose at least a portion of the pad, the plurality of nanoholes are located above the MEMS array and the plurality of nanoholes are arranged at intervals, and the nanoholes open from the passivation layer and extend downward into the dielectric layer.

[0146] See also Fig.21 , perform step S1, provide a substrate 1, the substrate 1 includes a first region 11 and a second region 12 located outside the first region 11, the material of the substrate 1 can be selected from silicon, germanium, germanium silicon, III-V group compounds or other suitable semiconductor materials. In this embodiment, the substrate 1 is selected from <100> The silicon wafer with crystal orientation should be cleaned and dried before starting to make other structures to avoid contamination.

[0147] See also Figure 21 to Figure 24 , perform step S2 to form a MEMS array 2 and an integrated circuit 3 on the substrate 1 , wherein the MEMS array 2 is located in the first area 11 , and the integrated circuit 3 is located in the second area 12 .

[0148] As an example, further, step S2 includes the following steps:

[0149] like Fig.21 As shown, an N well 121 and a P well 122 are sequentially formed in the substrate 1 through conventional semiconductor processes such as epitaxial growth, photoresist patterning, ion implantation, and annealing. The N well 121 and the P well 122 are used for the subsequent manufacture of NMOS and PMOS tubes of the integrated circuit 3.

[0150] like Fig. 22 As shown, a first isolation structure 111 and a second isolation structure 123 are formed in the substrate 1, wherein the first isolation structure 111 and the second isolation structure 123 both start from the top surface of the substrate 1 and extend downward, and the bottom surfaces of the first isolation structure 111 and the second isolation structure 123 are both higher than the bottom surface of the substrate 1, wherein the first isolation structure 111 includes a structure located in the first region 11, and the second isolation structure 123 is located in the second region 12.

[0151] As an example, the first isolation structure 111 and the second isolation structure 123 both include a shallow trench isolation structure (STI), and the specific formation steps include: first, forming an isolation oxide layer, a silicon nitride layer and a photoresist layer on the surface of the substrate 1 in sequence, and patterning the photoresist layer to form an etching window, and then etching the substrate 1 based on the etching window to obtain an STI groove, secondly, cleaning the inner wall of the groove in sequence, thermally oxidizing the inner wall of the groove to form a silicon oxide layer, and filling the groove with oxide by chemical vapor deposition (CVD) or other suitable methods, and finally, performing oxide planarization and removing the silicon nitride layer by chemical mechanical polishing (CMP) to obtain the first isolation structure 111 and the second isolation structure 123.

[0152] Specifically, the first isolation structure 111 serves as the first support layer and insulation layer of the thermopile 22 , and the second isolation structure 123 is used to isolate the N-well 121 from the P-well 122 .

[0153] like Fig.23 As shown, a first conductive type polysilicon layer is formed on the semiconductor substrate 1 and patterned to obtain a first conductive type polysilicon thermocouple strip 231 located on the first isolation structure 111 and a first conductive type polysilicon gate 13 located in the second region 12, and a second conductive type polysilicon layer is formed on the substrate 1 and patterned to obtain a second conductive type polysilicon thermocouple strip 232 located on the first isolation structure 111 and a second conductive type polysilicon gate 14 located in the second region 12.

[0154] As an example, a silicon dioxide layer is first grown on the surface of the substrate 1 by thermal oxidation as a gate dielectric layer, and then polysilicon is deposited by low pressure chemical vapor deposition (LPCVD), and then different types of doping are performed on different regions of the polysilicon in turn; and the polysilicon film layer is photolithographically and etched to simultaneously obtain a polysilicon gate structure (including the first conductive type polysilicon gate 13, the second conductive type polysilicon gate 14) and polysilicon thermocouple bars (including the first conductive type polysilicon thermocouple bar 231, the second conductive type polysilicon thermocouple bar 232).

[0155] In this embodiment, the heating resistor 28 ( Fig.23 (not shown) and the heat capacity enhancement body 29 ( Fig.23 not shown).

[0156] like Fig.24 As shown, the PMOS transistor and the NMOS transistor in the integrated circuit 3 are prepared by standard integrated circuit processes such as lightly doped drain, sidewall preparation, source and drain injection, etc.

[0157] See also Figure 25-26 , execute step S3, and sequentially form a conductive interconnect layer 4 and a passivation layer 5 on the substrate 1, wherein the conductive interconnect layer 4 covers the MEMS array 2 and the integrated circuit 3, and the conductive interconnect layer 4 includes a dielectric layer 41, at least one metal layer 42 embedded in the dielectric layer 41, and a pad 43 located on the dielectric layer 41, and the passivation layer 5 covers the conductive interconnect layer 4.

[0158] Specifically, the conductive interconnection layer 4 includes at least one metal layer 42. In this embodiment, the conductive interconnection layer 4 is prepared by a standard 1P4M process, so the conductive interconnection layer 4 includes four metal layers, wherein the metal layer at the bottom is the first metal layer 422, which is electrically connected to the MEMS array 2 sensor and the integrated circuit 3 through a metal plug 421 to achieve electrical connection between the MEMS array 2 sensor and the integrated circuit 3, so that data reading control can be performed, and two adjacent metal layers are also electrically connected through the metal plug 421. In this embodiment, the first metal layer 422 also includes a hot end metal (for realizing hot end connection of two adjacent thermocouple strips), a cold end metal (for realizing cold end connection of two adjacent thermocouple strips) and a connecting metal for realizing electrical connection between the MEMS array 2 sensor and the integrated circuit 3.

[0159] The formation process of the conductive interconnect layer 4 and the passivation layer 5 is described below by taking an example:

[0160] like Fig.25 As shown, the first dielectric layer 411, the first through hole (for forming a metal plug 421) and the first metal layer 422 (for realizing electrical connection between metal interconnection and thermocouple strips) are prepared by standard 1P4M processes such as contact hole formation process and local interconnection process, and at this time, the output end of each pixel structure is connected to the integrated circuit 3 through the first metal layer 422.

[0161] like Fig.26As shown, the second dielectric layer, the second through hole, the second metal, the third dielectric layer, the third through hole, the third metal, the fourth dielectric layer, the fourth through hole, the fourth metal layer and the passivation layer 5 are prepared by the standard 1P4M process, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer constitute the dielectric layer 41, the dielectric layer 41 and the first metal layer 422, the second metal layer and the third metal layer together constitute the conductive interconnect layer 4, and the fourth metal layer serves as the pad (PAD) 43.

[0162] See also Fig. 27 , execute step S4 to form at least one pad hole 6 and a plurality of nanoholes 7 for enhancing infrared absorption, wherein the pad hole 6 opens from the passivation layer 5 and extends downward to expose at least a portion of the pad 43, the plurality of nanoholes 7 are located above the MEMS array 2 and the plurality of nanoholes 7 are arranged at intervals, and the nanoholes 7 open from the passivation layer 5 and extend downward to the dielectric layer 41.

[0163] It should be noted that the nanopores of this embodiment are mainly prepared by PAD etching plates at the same time, which is fully compatible with standard CMOS processes and has no additional costs. While the surface passivation layer is photolithographically etched to expose the PAD structure (for forming the pad hole), the dielectric layer is photolithographically etched and etched (for forming the nanopores). In the actual etching process, the passivation layer on the surface of the PAD part is etched until the upper surface of the pad is exposed. In order to ensure that the passivation layer (such as the TiN layer) on the pad is etched cleanly, coupled with the etching loading effect, the actual etching depth of the nanopore part will be deeper than the depth of the pad hole, which guarantees the absorption rate of the nanopore to a certain extent, and at the same time reduces the effective film thickness of the infrared detector, reduces the thermal conductivity of the film layer, thereby reducing heat loss, and further improving the performance of the device response.

[0164] As an example, see Figure 28-29 The manufacturing method further includes the steps of forming the main release groove 26, the auxiliary release groove 27 and the cavity 21, including the following steps:

[0165] like Fig.28 As shown, a photoresist layer ( Fig.28 (not shown) and patterning the photoresist layer to obtain a plurality of etching windows, etching is performed based on the etching windows to form various release grooves (including the main release groove 26 and the auxiliary release groove 27), and the etching depth is required to completely expose the substrate 1. The deeper the etching depth, the better the subsequent wet etching effect and the faster the rate;

[0166] like Fig.29As shown, through the main release groove 26 and the auxiliary release groove 27 ( Fig.29 An etching solution is injected (not shown) to corrode the portion of the substrate 1 located below the first isolation structure 111 to obtain the cavity 21.

[0167] Specifically, the cavity 21 realizes thermal isolation between the surface structure (the suspension layer and the thermopile, heating resistor and other structures located above the suspension layer) and the substrate 1, reducing heat loss and thus ensuring good voltage response performance. In this embodiment, an anisotropic etching solution (alkaline solution such as TMAH tetramethylammonium hydroxide and potassium hydroxide solution) is injected into each release groove, so that the substrate 1 under the thermopile is corroded to form a cavity, achieving thermal isolation, thereby obtaining a thermopile pixel in the MEMS array.

[0168] As an example, during wet etching, a silicon oxide layer needs to be formed on the back side of the substrate 1 as a back side protective layer to prevent the back side of the substrate 1 from being damaged, thereby ensuring the structural stability of the infrared detector.

[0169] The infrared detector manufacturing method of the present embodiment can realize the simultaneous manufacturing of the MEMS array and the integrated circuit in the infrared detector while realizing the simultaneous manufacturing of the nanohole and the pad hole. The entire manufacturing step is fully compatible with the CMOS process, and the manufacturing of the infrared absorption enhancement structure in the infrared detector is realized without adding any additional cost. The simple structure can realize low-cost mass production, which effectively improves the competitiveness of the infrared detector.

[0170] In summary, the infrared detector of the present invention includes a MEMS array and an integrated circuit located at the periphery of the MEMS array. The overall structure is simple and the signal-to-noise ratio is convenient to adjust. Among them, the upper part of the MEMS array has an infrared enhancement structure composed of multiple nanoholes, which can effectively improve the infrared absorption efficiency of the infrared detector, reduce the thermal conductivity of the film layer and reduce heat loss, and by adjusting the arrangement, shape and size of the nanoholes and the thermocouple structure and arrangement of the temperature difference heat pile in the MEMS array, the infrared absorption rate can be effectively regulated. More importantly, the temperature difference heat pile and the infrared enhanced absorption structure in the MEMS array are fully compatible with the CMOS process and will not increase any additional costs. The infrared detector manufacturing method of the present invention can realize the simultaneous manufacturing of the MEMS array and the integrated circuit in the infrared detector while realizing the simultaneous manufacturing of the nanoholes and the pad holes. The entire manufacturing step is fully compatible with the CMOS process. The infrared absorption enhancement structure in the infrared detector is realized without adding any additional costs. The simple structure can realize low-cost mass production, which effectively improves the competitiveness of the infrared detector. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0171] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An infrared detector, characterized in that: include: A substrate having a MEMS array and an integrated circuit located at the periphery of the MEMS array; A conductive interconnect layer and a passivation layer, wherein the conductive interconnect layer is located above the substrate and covers the MEMS array and the integrated circuit, the conductive interconnect layer comprises a dielectric layer, at least one metal layer embedded in the dielectric layer, and a pad located on the dielectric layer, the pad is electrically connected to the metal layer and is located above the integrated circuit, and the passivation layer is located above the conductive interconnect layer and covers the pad; At least one pad hole and a plurality of nanoholes for enhancing infrared absorption, wherein the pad hole opens from the passivation layer and extends downward to expose at least a portion of the pad, the plurality of nanoholes are located above the MEMS array and the plurality of nanoholes are arranged at intervals, and the nanoholes open from the passivation layer and extend downward into the dielectric layer.

2. The infrared detector according to claim 1, characterized in that: The arrangement of the plurality of nanopores includes at least one of a rectangular array arrangement and a staggered array arrangement.

3. The infrared detector according to claim 1 or 2, characterized in that: The nanopore is a regular polygon, and the side length of the nanopore ranges from 0.1 μm to 5 μm, the spacing between two adjacent nanopores ranges from 0.1 μm to 5 μm, and the ratio of the side length of the nanopore to the spacing between two adjacent nanopores ranges from 1:50 to 50:

1.

4. The infrared detector according to claim 1, characterized in that: The MEMS array includes a plurality of thermal stack pixels arranged in an array, each of the thermal stack pixels includes a cavity and a thermoelectric pile, the cavity is buried in the substrate, a portion of the substrate located above the cavity constitutes a suspension layer, the thermoelectric pile is located above the substrate and the thermoelectric pile extends onto the suspension layer.

5. The infrared detector according to claim 4, characterized in that: The portion of the substrate surrounding the cavity forms a support frame, the suspension layer includes a central support film and a plurality of cantilever beams arranged around the central support film, and the cantilever beams are connected between the support frame and the central support film.

6. The infrared detector according to claim 5, characterized in that: Each of the thermal stack pixels further comprises a plurality of main release grooves, wherein the main release grooves are located between two adjacent cantilever beams and the main release grooves vertically penetrate the suspension layer and communicate with the cavity.

7. The infrared detector according to claim 6, characterized in that: An angle is formed between a surface of the main release groove adjacent to the support frame and a surface of the main release groove adjacent to the cantilever beam, and the angle includes at least one of an arc angle, an obtuse angle and a right angle.

8. The infrared detector according to claim 5, characterized in that: Each of the hot end pixels also includes a plurality of auxiliary release grooves, each of which vertically penetrates the suspension layer and communicates with the cavity. The auxiliary release grooves extend horizontally from the cantilever beam to the central support film, and the extension direction of the auxiliary release grooves is the same as the extension direction of the cantilever beam.

9. The infrared detector according to claim 8, characterized in that: The temperature difference thermal stack includes a plurality of sets of spaced-apart thermocouple pairs, wherein the thermocouple pairs extend from the support frame via the cantilever beam toward the central support film, and at least a portion of the thermocouple pairs extend onto the central support film. The thermocouple pairs include a cold end and a hot end that are relatively disposed, and the cold end is located on the support frame.

10. The infrared detector according to claim 9, characterized in that: The hot ends of multiple groups of thermocouple pairs are all located above the central supporting film, the cantilever beam includes a first cantilever region and a second cantilever region, the first cantilever region and the second cantilever region are arranged on both sides of the central axis of the horizontal extension direction of the auxiliary release groove, the hot ends of all thermocouple pairs extending through the first cantilever region are located on a first straight line, and the hot ends of all thermocouple pairs extending through the second cantilever region are located on a second straight line, and the first straight line coincides with or intersects with the second straight line.

11. The infrared detector according to claim 9, characterized in that: The thermocouple comprises at least one first thermocouple pair and at least one second thermocouple pair, the cantilever beam comprises a central cantilever region and edge cantilever regions located on both sides of the central cantilever region, and the portion of the auxiliary release groove located in the cantilever beam is located in the central cantilever region; The first thermocouple pair extends through the central cantilever area and the hot end of the first thermocouple pair is located on the side of the auxiliary release groove facing the support frame, the hot end of the first thermocouple pair is located on a straight line and the straight line is perpendicular to the extension direction of the cantilever beam, the second thermocouple pair extends through the edge cantilever area and the hot end of the second thermocouple pair is located on the central support film, the width of the second thermocouple pair on the side of the straight line away from the central support film is equal to the width of the first thermocouple pair, and the width of the second thermocouple pair on the side of the straight line facing the central support film is greater than the width of the first thermocouple pair.

12. The infrared detector according to claim 9, characterized in that: Each of the thermal pile pixels further comprises a plurality of heating resistors arranged at intervals, and the plurality of heating resistors are located on the central supporting film and are sequentially connected in series.

13. The infrared detector according to claim 12, characterized in that: Each of the thermal pile pixels further comprises a heat capacity enhancement body, which is located on the central support film and spaced apart from the thermocouple pair and the heating resistor.

14. A method for manufacturing an infrared detector, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a first region and a second region located outside the first region; forming a MEMS array and an integrated circuit on the substrate, wherein the MEMS array is located in the first area, and the integrated circuit is located in the second area; forming a conductive interconnect layer and a passivation layer on the substrate in sequence, wherein the conductive interconnect layer covers the MEMS array and the integrated circuit, the conductive interconnect layer comprises a dielectric layer, at least one metal layer embedded in the dielectric layer, and a pad located on the dielectric layer, and the passivation layer covers the conductive interconnect layer; At least one pad hole and a plurality of nanoholes for enhancing infrared absorption are formed, wherein the pad hole opens from the passivation layer and extends downward to expose at least a portion of the pad, the plurality of nanoholes are located above the MEMS array and the plurality of nanoholes are arranged at intervals, and the nanoholes open from the passivation layer and extend downward into the dielectric layer.

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