Resistance switching element and manufacturing method thereof

Abstract

The invention discloses a resistance switching element and a manufacturing method thereof. The resistance switching element comprises a substrate; a first dielectric layer disposed on the substrate; a conductive via disposed in the first dielectric layer; and a resistance switching structure embedded in an upper portion of the conductive via, where the resistance switching structure includes a top electrode layer having a lower sharp corner, a resistance switching material layer disposed around the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistance switching material layer and the upper portion of the conductive via.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a resistance switching element and a manufacturing method thereof. Background Art

[0002] Resistive random access memory (RRAM) is a memory structure that includes an array of RRAM cells, each of which uses resistance value rather than charge to store a bit of data. In particular, each RRAM cell includes a layer of resistance-switching material whose resistance can be adjusted to represent a logical "0" or a logical "1".

[0003] At advanced technology nodes, feature sizes are scaled down, and the size of memory elements is scaled accordingly. However, the scaling of RRAM elements is limited due to the "forming" operation, in which a high voltage is applied to the RRAM element to generate a conductive path in the resistance-switching material layer.

[0004] Since the RRAM element is fabricated during the back-end metal fabrication process, it will cause a loading effect from the memory area to the logic circuit area, increasing the risk of Cu residue or via open in the transition area between the memory area and the logic circuit area. In addition, an improved RRAM structure is also needed that can form a stronger electric field during operation to improve the performance of the "forming" process. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved resistance switching element and a manufacturing method thereof to solve the deficiencies or shortcomings of the prior art.

[0006] On one hand, the present invention provides a resistance switching element, comprising a substrate; a first dielectric layer disposed on the substrate; a conductive through hole disposed in the first dielectric layer; and a resistance switching structure embedded in the upper portion of the conductive through hole, wherein the resistance switching structure comprises a top electrode layer having a lower sharp corner, a resistance switching material layer covering the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistance switching material layer and the upper portion of the conductive through hole.

[0007] According to an embodiment of the present invention, the lower sharp angle is a right-angled sharp angle or an obtuse-angled sharp angle.

[0008] According to an embodiment of the present invention, the resistance switching structure has an L-shaped cross-sectional profile.

[0009] According to an embodiment of the present invention, the resistance switching structure has a sawtooth cross-sectional profile.

[0010] According to an embodiment of the present invention, a top surface of the resistance switching structure is coplanar with a top surface of the first dielectric layer and a top surface of the conductive via.

[0011] According to an embodiment of the present invention, the sidewall surface of the resistance switching structure is covered with a spacer.

[0012] According to an embodiment of the present invention, the spacer comprises silicon nitride.

[0013] According to an embodiment of the present invention, the resistance switching element further includes: a pad metal structure embedded in the first dielectric layer and connected to the resistance switching structure, wherein the pad metal structure is in direct contact with the spacer and the top electrode layer, and wherein the top surface of the pad metal structure is coplanar with the top surface of the first dielectric layer.

[0014] According to an embodiment of the present invention, the conductive via comprises tungsten.

[0015] According to an embodiment of the present invention, the bottom electrode includes TaN, TiN, Pt, Ir, Ru or W.

[0016] According to an embodiment of the present invention, the top electrode comprises TiN, TaN, Pt, Ir or W.

[0017] According to an embodiment of the present invention, the resistance switching layer includes hafnium oxide, tantalum oxide or titanium.

[0018] According to an embodiment of the present invention, the resistance switching element further includes: a second dielectric layer located on the top electrode layer; and a contact penetrating the second dielectric layer and electrically connected to the top electrode layer.

[0019] On the other hand, the present invention provides a method for forming a resistance switching element, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a conductive through hole in the first dielectric layer; and forming a resistance switching structure embedded in the upper portion of the conductive through hole, wherein the resistance switching structure comprises a top electrode layer having a lower pointed corner, a resistance switching material layer covering the lower pointed corner of the top electrode layer, and a bottom electrode layer disposed between the resistance switching material layer and the upper portion of the conductive through hole.

[0020] According to an embodiment of the present invention, the lower angle is a right angle or an obtuse angle.

[0021] According to an embodiment of the present invention, the resistance switching structure has an L-shaped cross-sectional profile.

[0022] According to an embodiment of the present invention, the resistance switching structure has a sawtooth cross-sectional profile.

[0023] According to an embodiment of the present invention, a top surface of the resistance switching structure is coplanar with a top surface of the first dielectric layer and a top surface of the conductive via.

[0024] According to an embodiment of the present invention, the sidewall surface of the resistance switching structure is covered with a spacer.

[0025] According to an embodiment of the present invention, the method further includes: forming a pad metal structure embedded in the first dielectric layer and connected to the resistance switching structure, wherein the pad metal structure is in direct contact with the spacer and the top electrode layer, and wherein the top surface of the pad metal structure is coplanar with the top surface of the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 13 A schematic diagram of a method for forming a resistance switching element according to an embodiment of the present invention;

[0027] Figures 14 to 20 A schematic diagram of a method for forming a resistance switching element according to another embodiment of the present invention;

[0028] Figure 21 to Figure 27 It is a schematic diagram of a method for forming a resistance switching element according to yet another embodiment of the present invention.

[0029] Explanation of symbols

[0030] 1 Resistor switching element

[0031] 100 Base

[0032] 102 Conductive structure

[0033] 110 first dielectric layer

[0034] 111 Through hole

[0035] 112 Metal Layer

[0036] 112a Conductive via

[0037] 114, 118 Etch stop layer

[0038] 120 second dielectric layer

[0039] 150 Planarization layer

[0040] 200 stacking structure

[0041] 210 bottom electrode layer

[0042] 211 Tantalum Oxide Layer

[0043] 212 Hafnium oxide layer

[0044] 220 resistance switching layer

[0045] 230 Top electrode layer

[0046] 231 Ir layer

[0047] 232 TiN layer

[0048] IM, IMP metal layer

[0049] IS circuit trench structure

[0050] LR memory area

[0051] MR Memory Area

[0052] OPV, OPT opening

[0053] PR, PR1, PR2 Photoresist pattern

[0054] PR1a Island pattern

[0055] R Recessed area

[0056] RS resistor switching structure

[0057] S1~S4 top surface

[0058] SP Spacer

[0059] T, T1~T4 groove

[0060] TS1, TS2 sidewall

[0061] TS3 Bottom

[0062] TA, TA1 lower corner

[0063] UM, UMP contact structure

[0064] VP Through Hole

[0065] θ Angle DETAILED DESCRIPTION

[0066] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0067] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0068] See also Figures 1 to 13 , which is a schematic diagram of a method for forming a resistance switching element according to an embodiment of the present invention. Figure 1As shown, first, a substrate 100 is provided, for example, a silicon substrate. According to an embodiment of the present invention, the substrate 100 has a memory region MR and a logic circuit region LR. At least one conductive structure 102, for example, a metal layer or a metal pad, is formed on the substrate 100 in the memory region MR, but is not limited thereto. According to an embodiment of the present invention, for example, the conductive structure 102 can be a damascene copper structure. Those familiar with the art should understand that the substrate 100 can also include circuit elements, dielectric layers, and internal connection structures, etc., which are not shown in the figure for simplicity of description.

[0069] Next, a first dielectric layer 110 is formed on the substrate 100 to cover the conductive structure 102. According to an embodiment of the present invention, for example, the first dielectric layer 110 may include a dielectric material such as silicon oxide. A through hole 111 is formed in the first dielectric layer 110 in the memory region MR using photolithography and etching processes to expose a portion of the conductive structure 102. Next, a metal layer 112, for example, a tungsten metal layer, is deposited on the substrate 100 to fill the through hole 111.

[0070] like Figure 2 As shown, a chemical mechanical polishing (CMP) process is then performed to remove the metal layer 112 outside the through hole 111, leaving only the metal layer 112 inside the through hole 111, thereby forming a conductive through hole 112a. The top surface S1 of the conductive through hole 112a is coplanar with the top surface S2 of the first dielectric layer 110.

[0071] like Figure 3 As shown, a trench T is formed in the upper part of the conductive via 112a and the first dielectric layer 110 by using photolithography and etching processes, including a side wall TS1 formed by the conductive via 112a, a side wall TS2 formed by the first dielectric layer 110, and a bottom surface TS3 formed by the conductive via 112a and the first dielectric layer 110, wherein a lower sharp angle TA is formed between the side wall TS1 and the bottom surface TS3, for example, a right angle or an obtuse angle. According to an embodiment of the present invention, the angle θ between the side wall TS1 and the bottom surface TS3 can be a right angle or an obtuse angle. According to an embodiment of the present invention, the bottom surface TS3 can be a plane or a slightly concave curved surface.

[0072] like Figure 4As shown, a stacked structure 200 is then conformally deposited on the first dielectric layer 110 and in the trench T using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, including a bottom electrode layer 210, a resistance switching layer 220, and a top electrode layer 230. According to an embodiment of the present invention, for example, a top surface of the top electrode layer 230 may form a recessed region R in the trench T. The top electrode layer 230 also has a lower pointed corner TA-1.

[0073] According to an embodiment of the present invention, for example, the bottom electrode layer 210 may include TaN, TiN, Pt, Ir, Ru or W. According to an embodiment of the present invention, for example, the resistance switching layer 220 may include a tantalum oxide layer 221 and a hafnium oxide layer 222. According to an embodiment of the present invention, the resistance switching layer 220 may include hafnium oxide, tantalum oxide or titanium. According to an embodiment of the present invention, for example, the top electrode layer 230 may include an Ir layer 231 and a TiN layer 232. According to an embodiment of the present invention, the top electrode layer 230 may include TiN, TaN, Pt, Ir or W.

[0074] like Figure 5 As shown, then, a trench T2 is formed in the stacked structure 200 and the first dielectric layer 110 next to the conductive via 112a using photolithography and etching processes. According to an embodiment of the present invention, for example, the depth of the trench T2 is approximately equal to the depth of the trench T. According to other embodiments of the present invention, for example, the depth of the trench T2 may be slightly greater than the depth of the trench T. According to an embodiment of the present invention, the stacked structure 200 at the bottom of the trench T2 is completely removed.

[0075] like Figure 6 As shown, then, a chemical mechanical polishing process is performed to remove the stacked structure 200 outside the trench T2, thereby forming a resistance switching structure RS embedded in the upper portion of the conductive via 112a. According to an embodiment of the present invention, the resistance switching structure RS has an L-shaped cross-sectional profile. According to an embodiment of the present invention, the top surface S3 of the resistance switching structure RS is coplanar with the top surface S2 of the first dielectric layer 110 and the top surface S1 of the conductive via 112a.

[0076] like Figure 7 As shown, then, an etch stop layer 114 is deposited all over the substrate 100, so that the etch stop layer 114 is conformally deposited on the first dielectric layer 110 and in the trench T2. The etch stop layer 114 covers the resistance switching structure RS. According to an embodiment of the present invention, for example, the etch stop layer 114 may include a nitrogen-doped silicon carbide (NDC) layer.

[0077] like Figure 8 As shown, then, a trench T3 is formed in the etching stop layer 114 and the first dielectric layer 110 in the logic circuit region LR by using photolithography and etching processes.

[0078] like Fig. 9 As shown, a planarization layer 150 is formed on the etch stop layer 114 and in the trench T3, for example, spin-on glass, etc., but not limited thereto. Then, a photolithography process is performed to form a photoresist pattern PR on the planarization layer 150. According to an embodiment of the present invention, the photoresist pattern PR has an opening OPV in the logic circuit region LR, defining the position of the through hole to be formed in the first dielectric layer 110. According to an embodiment of the present invention, the photoresist pattern PR has an opening OPT in the memory region MR, which is located directly above the trench T2 and is aligned with the trench T2.

[0079] like Fig.10 As shown, the photoresist pattern PR is used as an etching resistance mask to perform an anisotropic dry etching process, and the planarization layer 150 and the first dielectric layer 110 are etched downward through the opening OPV, and the planarization layer 150 and the etching stop layer 114 are etched downward through the opening OPT at the same time, so that a circuit trench structure IS is formed in the logic circuit region LR, and a spacer SP is formed on the sidewall of the trench T2 in the memory region MR. According to an embodiment of the present invention, the spacer SP comprises, for example, silicon nitride.

[0080] like Fig.11 As shown, a metallization process is then performed to fill the circuit trench structure IS of the logic circuit region LR and the trench T2 of the memory region MR with metal layers IM and IMP, respectively, wherein the metal layer IMP and the resistance switching structure RS are separated by a spacer SP. According to an embodiment of the present invention, the metal layer IMP can cover the spacer SP on the resistance switching structure RS and directly contact the top electrode layer 230 of the resistance switching structure RS.

[0081] According to an embodiment of the present invention, the metal layer IMP is used as a pad metal structure, embedded in the first dielectric layer 110 and connected to the resistance switching structure RS. According to an embodiment of the present invention, the metal layer IMP is in direct contact with the spacer SP and the top electrode layer 230, wherein the top surface S4 of the pad metal structure IMP is coplanar with the top surface S2 of the first dielectric layer 110.

[0082] like Fig.12As shown, then, a chemical vapor deposition process is performed to deposit an etching stop layer 118 and a second dielectric layer 120 on the substrate 100. According to an embodiment of the present invention, for example, the etching stop layer 118 may include a silicon nitride layer or a nitrogen-doped silicon carbide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the second dielectric layer 120 may include a silicon oxide layer, but is not limited thereto.

[0083] like Fig.13 As shown, a metallization process is then performed to form contact structures UM and UMP in the second dielectric layer 120 and the etching stop layer 118 in the logic circuit region LR and the memory region MR, respectively. The contact structure UMP formed in the memory region MR directly contacts the metal layer IMP, and the contact structure UMP penetrates the second dielectric layer 120 and is electrically connected to the top electrode layer 230 of the resistance switching structure RS.

[0084] Structurally, such as Fig.13 As shown, the resistance switching element 1 of the present invention includes a substrate 100, a first dielectric layer 110 disposed on the substrate 100, and a conductive via 112a disposed in the first dielectric layer 110. The resistance switching element 1 also includes a resistance switching structure RS embedded in the upper portion of the conductive via 112a. The resistance switching structure RS includes a top electrode layer 230 having a lower sharp corner TA-1, a resistance switching material layer 220 covering the lower sharp corner TA-1 of the top electrode layer 230, and a bottom electrode layer 210 disposed between the resistance switching material layer 220 and the upper portion of the conductive via 112a.

[0085] See also Figures 14 to 20 , which is a schematic diagram of a method for forming a resistance switching element according to another embodiment of the present invention, wherein the same regions, layers or elements are still represented by the same symbols.

[0086] In completion Figures 1 to 4 After the steps, Fig.14 As shown, then, a chemical mechanical polishing process is performed to remove the stacked structure 200 outside the trench T2, thereby forming a resistance switching structure RS partially embedded in the upper portion of the conductive via 112a. According to an embodiment of the present invention, the resistance switching structure RS may have a U-shaped cross-sectional profile. According to an embodiment of the present invention, the top surface S3 of the resistance switching structure RS is coplanar with the top surface S2 of the first dielectric layer 110 and the top surface S1 of the conductive via 112a.

[0087] like Fig.15 As shown, then, a grinding stop layer 114 is deposited all over the substrate 100, so that the etch stop layer 114 is conformally deposited on the first dielectric layer 110 and the resistance switching structure RS. According to an embodiment of the present invention, for example, the etch stop layer 114 may include a nitrogen-doped silicon carbide layer.

[0088] like Fig.16 As shown, then, a trench T3 is formed in the etching stop layer 114 and the first dielectric layer 110 in the logic circuit region LR by using photolithography and etching processes.

[0089] like Fig.17 As shown, photolithography and etching processes are then performed to form a circuit trench structure IS in the logic circuit region LR.

[0090] like Fig.18 As shown, a metallization process and a chemical mechanical polishing process are then performed to form a metal layer IM in the circuit trench structure IS of the logic circuit region LR.

[0091] like Fig.19 and Fig. 20 As shown, then, a chemical vapor deposition process is performed to deposit an etching stop layer 118 and a second dielectric layer 120 on the substrate 100. According to an embodiment of the present invention, for example, the etching stop layer 118 may include a silicon nitride layer or a nitrogen-doped silicon carbide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the second dielectric layer 120 may include a silicon oxide layer, but is not limited thereto.

[0092] Then, a metallization process is performed to form contact structures UM and UMP in the second dielectric layer 120 and the etching stop layer 118 in the logic circuit region LR and the memory region MR, respectively. The contact structure UMP formed in the memory region MR directly penetrates the etching stop layer 114 and contacts the top electrode layer 230 of the resistance switching structure RS.

[0093] See also Figure 21 to Figure 27 , which is a schematic diagram of a method for forming a resistance switching element according to yet another embodiment of the present invention, wherein the same regions, layers or elements are still represented by the same symbols.

[0094] Also completing Figures 1 to 4 After the steps, Fig.21 As shown, a photoresist pattern PR1 is formed on the stacked structure 200 , wherein the photoresist pattern PR1 covers the logic circuit region LR and includes a plurality of island patterns PR1 a in the memory region MR, which are aligned with the conductive vias 112 a .

[0095] like Fig. 22 As shown, an anisotropic dry etching process is performed to etch the stacked structure 200 and a portion of the first dielectric layer 110 that are not covered by the photoresist pattern PR1, so that a resistance switching structure RS having a sawtooth cross-sectional profile is formed on the conductive via 112a. At this time, the upper portion of the conductive via 112a and the resistance switching structure RS protrude from the upper surface S2 of the first dielectric layer 110.

[0096] like Fig.23 As shown, then, a grinding stop layer 118 is deposited on the substrate 100 in an all-round manner, so that the etching stop layer 118 is conformally deposited on the first dielectric layer 110 and the resistance switching structure RS. According to an embodiment of the present invention, for example, the etching stop layer 118 may include a nitrogen-doped silicon carbide layer. Then, a second dielectric layer 120 is deposited on the etching stop layer 118. According to an embodiment of the present invention, for example, the second dielectric layer 120 may include a silicon oxide layer, but is not limited thereto.

[0097] like Fig.24 As shown, then, a trench T4 is formed in the etching stop layer 118 and the second dielectric layer 120 in the logic circuit region LR by using photolithography and etching processes.

[0098] like Fig.25 As shown, a planarization layer 150 is formed on the second dielectric layer 120 and in the trench T4, for example, spin-on glass, etc., but not limited thereto. Then, a photolithography process is performed to form a photoresist pattern PR2 on the planarization layer 150. According to an embodiment of the present invention, the photoresist pattern PR2 has an opening OPV in the logic circuit region LR, defining the position of the through hole to be formed in the first dielectric layer 110. According to an embodiment of the present invention, the photoresist pattern PR2 has an opening OPT in the memory region MR, which is located directly above the conductive through hole 112a and is aligned with the conductive through hole 112a.

[0099] like Fig.26 As shown, an anisotropic dry etching process is performed using the photoresist pattern PR2 as an etching resistance mask, and the planarization layer 150 and the first dielectric layer 110 are etched downward through the opening OPV, and the planarization layer 150 and the etching stop layer 114 are etched downward through the opening OPT at the same time, so that a circuit trench structure IS is formed in the logic circuit region LR, and a through hole VP is formed in the second dielectric layer 120 in the memory region MR, exposing a portion of the top electrode layer 230.

[0100] like Fig. 27 As shown, a metallization process is then performed to fill the circuit trench structure IS of the logic circuit region LR and the through hole VP of the memory region MR with metal layers IM and IMP, respectively. According to an embodiment of the present invention, the metal layer IMP is in direct contact with the top electrode layer 230 of the resistance switching structure RS.

[0101] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A resistance switching element, comprising: substrate; A first dielectric layer is disposed on the substrate; A conductive via disposed in the first dielectric layer; and A resistance switching structure is embedded in the upper part of the conductive through hole, wherein the resistance switching structure includes a top electrode layer having a lower pointed corner, a resistance switching material layer arranged around the lower pointed corner of the top electrode layer, and a bottom electrode layer arranged between the resistance switching material layer and the upper part of the conductive through hole.

2. The resistance switching element according to claim 1, wherein: The lower sharp angle is a right angle or an obtuse angle.

3. The resistance switching element according to claim 1, wherein: The resistance switching structure has an L-shaped cross-sectional profile.

4. The resistance switching element according to claim 1, wherein: The resistance switching structure has a sawtooth cross-sectional profile.

5. The resistance switching element according to claim 1, wherein: A top surface of the resistance switching structure is coplanar with a top surface of the first dielectric layer and a top surface of the conductive via.

6. The resistance switching element according to claim 1, wherein: The sidewall surface of the resistance switching structure is covered with a spacer.

7. The resistance switching element according to claim 6, wherein: The spacer comprises silicon nitride.

8. The resistance switching element according to claim 6, wherein: Also includes: A pad metal structure is embedded in the first dielectric layer and connected to the resistance switching structure, wherein the pad metal structure is in direct contact with the spacer and the top electrode layer, and wherein the top surface of the pad metal structure is coplanar with the top surface of the first dielectric layer.

9. The resistance switching element according to claim 1, wherein: The conductive via includes tungsten.

10. The resistance switching element according to claim 1, wherein: The bottom electrode includes TaN, TiN, Pt, Ir, Ru or W.

11. The resistance switching element according to claim 1, wherein: The top electrode includes TiN, TaN, Pt, Ir or W.

12. The resistance switching element according to claim 1, wherein: The resistance switching layer includes hafnium oxide, tantalum oxide or titanium.

13. The resistance switching element according to claim 1, wherein: Also includes: a second dielectric layer disposed on the top electrode layer; and A contact penetrates the second dielectric layer and is electrically connected to the top electrode layer.

14. A method of forming a resistance switching element, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a conductive via in the first dielectric layer; and A resistance switching structure is formed embedded in the upper portion of the conductive via, wherein: The resistance switching structure includes a top electrode layer with a lower sharp corner, a resistance switching material layer disposed at the lower sharp corner of the top electrode layer, and a bottom electrode layer disposed between the resistance switching material layer and the upper portion of the conductive through hole.

15. The method of claim 14, wherein: The lower angle is a right angle or an obtuse angle.

16. The method of claim 14, wherein: The resistance switching structure has an L-shaped cross-sectional profile.

17. The method of claim 14, wherein: The resistance switching structure has a sawtooth cross-sectional profile.

18. The method of claim 14, wherein: A top surface of the resistance switching structure is coplanar with a top surface of the first dielectric layer and a top surface of the conductive via.

19. The method of claim 14, wherein: The sidewall surface of the resistance switching structure is covered with a spacer.

20. The method of claim 19, further comprising: A pad metal structure is formed, embedded in the first dielectric layer and connected to the resistance switching structure, wherein: The pad metal structure is in direct contact with the spacer and the top electrode layer, and the top surface of the pad metal structure is coplanar with the top surface of the first dielectric layer.

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