Clamp circuit and amplifier

Abstract

The clamping circuit is connected between a node through which the high-frequency signal passes and a ground potential. The clamp circuit includes a plurality of clamp elements connected in multiple stages. Each of the plurality of clamp elements is turned on when a voltage greater than or equal to the rising edge voltage is applied. At least one of the plurality of clamp elements is configured from a resistance-connected transistor including a bipolar transistor and a base-collector resistance element connected between a base and a collector.

Description

Technical Field

[0001] The invention relates to a clamping circuit and an amplifier. Background Art

[0002] One of the main components installed in portable terminals is a high-frequency power amplifier. In order to increase the wireless transmission capacity of portable terminals, wireless communication standards that use many frequency bands, such as carrier aggregation (CA), have been put into practical use. As the number of frequency bands used increases, the circuit structure of the RF front end becomes more complicated. Furthermore, in order to be able to use the frequency band of the Sub-6GHz band of the 5th generation mobile communication system (5G), the circuit structure of the RF front end becomes more complicated.

[0003] If the circuit structure of the RF front end becomes complicated, the loss caused by the filter, switch, etc. inserted in the transmission line from the high-frequency power amplifier to the antenna increases. As a result, high-frequency power amplifiers are required to have higher output in addition to being able to cope with multiple frequency bands.

[0004] The output current and output voltage of a high-frequency power amplifier vary greatly depending on the load impedance. High-frequency power amplifiers are required to have high output and to improve the withstand voltage characteristics when the load impedance varies. By inserting a clamp circuit between the output terminal (collector of a bipolar transistor) of a power stage transistor of a high-frequency power amplifier and ground, an excessive rise in the output voltage can be suppressed. This can suppress the breakdown of the transistor.

[0005] In addition, in a semiconductor device that is mixed with a high-voltage circuit and a low-voltage circuit, a clamp circuit is used to prevent a high voltage from being applied to the low-voltage circuit (for example, Patent Document 1). The clamp circuit is composed of a plurality of diodes connected in multiple stages in the forward direction. For example, bipolar transistors connected in diodes can be used for these diodes.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2009-164415 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] The clamp circuit is turned on when a given clamp voltage is applied, and when a voltage higher than the clamp voltage is applied to both ends of the clamp circuit, the voltage rise is limited, making it difficult to generate excessive voltage. The clamp voltage is equal to the value of the rising edge voltage of each of the multiple diodes constituting the clamp circuit multiplied by the number of diode stages. Therefore, the clamp voltage becomes a value of an integer multiple of the rising edge voltage of each of the multiple diodes.

[0011] As the RF front end becomes more complex, the requested output of the high-frequency power amplifier becomes larger. The clamping circuit needs to limit the output power so that the requested output required for the high-frequency power amplifier circuit is met and does not exceed the breakdown limit. If the requested output of the high-frequency power amplifier becomes larger, the requested output is close to the breakdown limit of the transistor, so it becomes necessary to finely adjust the size of the output power limit (sometimes called power limiting) of the high-frequency power amplifier circuit. In the previous clamping circuit that can only adjust the clamping voltage of the output node of the high-frequency power amplifier to a value of an integer multiple of the rising edge voltage of each of the multiple diodes, it is difficult to finely adjust the size of the output power limit so that the requested output close to the breakdown limit is met and does not exceed the breakdown limit.

[0012] In addition, by connecting a clamp circuit to the input side of the high-frequency power amplifier and limiting the input power, the output power can also be limited. Even in the clamp circuit on the input side, if the conventional clamp circuit can only adjust the clamp voltage to a value of an integral multiple of the rising edge voltage of each of the plurality of diodes, it is difficult to finely adjust the magnitude of the input power limit so as to meet the requested output close to the breakdown limit and not exceed the breakdown limit.

[0013] An object of the present invention is to provide a clamp circuit capable of finely adjusting the magnitude of power limitation.

[0014] Technical solutions to solve problems

[0015] According to one aspect of the present invention, there is provided a clamping circuit connected between a node through which a high-frequency signal passes and a ground potential, wherein:

[0016] The clamp circuit includes a plurality of clamp elements connected in multiple stages.

[0017] Each of the plurality of clamp elements is turned on when a voltage higher than the rising edge voltage is applied.

[0018] At least one of the plurality of clamp elements is formed of a resistor-connected transistor including a bipolar transistor and a base-collector resistor element connected between a base and a collector.

[0019] According to another aspect of the present invention, there is provided an amplifier comprising:

[0020] a high-frequency power amplifier circuit that amplifies a high-frequency signal input from an input node and outputs it from an output node; and

[0021] The clamp circuit is connected between one of an input node and an output node of the high-frequency power amplifier circuit and a ground potential.

[0022] Effects of the Invention

[0023] If a given voltage is applied between the collector and the emitter of the resistance-connected transistor, the resistance-connected transistor is turned on. If the resistance value of the base-emitter resistance element of the resistance-connected transistor changes, the current-voltage characteristic of the clamp circuit changes. Therefore, by adjusting the resistance value of the base-emitter resistance element, the size of the power limitation caused by the conduction of the clamp circuit can be finely adjusted. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A is an equivalent circuit diagram of an amplifier including the clamp circuit according to the first embodiment, Figure 1 B is an equivalent circuit diagram of an amplifier including a clamp circuit according to a comparative example.

[0025] Figure 2 A schematically shows the first embodiment ( Figure 1 A) and Comparative Example ( Figure 1 B) is a graph showing the relationship between the clamp current Id and the output voltage Vout of the clamp circuit. Figure 2 B schematically shows the first embodiment ( Figure 1 A) and Comparative Example ( Figure 1 B) A graph showing the relationship between the amplifier gain and output power Pout.

[0026] Figure 3 A is an equivalent circuit diagram of a clamp circuit and an amplifier according to the second embodiment. Figure 3 B is an equivalent circuit diagram of a clamp circuit and an amplifier according to a comparative example, Figure 3 C is an equivalent circuit diagram of an amplifier according to another comparative example.

[0027] Figure 4 A is configured according to the second embodiment ( Figure 3 A) A cross-sectional view of the clamping circuit including the diode. Figure 4 B and Figure 4 C is a cross-sectional view of a portion where a resistance-connected transistor is arranged.

[0028] Figure 5 A is a diagram showing the positional relationship of the components of the clamp circuit according to the second embodiment in a plan view. Figure 5 B is a diagram showing the comparison example ( Figure 3 B) is a diagram showing the positional relationship of components of the clamp circuit in a plan view.

[0029] Figure 6 A is the equivalent circuit diagram of the simulated circuit. Figure 6 B is a diagram showing the second embodiment ( Figure 3 A) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results showing the relationship between the amplifier gain and output power Pout.

[0030] Figure 7 It is an equivalent circuit diagram of the clamp circuit and the amplifier according to the third embodiment.

[0031] Figure 8 This is a diagram showing the top-view arrangement of a resistor-connected transistor and a plurality of diodes constituting a clamp circuit according to a third embodiment.

[0032] Fig. 9 is a diagram showing the third embodiment ( Figure 7 ) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results showing the relationship between the amplifier gain and output power Pout.

[0033] Fig.10 It is an equivalent circuit diagram of the clamp circuit and the amplifier according to the fourth embodiment.

[0034] Fig.11 It is an equivalent circuit diagram of a clamp circuit and an amplifier according to a modified example of the fourth embodiment.

[0035] Fig.12 It is an equivalent circuit diagram of the clamp circuit and the amplifier according to the fifth embodiment.

[0036] Fig.13 is a diagram showing the fifth embodiment ( Fig.12 ) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results showing the relationship between the amplifier gain and output power Pout.

[0037] Fig.14 It is an equivalent circuit diagram of a clamp circuit and an amplifier according to a modified example of the fifth embodiment.

[0038] Fig.15 A modified example according to the fifth embodiment ( Fig.14 ) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results showing the relationship between the amplifier gain and output power Pout.

[0039] Fig.16 A is an equivalent circuit diagram of a clamp circuit and an amplifier according to the sixth embodiment. Fig.16 B is an equivalent circuit diagram of a clamp circuit and an amplifier according to a comparative example.

[0040] Fig.17A is a graph showing the result of simulating the relationship between input power Pin and gain. Fig.17 B is a graph showing the result of simulation of the relationship between the output power Pout and the gain.

[0041] Fig.18 A is an equivalent circuit diagram of an amplifier according to the seventh embodiment, Fig.18 B and Fig.18 C is an equivalent circuit diagram of an amplifier according to a variation of the seventh embodiment.

[0042] Fig.19 It is an equivalent circuit diagram of an amplifier according to another variation of the seventh embodiment.

[0043] Fig. 20 A. Fig. 20 B. and Fig. 20 C is an equivalent circuit diagram of an amplifier according to another variation of the seventh embodiment.

[0044] Fig.21 A. Fig.21 B. and Fig.21 C is an equivalent circuit diagram of an amplifier according to another variation of the seventh embodiment.

[0045] Fig. 22 is an equivalent circuit diagram of the amplifier according to the eighth embodiment.

[0046] Fig.23 It is an equivalent circuit diagram of an amplifier according to a variation of the eighth embodiment.

[0047] Fig.24 is an equivalent circuit diagram of an amplifier according to another variation of the eighth embodiment.

[0048] Fig.25 is an equivalent circuit diagram of an amplifier according to the ninth embodiment.

[0049] Fig.26 It is an equivalent circuit diagram of an amplifier according to a variation of the ninth embodiment.

[0050] Fig. 27 is an equivalent circuit diagram of an amplifier according to another variation of the ninth embodiment.

[0051] Fig.28 is an equivalent circuit diagram of the amplifier according to the tenth embodiment. DETAILED DESCRIPTION

[0052] [First embodiment]

[0053] Reference Figure 1 A to Figure 2B illustrates the clamp circuit and amplifier according to the first embodiment.

[0054] Figure 1 A is an equivalent circuit diagram of an amplifier including a clamp circuit according to the first embodiment. A high-frequency signal RFin is input to an input node 11 of a high-frequency power amplifier circuit 10 (hereinafter referred to as an "amplifier circuit"), and an amplified high-frequency signal is output from an output node 12. The amplifier circuit 10 includes, for example, a plurality of heterojunction bipolar transistors (HBTs) connected in parallel to each other. A power supply voltage Vcc is applied to the output node 12 (i.e., the collectors of the plurality of HBTs) via a choke coil 50.

[0055] A clamp circuit 20 is connected between the output node 12 and a reference potential (hereinafter referred to as a ground potential). That is, the clamp circuit 20 is connected between a node through which a high-frequency signal passes and the ground potential. The clamp circuit 20 includes a plurality of (for example, three) clamp elements connected in multiple stages (connected in series). One of the plurality of clamp elements is a resistor-connected transistor 21, and the other two are diodes 25. As the diode 25, for example, a general pn junction diode can be used. If the peak value of the high-frequency voltage generated between the output node 12 and the ground potential exceeds a given voltage value, the clamp circuit 20 is turned on, thereby limiting the peak value of the high-frequency voltage between the output node 12 and the ground potential.

[0056] When the clamp circuit 20 is turned on, part of the high-frequency signal output from the output node 12 flows through the clamp circuit 20 , and the remaining high-frequency signal RFout is supplied to a subsequent circuit (eg, a load).

[0057] The resistance connection type transistor 21 includes a bipolar transistor 22 (hereinafter referred to as "transistor 22") and a base-collector resistance element 23 connected between the base and the collector of the transistor 22. The collector of the transistor 22 is connected to the output node 12. A plurality of diodes 25 connected in multiple stages are connected between the emitter of the transistor 22 and the ground potential. The plurality of diodes 25 are connected in a forward direction from the output node 12 toward the ground potential.

[0058] When a voltage higher than the rising edge voltage is applied to each diode 25, a forward current flows through the diode 25. The rising edge voltage of the diode 25 is denoted as Von. The current flowing through the clamp circuit 20 (hereinafter referred to as the clamp current) is denoted as Id, the resistance value of the base-collector resistor 23 is denoted as R, and the current amplification factor of the transistor 22 is denoted as β. The base-emitter voltage of the transistor 22 is denoted as Vbe.

[0059] If a voltage greater than the base-emitter voltage Vbe is applied to the resistor-connected transistor 21, the transistor 22 is turned on. The voltage drop caused by the base-collector resistor 23 at this time can be expressed as R×Id / (1+β). The collector-emitter voltage Vce of the transistor 22 can be expressed as R×Id / (1+β)+Vbe.

[0060] When the same layer as the emitter layer of the transistor 22 and the same layer as the base layer are used as the cathode layer and the anode layer of the diode 25, respectively, the base-emitter voltage Vbe of the transistor 22 becomes equal to the rising edge voltage Von of the diode 25. At this time, if a voltage higher than the rising edge voltage Von is applied to the resistance-connected transistor 21 and the diode 25, respectively, the clamp circuit 20 is turned on.

[0061] When the clamp current Id flows through the clamp circuit 20, the voltage across both ends of the resistance-connected transistor 21 becomes higher by R×Id / (1+β) than the rising edge voltage Von of each diode 25. That is, the resistance-connected transistor 21 is equivalent to a circuit in which a resistor having a resistance value of R / (1+β) is connected in series to the diode 25.

[0062] Next, refer to Figure 1 B. Figure 2 A. and Figure 2 B. The clamp characteristics of the clamp circuits according to the first embodiment and the comparative example are described.

[0063] Figure 1 B is an equivalent circuit diagram of an amplifier including a clamp circuit 20D according to a comparative example. The clamp circuit 20D according to the comparative example is composed of four diodes 25 connected in series, and does not include a resistor-connected transistor 21 ( Figure 1 A).

[0064] Figure 2 A schematically shows the first embodiment ( Figure 1 A) and Comparative Example ( Figure 1 B) is a graph showing the relationship between the clamp current Id and the output voltage Vout (the voltage of the output node 12) of the clamp circuit. The horizontal axis of the graph represents the output voltage Vout, and the vertical axis represents the clamp current Id. In addition, the output voltage Vout and the clamp current Id represent the instantaneous value of the high-frequency signal.

[0065] The thin solid line and the thick solid line in the graph show the first embodiment ( Figure 1 A) is a clamp current Id of the clamp circuit 20. If the base-collector resistance element 23 is increased, the clamp current Id approaches the characteristic of the thin solid line from the characteristic of the thick solid line. The thin dotted line shows the characteristic of the clamp circuit 20 according to the comparative example ( Figure 1B) of the clamp circuit 20D, the thick dashed line shows the clamp current Id according to the comparative example ( Figure 1 B) The clamp current Id of the clamp circuit 20D when the diode 25 of the clamp circuit 20D is changed from a four-stage structure to a three-stage structure.

[0066] In the comparative example ( Figure 1 In B), the clamp current Id starts to flow when the output voltage Vout reaches 4×Von. If the diode 25 is configured as a three-stage structure, the clamp current Id starts to flow when the output voltage Vout reaches 3×Von. The clamp current Id rises sharply as the output voltage Vout increases.

[0067] In the first embodiment ( Figure 1 ), the clamp current Id starts to flow from the time when the output voltage Vout reaches 3×Von. The clamp circuit 20 according to the first embodiment is equivalent to a circuit in which a resistor with a resistance value of R / (1+β) is connected in series to a multi-stage connection circuit including only diodes, so the increase slope of the clamp current Id accompanying the increase in the output voltage Vout is gentler than that of the comparative example. In addition, as the resistance value R of the base-collector resistor 23 increases, the slope of the graph becomes gentler.

[0068] Figure 2 B schematically shows the first embodiment ( Figure 1 A) and Comparative Example ( Figure 1 B) A graph showing the relationship between the gain and output power Pout of the amplifier. The horizontal axis of the graph represents the output power Pout, and the vertical axis represents the gain. In addition, the output power Pout means the average power of the high-frequency signal.

[0069] The thin solid line and the thick solid line in the graph show the first embodiment ( Figure 1 A) is the gain of the amplifier. If the resistance value R of the base-collector resistor 23 increases, the gain approaches the characteristic of the thin solid line from the characteristic of the thick solid line. The thin dotted line shows the gain of the amplifier according to the comparative example ( Figure 1 B) The gain of the amplifier, the thick dashed line shows that according to the comparative example ( Figure 1 B) The gain of the amplifier when the diode 25 of the clamp circuit 20D is changed from a four-stage structure to a three-stage structure. The long dashed line shows the gain of the amplifier without the clamp circuit connected.

[0070] If the clamp circuits 20 and 20D are connected, the output power Pout can be limited compared to the case where the clamp circuits are not connected. Figure 1B), if the clamp circuit 20D is changed from a four-stage structure of the diode 25 to a three-stage structure, the output power limitation amount (limiting amount) becomes larger. Figure 1 A) amplifier, the output power Pout is limited by more than that according to the comparative example ( Figure 1 B) is smaller than the limiting amount when the diode 25 of the clamp circuit 20D is set to a four-stage structure according to the comparative example ( Figure 1 B) The limiting amount when the diode 25 of the clamp circuit 20D is a three-stage structure.

[0071] Next, the excellent effects of the first embodiment will be described.

[0072] In the comparative example ( Figure 1 In the clamp circuit 20D where only the diodes 25 are connected in multiple stages as in B), the output voltage Vout at which the clamp circuit 20D starts conducting is limited to an integral multiple of the rising edge voltage Von of each diode 25, and the rising edge of the clamp current Id becomes steep. Figure 2 As shown in B, the output power Pout limit cannot be finely adjusted. Figure 2 In the graph shown in B, a characteristic between the gain-output voltage characteristic of the comparative example including the diode 25 of the three-stage structure and the gain-output voltage characteristic of the comparative example including the diode 25 of the four-stage structure cannot be achieved.

[0073] For example, when the clamp circuit 20D ( Figure 1 B) When the output power Pout exceeds the breakdown limit when the four-stage structure is used, the clamp circuit 20D must be set to a three-stage structure to prevent breakdown. Figure 2 As shown in B, the output power Pout is greatly limited and sometimes fails to satisfy the requested output.

[0074] In contrast, in the first embodiment, the clamp circuit 20 includes the resistor-connected transistor 21, thereby Figure 2 As shown in FIG. 2B , it is possible to achieve a gain-output voltage characteristic between the comparative example in which the clamp circuit 20D has a three-stage structure and the comparative example in which the clamp circuit 20D has a four-stage structure. By adjusting the base-collector resistor element 23 ( Figure 1 A) of the resistor value R, so that the output power limit amount can be finely adjusted so that the output power Pout is within the range that does not exceed the breakdown limit and satisfies the requested output.

[0075] Furthermore, if the resistance value R of the base-collector resistor 23 is increased, the gain-output power characteristic can be made as follows: Figure 2B is close to the gain-output power characteristic of the comparative example in which the clamp circuit 20D has a four-stage structure. That is, the gain-output power characteristic of the clamp circuit 20 having a total of three stages including one resistance-connected transistor 21 and two diodes 25 can be made close to the gain-output power characteristic of the clamp circuit 20D having a four-stage structure. Since the number of stages of the clamp circuit 20 is reduced, the area occupied by the clamp circuit 20 on the substrate can be reduced.

[0076] In addition, a plurality of diodes connected in multiple stages are sometimes used in an ESD protection circuit for protecting an electronic circuit from electrostatic discharge (ESD). The ESD protection circuit is not required to have a function of finely adjusting the limit amount of high-frequency output power. The structure of the clamp circuit according to the first embodiment is particularly suitable for a circuit for the purpose of improving the withstand voltage characteristics of a high-frequency power amplifier when the load impedance varies.

[0077] Next, a modification of the first embodiment will be described.

[0078] As the diode 25 ( Figure 1 A) A diode-connected bipolar transistor can also be used.

[0079] Although in the first embodiment ( Figure 1 A), the diode 25 is formed by the same layer as the base layer of the transistor 22 and the same layer as the emitter layer, but the diode 25 may be formed by the same layer as the base layer and the same layer as the collector layer. In this case, the rising edge voltage Von of the resistance-connected transistor 21 and the rising edge voltage Von of the diode 25 will not become the same. Furthermore, as the diode 25, a bipolar transistor connected by a diode may be used, for example, a HBT connected by a diode may be used. For example, as the diode 25, an HBT in which the base and the collector are short-circuited may be used, and an HBT in which the emitter and the base are short-circuited may be used.

[0080] In the first embodiment, the clamp circuit 20 is composed of one resistance-connected transistor 21 and two diodes 25, but the number of resistance-connected transistors 21 may be set to two or more as described later in other embodiments. In addition, the number of diodes 25 may be set to one or three or more. Furthermore, the clamp circuit 20 may be composed of only a plurality of resistance-connected transistors 21 without including the diodes 25.

[0081] [Second embodiment]

[0082] Next, refer to Figure 3 A to Figure 6B, a clamp circuit and an amplifier according to a second embodiment are described. Figure 1 A) Common structures, description will be omitted.

[0083] Figure 3 A is an equivalent circuit diagram of the clamp circuit 20 and the amplifier according to the second embodiment. Figure 1 In A), the clamp circuit 20 is composed of one resistance-connected transistor 21 and two diodes 25. In contrast, in the second embodiment, the clamp circuit 20 is composed of one resistance-connected transistor 21 and six diodes 25 connected in multiple stages.

[0084] Figure 3 B is an equivalent circuit diagram of a clamp circuit 20D and an amplifier according to a comparative example, Figure 3 C is an equivalent circuit diagram of an amplifier according to another comparative example. Figure 3 In the comparative example shown in B, the clamp circuit 20D is composed of nine diodes 25 connected in multiple stages, and does not include a resistor-connected transistor. Figure 3 In the comparative example shown in C, no clamp circuit is connected to the output node 12 of the amplifier circuit 10 .

[0085] Figure 4 A is configured according to the second embodiment ( Figure 3 A) is a cross-sectional view of a diode 25 included in the clamp circuit 20. An epitaxial layer 81 is formed on a semiconductor substrate 80. The epitaxial layer 81 is composed of a plurality of conductive regions 81C and an insulating element isolation region 81I surrounding each of the conductive regions 81C. Each diode 25 includes a cathode layer 25C disposed above one conductive region 81C and an anode layer 25A disposed above the cathode layer 25C.

[0086] In addition to the cathode layer 25C, a cathode electrode 26C is disposed above the conductive region 81C. The cathode electrode 26C is electrically connected to the cathode layer 25C via the conductive region 81C. An anode electrode 26A is disposed above the anode layer 25A. The anode electrode 26A is in ohmic contact with the anode layer 25A. The wiring 40D of the first layer connects the cathode electrode 26 of one diode 25 to the anode electrode 26A of the adjacent diode 25.

[0087] Figure 4 B and Figure 4 C is configured with a resistor-connected transistor 21 ( Figure 3 A) is a cross-sectional view of the part. Figure 4As shown in FIG. 2B , a transistor 22 is disposed on the semiconductor substrate 80 . The transistor 22 includes a collector layer 22C and a base layer 22B stacked on one conductive region 81C of the epitaxial layer 81 , and two emitter mesas 22E disposed at a distance from each other on the base layer 22B.

[0088] In addition to the collector layer 22C, two collector electrodes 24C are arranged above the conductive region 81C so as to sandwich the collector layer 22C. The collector electrode 24C is electrically connected to the collector layer 22C via the conductive region 81C. An emitter electrode 24E is arranged above each of the two emitter mesas 22E. The emitter electrode 24E is electrically connected to the emitter mesas 22E. A base electrode 24B is arranged above the base layer 22B. The base electrode 24B is electrically connected to the base layer 22B. Figure 4 In the cross section shown in B, a part of the base electrode 24B is arranged between the two emitter mesas 22E.

[0089] exist Figure 4 In the cross section shown in FIG. B, the collector electrode 24C may be arranged only on one side of the collector layer 22C. Alternatively, in addition to a portion of the base electrode 24B between the two emitter mesas 22E, another portion of the base electrode 24B may be arranged outside the two emitter mesas 22E. In addition, the emitter mesas 22E may be provided as one. In this case, a portion of the base electrode 24B may be arranged on both sides of the emitter mesas 22E, or a portion of the base electrode 24B may be arranged on one side of the emitter mesas 22E.

[0090] The collector wiring 40C of the first layer is connected to the collector electrode 24C. The emitter wiring 40E of the first layer is connected to the two emitter electrodes 24E.

[0091] Figure 4 C is Figure 4 B is a cross-sectional view taken along the dashed line 4C-4C. Figure 4 B is equivalent to Figure 4 C is a cross-sectional view taken along the dashed line 4B-4B. Above the element isolation region 81I, a base-collector resistor 23 is disposed via an interlayer insulating film (not shown). The first-layer base wiring 40B connects the base electrode 24B and the base-collector resistor 23. In addition to the base wiring 40B, the first-layer collector wiring 40C and the emitter wiring 40E are also disposed.

[0092] Next, an example of the materials of the components of the resistance-connected transistor 21 and the diode 25 is described. As the semiconductor substrate 80, a semi-insulating GaAs substrate is used. The conductive region 81C of the epitaxial layer 81 is formed by n-type GaAs. The collector layer 22C and the cathode layer 25C are formed by patterning a common epitaxial layer formed by n-type GaAs. The base layer 22B and the anode layer 25A are formed by patterning a common epitaxial layer formed by p-type GaAs. The emitter mesa 22E is composed of an n-type InGaP layer and an n-type GaAs layer thereon. A contact layer formed by n-type InGaAs may also be arranged between the n-type GaAs layer and the emitter electrode 24E. In addition, other semiconductor materials may also be used for these parts. For the base-collector resistance element 23, for example, a thin film resistor material may be used.

[0093] Figure 5 A is a diagram showing the positional relationship of the components of the clamp circuit 20 according to the second embodiment in a plan view. One resistor-connected transistor 21 and six diodes 25 are arranged in two rows by turning back halfway. One row includes one resistor-connected transistor 21 and two diodes 25, and the other row includes four diodes 25. Figure 5 In A, the collector electrode 24C, the emitter electrode 24E, the base electrode 24B, the anode electrode 26A, and the cathode electrode 26C are hatched relatively densely and tilted downward to the right. The wiring of the first layer is indicated by a relatively thick outline, and the wiring of the first layer is hatched relatively sparsely and tilted upward to the right.

[0094] The collector wiring 40C, which is U-shaped when viewed from above, overlaps with the two collector electrodes 24C of the resistance-connected transistor 21, respectively, and is connected to the two collector electrodes 24C. A portion of the base electrode 24B, which is T-shaped when viewed from above, is arranged between the two emitter electrodes 24E. The base wiring 40B overlaps with a portion of the base electrode 24B, and is connected to the base electrode 24B at the overlapping portion. One end of the base-collector resistor 23 overlaps with the collector wiring 40C, and the other end overlaps with the base wiring 40B, and is respectively connected to the collector wiring 40C and the base wiring 40B at the overlapping portion. The emitter wiring 40E overlaps with the two emitter electrodes 24E, and is connected to the emitter electrode 24E at the overlapping portion.

[0095] The emitter wiring 40E extends to a portion overlapping with the anode electrode 26A of the adjacent diode 25 arranged in the same row, and is connected to the anode electrode 26A at the overlapping portion. The cathode electrode 26C of the diode 25 is U-shaped in a plan view, and surrounds the anode electrode 26A from three directions. In addition, the shape of the cathode electrode 26C in a plan view may also be a shape other than the U-shape. The wiring 40D overlaps with the cathode electrode 26C of one diode 25 and the anode electrode 26A of the other diode 25 in a plan view, respectively, and is connected to the cathode electrode 26C and the anode electrode 26A at the overlapping portion.

[0096] The cathode electrode 26C of the diode 25 located at the end of the first row is connected to the anode electrode 26A of the diode 25 located at the end of the second row via the wiring 40D. The cathode electrode 26C of the diode 25 located at the other end of the second row is connected to the ground potential. The collector wiring 40C connected to the collector electrode 24C of the resistance-connected transistor 21 is connected to the output node 12 ( Figure 3 A).

[0097] Figure 5 B is a diagram showing the comparison example ( Figure 3 FIG. 2 is a diagram showing the positional relationship of the components of the clamp circuit 20D in a plan view. The nine diodes 25 are arranged in two rows by turning back halfway. The connection structure of the adjacent diodes 25 is similar to that of the clamp circuit 20 ( Figure 5 The connection structure of the two diodes 25 in A) is the same.

[0098] Next, refer to Figure 6 A and Figure 6 B. The amplifier ( Figure 3 A) and an amplifier according to a comparative example ( Figure 3 B. Figure 3 C) The relationship between the gain and the output power Pout is described below.

[0099] Figure 6 A is an equivalent circuit diagram of a simulated circuit. A high-frequency signal source 90 having an output impedance of 50Ω is connected to an input node 11 of the amplifier circuit 10 via an impedance matching circuit 92. A clamp circuit 20 or 20D is connected to an output node 12 of the amplifier circuit 10. Furthermore, a load 93 having an impedance of 5Ω is connected to the output node 12. Figure 3 A) uses a GaAs / InGaP HBT. The device temperature during operation is set to 25°C. The resistance value R ( Figure 3 A) is set to 100Ω.

[0100] The high frequency power (input power Pin) of 2.5 GHz generated by the high frequency signal source 90 was changed within a range of 30 dBm or less. The power supply voltage Vcc was set to 5.5 V. The base bias voltage of the HBT constituting the amplifier circuit 10 was set to 1.3V.

[0101] Figure 6 B is a diagram showing the second embodiment ( Figure 3 A) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results of the relationship between the gain and output power Pout of the amplifier. The horizontal axis represents the output power Pout in [dBm], and the vertical axis represents the gain in [dB]. Here, the output power Pout is the power consumed by the load 93.

[0102] Figure 6 The solid line, dotted line, and long dashed line in the graph shown in B respectively represent the use of the second embodiment ( Figure 3 A) Comparative Example ( Figure 3 B) and another comparative example ( Figure 3 C) The gain-output voltage characteristics of the amplifier of the clamp circuit. If the input power Pin is increased, the output power Pout also increases. If the input power Pin is greater than a certain value, the gain begins to decrease, and the increase of the output power Pout can be suppressed.

[0103] It can be seen that in the amplifier according to the comparative example ( Figure 3 B) and the amplifier according to the second embodiment ( Figure 3 A), approximately the same output power limit amount is obtained. Figure 3 A) uses a seven-stage clamp circuit 20, and in the comparative example ( Figure 3 B) uses a nine-stage clamp circuit 20D. That is, it can be seen that even with the clamp circuit 20D ( Figure 3 B) The number of stages is reduced compared to the clamp circuit 20 ( Figure 3 A) can also obtain approximately the same output power limitation.

[0104] Next, the excellent effects of the second embodiment will be described.

[0105] Like the second embodiment ( Figure 3 A. Figure 5 A), by using the resistor-connected transistor 21 as one of the clamp elements constituting the clamp circuit 20, the clamp circuit 20D ( Figure 3 B. Figure 5 B), the number of clamping elements can be reduced. Figure 5A and Figure 5 As shown in B, the area occupied by the clamp circuit 20 can be reduced. Figure 5 In A, an example in which the clamp circuit 20 of the multi-stage structure is folded back is shown. However, if the number of stages of the clamp circuit 20 is reduced, the clamp circuit 20 can be arranged in a straight line without folding back.

[0106] Furthermore, similarly to the first embodiment, by adjusting the resistance value R ( Figure 3 A), so that the output power limit amount can be finely adjusted. Thus, the output power limit amount can be adjusted so that the output power of the amplifier circuit 10 does not exceed the breakdown limit and satisfies the requested output.

[0107] [Third embodiment]

[0108] Next, refer to Figure 7 , Figure 8 as well as Fig. 9 , a clamp circuit and an amplifier according to a third embodiment are described. Figure 3 A) Common structures, description will be omitted.

[0109] Figure 7 2 is an equivalent circuit diagram of the clamp circuit 20 and the amplifier according to the third embodiment. Figure 3 In the embodiment A), the resistance-connected transistor 21 is connected to the end on the output node 12 side of the multi-stage clamp circuit 20. In contrast, in the third embodiment, the resistance-connected transistor 21 is connected to the middle stage of the multi-stage clamp circuit 20. For example, the resistance-connected transistor 21 is connected to the center of the multi-stage clamp circuit 20. That is, the number of diodes 25 connected to the output node 12 side of the resistance-connected transistor 21 and the number of diodes 25 connected to the ground potential side of the resistance-connected transistor 21 are the same.

[0110] Figure 8 1 is a diagram showing the top view of the configuration of the resistor-connected transistor 21 and the plurality of diodes 25 constituting the clamp circuit 20 according to the third embodiment. The configurations of the resistor-connected transistor 21 and the plurality of diodes 25 are similar to those of the clamp circuit according to the second embodiment ( Figure 5 A) has the same structure as the clamp circuit 20.

[0111] The six diodes 25 are arranged in two rows, and the diode 25 at the end of one row and the diode 25 at the end of the same side of the other row are connected via the resistance-connected transistor 21. That is, the plurality of clamp elements constituting the clamp circuit 20 are folded back and arranged in the middle, and the resistance-connected transistor 21 is arranged at the folded portion.

[0112] Fig. 9 is a diagram showing the third embodiment ( Figure 7 ) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results of the relationship between the gain and output power Pout of the amplifier. The horizontal axis represents the output power Pout in [dBm], and the vertical axis represents the gain in [dB]. Fig. 9 The solid line, dotted line, and long dashed line in the graph respectively show the use of the third embodiment ( Figure 7 )、Comparative Example( Figure 3 B), and another comparative example ( Figure 3 C) Gain-output voltage characteristics of the amplifier of the clamp circuit. The amplifier according to the third embodiment can also obtain characteristics substantially equivalent to the relationship between the gain and the output power Pout of the amplifier according to the second embodiment.

[0113] Next, the excellent effects of the third embodiment will be described.

[0114] In the third embodiment, as in the second embodiment, the base-collector resistor 23 can be adjusted to obtain a Figure 3 A), thereby finely adjusting the output power limit amount. Thus, the output power limit amount can be adjusted so that the output power does not exceed the breakdown limit of the amplifier circuit 10 and satisfies the requested output.

[0115] Furthermore, in the third embodiment, the resistance-connected transistor 21 is arranged at the turn-back portion of the clamp circuit 20 , so that the symmetry of the planar arrangement of the plurality of diodes 25 and the resistance-connected transistor 21 is improved, and the area occupied by the clamp circuit 20 can be reduced.

[0116] Next, a modification of the third embodiment will be described.

[0117] In the third embodiment, the resistor-connected transistor 21 is connected to the center of the multi-stage clamp circuit 20, but the resistor-connected transistor 21 may be connected to any other position.

[0118] [Fourth embodiment]

[0119] Next, refer to Fig.10 , a clamp circuit and an amplifier according to a fourth embodiment are described. Figure 7 , Figure 8 ,as well as Fig. 9 The common structures of the clamp circuit 20 and the amplifier according to the third embodiment described above will be omitted.

[0120] Fig.10is an equivalent circuit diagram of the clamp circuit 20 and the amplifier according to the fourth embodiment. Figure 7 ), a base-collector resistor 23 having a fixed resistance value R is connected between the base and collector of the resistance-connected transistor 21, and the base-collector resistance is a fixed value. In contrast, in the fourth embodiment, a variable resistance circuit 30 is connected in parallel with the base-collector resistor 23. The variable resistance circuit 30 includes a resistor 32 and a switch element 31 connected in series with each other. For the resistor 32, for example, a thin film resistor material can be used, as with the base-collector resistor 23. For the switch element 31, for example, a MOSFET can be used.

[0121] When the switch element 31 is switched between on and off, the resistance value between the base and the collector of the resistance-connected transistor 21 changes. Figure 2 As shown in A, the clamp current-output voltage characteristic changes, and as a result, the gain-output power characteristic changes.

[0122] Next, the excellent effects of the fourth embodiment will be described.

[0123] In the fourth embodiment, the output power limit amount can be adjusted more finely than in the third embodiment by adjusting the value of the base-collector resistance of the resistance-connected transistor 21. Thus, the output power limit amount can be adjusted so that the output power does not exceed the breakdown limit of the amplifier circuit 10 and the requested output is satisfied.

[0124] Next, refer to Fig.11 , a modified example of the fourth embodiment is described.

[0125] Fig.11 2 is an equivalent circuit diagram of a clamp circuit 20 and an amplifier according to a modification of the fourth embodiment. Fig.10 ), the resistor-connected transistor 21 is connected to the middle stage of the multi-stage clamp circuit 20. Fig.11 In the illustrated modification, a resistance-connected transistor 21 is connected to an end portion of the clamp circuit 20 on the ground potential side.

[0126] There is a parasitic capacitance between the mutual connection point of the clamping elements of each stage of the clamping circuit 20 and the ground potential. Due to these parasitic capacitances, when no current flows in the clamping circuit 20, the voltage applied to the diode 25 and the resistance-connected transistor 21 of each stage gradually decreases from the stage close to the output node 12 toward the stage close to the ground potential. As a result, if the resistance-connected transistor 21 is connected to the end on the ground potential side, the voltage applied to the switch element 31 decreases compared with the structure connected to the output node 12 side of the amplifier circuit 10. As a result, the switch element 31 can be miniaturized.

[0127] Next, another modification of the fourth embodiment will be described.

[0128] Although the variable resistance circuit 30 is composed of the switch element 31 and the resistor element 32 connected in series in the fourth embodiment, the variable resistance circuit 30 may be composed of only the switch element 31. In this case, when the switch element 31 is turned on, the base-collector of the resistance-connected transistor 21 is short-circuited, and the resistance-connected transistor 21 has the same current-voltage characteristics as the diode 25.

[0129] Although a single-pole single-throw (SPST) switch is used as the switch element 31 in the fourth embodiment, a single-pole multi-throw (SPNT) switch may be used, and resistor elements with different resistance values ​​may be connected to the multiple contacts of the SPNT switch. If this structure is adopted, the resistance value between the base and the collector of the resistance-connected transistor 21 can be changed more finely.

[0130] The variable resistance circuit 30 may be connected in series with the base-collector resistance element 23. In this case, the variable resistance circuit 30 may be configured to have a structure in which the resistance element and the switch element are connected in parallel. Even with this structure, the resistance value between the base and the collector of the resistance-connected transistor 21 can be changed by switching the switch element between conduction and non-conduction.

[0131] [Fifth embodiment]

[0132] Next, refer to Fig.12 as well as Fig.13 , the clamp circuit and amplifier according to the fifth embodiment are described. Figure 3 A. Figure 4 A to Figure 5 A description of the common structure of the clamp circuit 20 and the amplifier according to the second embodiment illustrated in FIG. 1 will be omitted.

[0133] Fig.12: is an equivalent circuit diagram of the clamp circuit 20 and the amplifier according to the fifth embodiment. Figure 3 A) A structure in which one resistance-connected transistor 21 and six diodes 25 are connected in multiple stages. In contrast, the clamp circuit 20 according to the fifth embodiment has a structure in which two resistance-connected transistors 21 and four diodes 25 are connected in multiple stages.

[0134] Fig.13 is a diagram showing the fifth embodiment ( Fig.12 ) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results of the relationship between the gain and output power Pout of the amplifier. The horizontal axis represents the output power Pout in [dBm], and the vertical axis represents the gain in [dB]. Fig.13 The solid line, dotted line, and long dashed line in the graph respectively show the use of the fifth embodiment ( Fig.12 )、Comparative Example( Figure 3 B), and another comparative example ( Figure 3 C) The gain-output voltage characteristics of the amplifier of the clamp circuit. The base-collector resistance element 23 ( Fig.12 ) are all set to 100Ω. If the input power Pin is greater than a certain value, the gain begins to decrease, and the increase in the output power Pout can be suppressed. It can be seen that in the amplifier according to the comparative example ( Figure 3 B) and the amplifier according to the fifth embodiment ( Fig.12 ), approximately the same output power limitation amount is obtained.

[0135] Next, the excellent effects of the fifth embodiment will be described.

[0136] According to the clamp circuit 20D ( Figure 3 B) has a nine-stage structure, whereas the clamp circuit 20 according to the fifth embodiment has a six-stage structure. As described above, in the fifth embodiment, the clamp circuit 20 can be realized with a small number of stages compared to the comparative example ( Figure 3 B) has the same output power limitation amount as the clamp circuit 20D of FIG. Therefore, the area occupied by the clamp circuit 20 on the substrate can be reduced.

[0137] Furthermore, even with the second embodiment ( Figure 3 Compared with the clamp circuit 20 of the second embodiment ( Figure 3 Compared with the area occupied by the clamp circuit 20 on the substrate in FIG. 1 , the area occupied by the clamp circuit 20 can be reduced.

[0138] Next, refer to Fig.14 as well as Fig.15 , a clamp circuit and an amplifier according to a variation of the fifth embodiment are described.

[0139] Fig.14 : is an equivalent circuit diagram of a clamp circuit 20 and an amplifier according to a modification of the fifth embodiment. Fig.12 ) has a structure in which two resistance-connected transistors 21 and four diodes 25 are connected in multiple stages. In contrast, Fig.14 The clamp circuit 20 according to the modified example of the fifth embodiment shown has a structure in which three resistance-connected transistors 21 and two diodes 25 are connected in multiple stages.

[0140] Fig.15 A modified example according to the fifth embodiment ( Fig.14 ) and Comparative Example ( Figure 3 B. Figure 3 C) is a graph of simulation results of the relationship between the gain and output power Pout of the amplifier. The horizontal axis represents the output power Pout in [dBm], and the vertical axis represents the gain in [dB]. Fig.15 The solid line, dotted line, and long dashed line in the graph respectively show the use of the modified example according to the fifth embodiment ( Fig.14 )、Comparative Example( Figure 3 B), and another comparative example ( Figure 3 C) Gain-output voltage characteristics of the amplifier of the clamp circuit The resistance value R of each of the base-collector resistance elements 23 of the three resistance-connected transistors 21 according to the modification of the fifth embodiment is set to 100Ω.

[0141] It can be seen that even in the amplifier according to the modified example of the fifth embodiment ( Fig.14 ) and the results obtained are similar to those obtained in the comparative example ( Figure 3 B) has an output power limit amount that is substantially the same as that of the amplifier. According to the clamp circuit 20 ( Fig.12 ) is a six-level structure. In contrast, Fig.14 The clamp circuit 20 according to the modified example shown has a five-stage structure. Therefore, compared with the fifth embodiment, the Fig.14 The area occupied by the clamp circuit 20 according to the modified example is shown.

[0142] Next, another modification of the fifth embodiment will be described.

[0143] In the simulation of the fifth embodiment and its modified example ( Fig.13 , Fig.15), the resistance values ​​R of the base-collector resistance elements 23 of all the resistance-connected transistors 21 included in the clamp circuit 20 are set to be the same. As another modification, the resistance values ​​R of the base-collector resistance elements 23 of the plurality of resistance-connected transistors 21 included in the clamp circuit 20 may be different. By making the resistance values ​​R different, the output power limit amount can be adjusted more finely.

[0144] In the fifth embodiment ( Fig.12 ) and its variants ( Fig.14 ), the clamp circuit 20 includes at least one diode 25. As another modification, the clamp circuit 20 may be configured to include a plurality of resistor-connected transistors 21 connected in multiple stages and not include the diode 25. In addition, the number of resistor-connected transistors 21 and the number of diodes 25 constituting the clamp circuit 20 may be adjusted according to the desired output power limitation amount.

[0145] [Sixth embodiment]

[0146] Next, refer to Fig.16 A to Fig.17 B, a clamp circuit and an amplifier according to a sixth embodiment are described. Figure 1 A) Common structures, description will be omitted.

[0147] Fig.16 A is an equivalent circuit diagram of the clamp circuit 20 and the amplifier according to the sixth embodiment. Figure 1 In A), the clamp circuit 20 is connected between the output node 12 of the amplifier circuit 10 and the ground potential. In contrast, in the sixth embodiment, the clamp circuit 20 is connected between the input node 11 of the amplifier circuit 10 and the ground potential.

[0148] The clamp circuit 20 is different from the clamp circuit 20 according to the first embodiment ( Figure 1 A) Similarly, it includes resistance-connected transistors 21 and diodes 25 connected in multiple stages. For example, one resistance-connected transistor 21 and one diode 25 are connected in series.

[0149] When the input voltage Vin (the voltage of the input node 11) becomes higher than the clamp voltage of the clamp circuit 20, the clamp circuit 20 turns on. Therefore, when the power (input power Pin) of the high-frequency signal RFin input from the previous amplifier circuit increases, a clamp current starts to flow in the clamp circuit 20. As a result, the power input to the input node 11 of the amplifier circuit 10 decreases. The clamp circuit 20 connected between the input node 11 of the amplifier circuit 10 and the ground potential has a function of limiting the power of the high-frequency signal input to the input node 11 of the amplifier circuit 10.

[0150] Fig.16 B is an equivalent circuit diagram of the clamp circuit 20 and the amplifier according to the comparative example. Fig.16 In the comparative example shown in B, the clamp circuit 20D connected to the input node 11 of the amplifier circuit 10 is composed only of a plurality of diodes 25 (for example, three diodes) connected in multiple stages, and the resistance-connected transistor 21 is not connected.

[0151] Fig.17 A is a graph showing the result of simulating the relationship between input power Pin and gain. Fig.17 B is a graph showing the result of simulation of the relationship between the output power Pout and the gain. Fig.17 The horizontal axis of A represents the input power Pin, in [dBm], Fig.17 The horizontal axis of B represents the output power Pout in [dBm]. Fig.17 A and Fig.17 The vertical axis of B represents gain, and the unit is [dB]. Here, gain means the ratio of output power Pout to input power Pin (when the unit is expressed in dB, it is the difference between output power Pout and input power Pin). The frequency of high-frequency signal RFin is set to 2.5 GHz, and the input power Pin is changed within a range below 30 dBm. The power supply voltage Vcc of amplifier circuit 10 is set to 5.5 V. The base bias voltage of HBT constituting amplifier circuit 10 is set to 1.3 V.

[0152] Fig.17 A and Fig.17 The thin solid line and the thick solid line in the graph shown in B respectively represent the sixth embodiment ( Fig.16 The gain when the resistance value R of the base-collector resistor 23 of the clamp circuit 20 of A) is set to 50Ω and 100Ω. The dotted line shows the gain when the base-collector resistor 23 of the clamp circuit 20 of Comparative Example ( Fig.16 B) shows the gain when the clamp circuit 20D is connected, and the long dashed line shows the gain when the clamp circuit is not connected. If the input power Pin is increased, the high frequency power input to the input node 11 of the amplifier circuit 10 can be limited.

[0153] like Fig.17 As shown in A, since the high frequency power input to the input node 11 is limited, the gain decreases when the input power Pin is about 23 dBm or more compared to the gain when the clamp circuit is not connected. The decrease in gain is the smallest when the clamp circuit is not connected. Fig.16 The gain drop in the sixth embodiment is an intermediate value between the two and is smaller when the resistance value R of the base-collector resistance element 23 is set to 100Ω than when the resistance value R of the base-collector resistance element 23 is set to 50Ω.

[0154] like Fig.17 As shown in FIG. 2B , if the clamp circuit 20 or the clamp circuit 20D is connected to the input node 11, the output power Pout can be limited compared to the case where the clamp circuit is not connected. Fig.16 A) compared to the comparative example ( Fig.16 B) has a larger output power limit. Fig.16 In A), the smaller the resistance value R of the base-collector resistance element 23 is, the larger the output power limit amount becomes.

[0155] Next, the excellent effects of the sixth embodiment will be described.

[0156] As in the sixth embodiment, the output power Pout can be limited by connecting the clamp circuit 20 to the input node 11 of the amplifier circuit 10. This can prevent the amplifier circuit 10 from operating beyond the breakdown limit. In addition, by adjusting the resistance value R of the base-collector resistor 23 of the resistance-connected transistor 21 included in the clamp circuit 20, the limit amount of the output power Pout can be finely adjusted. As a result, the limit amount of the output power Pout can be adjusted so that the output power does not exceed the breakdown limit and the requested output is satisfied.

[0157] In order to achieve the same output power limitation as the clamp circuit 20 in which the resistance value R of the base-collector resistor 23 is set to 100Ω using only the diode 25, for example, the clamp circuit 20D ( Fig.16 B) A multi-stage structure with more than three stages. In the sixth embodiment, the output power limitation amount equivalent to that of the clamp circuit 20D with more than three stages can be achieved by the clamp circuit 20 with a two-stage structure. Therefore, the area occupied by the clamp circuit 20 on the substrate can be reduced.

[0158] Next, a modification of the sixth embodiment will be described.

[0159] Although the clamp circuit 20 ( Fig.16 A) The resistor-connected transistor 21 and the diode 25 are included. However, the clamp circuit 20 may be constituted by a plurality of resistor-connected transistors 21 without using the diode 25 .

[0160] [Seventh embodiment]

[0161] Next, refer to Fig.18 A. An amplifier according to a seventh embodiment will be described. In the amplifier according to the seventh embodiment, the clamp circuit 20 according to any one of the first to sixth embodiments can be used.

[0162] Fig.18 A is an equivalent circuit diagram of an amplifier according to the seventh embodiment. The amplifier according to the seventh embodiment includes an amplifier circuit 10A at the primary stage and an amplifier circuit 10B at the output stage. In each of the first to sixth embodiments, a clamp circuit 20 is connected to one of the input node 11 or the output node 12 of an amplifier circuit 10. In the seventh embodiment, a clamp circuit 20B is connected to the output node 12B of the amplifier circuit 10B at the output stage of the two-stage amplifier. In addition, an impedance matching circuit is usually inserted between the amplifier circuit 10A at the primary stage and the amplifier circuit 10B at the output stage, but in Fig.18 The impedance matching circuit is omitted in A. Fig.18 B. Fig.18 The same is true in C.

[0163] The clamp circuit 20B has the same configuration as that of the first embodiment ( Figure 1 A) Second embodiment ( Figure 3 A) Embodiment 3 ( Figure 7 )、The fourth embodiment( Fig.10 )、5th embodiment( Fig.12 ), or the same structure as the clamping circuit 20 of the modified examples of these embodiments.

[0164] Fig.18 B and Fig.18 C is an equivalent circuit diagram of an amplifier according to a variation of the seventh embodiment.

[0165] exist Fig.18 In the modified example shown in B, a clamp circuit 20A is connected between the amplifier circuit 10A at the primary stage and the amplifier circuit 10B at the output stage. The clamp circuit 20A has the same structure as that according to the sixth embodiment ( Fig.16A) or the same structure as the clamp circuit 20 of its modified example. The inter-stage impedance matching circuit can be inserted between the output node 12A of the amplifier circuit 10A at the first stage and the clamp circuit 20A, or can be connected between the clamp circuit 20A and the input node 11B of the amplifier circuit 10B at the output stage. In addition, the impedance matching circuit can be inserted in these two places.

[0166] The preferred magnitude of the voltage (clamp voltage) at which the clamp circuit 20A should be turned on varies depending on the location where the impedance matching circuit is inserted. The clamp circuit 20A may be designed according to the clamp voltage required for the clamp circuit 20A.

[0167] exist Fig.18 In the variation shown in C, a clamp circuit 20A is connected between the amplifier circuit 10A at the first stage and the amplifier circuit 10B at the output stage, and another clamp circuit 20B is connected to the output node 12B of the amplifier circuit 10B at the output stage. The number of clamp circuits 20B is greater than that of the clamp circuit 20A.

[0168] Next, the excellent effects of the seventh embodiment will be described.

[0169] As in the seventh embodiment, even in a two-stage amplifier, the output power limit amount can be finely adjusted by connecting a clamp circuit to either the node between the amplifier circuit 10A at the first stage and the amplifier circuit 10B at the output stage or the output node 12B of the amplifier circuit 10B at the output stage. Thus, the output power limit amount can be adjusted so that the output power of the amplifier circuit 10B at the output stage does not exceed the breakdown limit and the requested output is satisfied.

[0170] like Fig.18 B, the number of stages of the clamp circuit 20A connected between stages is larger than that of Fig.18 The number of stages of the clamp circuit 20B connected to the output node 12B of the amplifier circuit 10B at the output stage as in A is small. Therefore, the area occupied by the clamp circuit on the substrate can be reduced.

[0171] like Fig.18 As shown in C, by connecting the clamp circuits 20A and 20B to the two nodes, respectively, it is possible to improve the effect of suppressing the output power of the amplifier circuit 10B in the output stage from exceeding the breakdown limit and operating.

[0172] Even if a clamp circuit is connected to input node 11A of amplifier circuit 10A at the first stage, no clamping effect is substantially obtained. Therefore, the clamp circuit is preferably connected between amplifier circuit 10A at the first stage and amplifier circuit 10B at the output stage, or at least one of output node 12B of amplifier circuit 10B at the output stage.

[0173] Next, refer to Figures 19 to 21 The accompanying drawings in Figure C illustrate various other modifications of the seventh embodiment. Figures 19 to 21 FIG. C is an equivalent circuit diagram of an amplifier according to various modified examples of the seventh embodiment. Although the amplifier according to the seventh embodiment has a two-stage structure, Figures 19 to 21 The amplifier according to the modification of the seventh embodiment shown in the drawings of FIG. C has a three-stage structure, including an amplifier circuit 10A at the first stage, an amplifier circuit 10B at the middle stage, and an amplifier circuit 10C at the output stage. In these drawings, the description of the impedance matching circuit is omitted.

[0174] exist Fig.19 In the modified example shown, a clamp circuit 20C is connected to an output node 12C of an amplifier circuit 10C at the output stage. Fig. 20 In the modification shown in A, a clamp circuit 20B is connected between the amplifier circuit 10B at the intermediate stage and the amplifier circuit 10C at the output stage. Fig. 20 In the modification shown in B, a clamp circuit 20A is connected between the first-stage amplifier circuit 10A and the middle-stage amplifier circuit 10B. Fig. 20 In the modification shown in C, a clamp circuit 20A is connected between the amplifier circuit 10A at the first stage and the amplifier circuit 10B at the middle stage, and a clamp circuit 20B is connected between the amplifier circuit 10B at the middle stage and the amplifier circuit 10C at the output stage.

[0175] exist Fig.21 A. Fig.21 B. and Fig.21 In the modified example shown in C, Fig. 20 A. Fig. 20 B. and Fig. 20 The output node 12C of the amplifier circuit 10C in the output stage of the amplifier according to the modification shown in C is further connected to a clamp circuit 20C.

[0176] Even in Figures 19 to 21 In the three-stage amplifier shown in C, the output power of the amplifier circuit 10C at the output stage can be limited by connecting the clamp circuits 20A, 20B, 20C, etc. to at least one node other than the input node 11A of the amplifier circuit 10A at the first stage. By including the resistor-connected transistor 21 in the clamp circuits 20A, 20B, 20C as in the clamp circuit 20 of the first embodiment, the output power limit amount can be finely adjusted.

[0177] [Eighth Embodiment]

[0178] Next, refer to Fig. 22, an amplifier according to an eighth embodiment will be described. In the amplifier according to the eighth embodiment, the clamp circuit 20 according to any one of the first to sixth embodiments can be used.

[0179] Fig. 22 : is an equivalent circuit diagram of an amplifier according to the eighth embodiment. In the amplifiers according to the first to sixth embodiments, both the input signal and the output signal are single-ended signals. In contrast, the amplifier according to the eighth embodiment includes an amplifier circuit 10A at the primary stage and amplifier circuits 10B1 and 10B2 at the output stage, and the amplifier circuits 10B1 and 10B2 constitute a differential amplifier circuit. A high-frequency signal RFin as a single-ended signal is input to the amplifier circuit 10A at the primary stage. The balanced-unbalanced conversion circuit 55 converts the high-frequency signal output from the amplifier circuit 10A into a differential signal.

[0180] One of the differential signals output from the balanced-unbalanced conversion circuit 55 is input to the amplifier circuit 10B1, and the other is input to the amplifier circuit 10B2. A clamp circuit 201 is connected between the output node 12B1 of the amplifier circuit 10B1 and the ground potential, and another clamp circuit 202 is connected between the output node 12B2 of the other amplifier circuit 10B2 and the ground potential. For example, the clamp circuits 201 and 202 may be configured as those according to the first embodiment ( Figure 1 A) Second embodiment ( Figure 3 A) Embodiment 3 ( Figure 7 )、The fourth embodiment( Fig.10 )、5th embodiment( Fig.12 ), or a clamp circuit 20 of a modified example thereof.

[0181] When the output voltage of amplifier circuit 10B1 becomes higher than the clamp voltage of clamp circuit 201 , the output power of amplifier circuit 10B1 is limited. When the output voltage of amplifier circuit 10B2 becomes higher than the clamp voltage of clamp circuit 202 , the output power of amplifier circuit 10B2 is limited.

[0182] Next, the excellent effects of the eighth embodiment will be described.

[0183] By combining the first embodiment ( Figure 1 A) Second embodiment ( Figure 3 A) Embodiment 3 ( Figure 7 )、The fourth embodiment( Fig.10 )、5th embodiment( Fig.12), or the clamp circuit 20 of the modified example thereof is applied to the differential amplifier circuit, so that even in the differential amplifier circuit, the output power limit amount can be finely adjusted as in the first embodiment, etc. Thus, the output power limit amount can be adjusted so that the output power of the amplifier circuits 10B1 and 10B2 at the output stage does not exceed the breakdown limit and satisfies the requested output.

[0184] Next, refer to Fig.23 as well as Fig.24 , a modified example of the 8th embodiment is described. Fig.23 as well as Fig.24 It is an equivalent circuit diagram of an amplifier according to a variation of the eighth embodiment.

[0185] You can also Fig.23 As shown in the modified example, the clamp circuit 200 is connected between the output node 12A of the first-stage amplifier circuit 10A and the balanced-unbalanced conversion circuit 55. The clamp circuit 200 has, for example, the same configuration as that according to the sixth embodiment ( Fig.16 A) has the same structure as the clamp circuit 20. The clamp circuit 200 can limit the power of the single-ended signal input to the balanced-unbalanced conversion circuit 55. As a result, the power of the differential signal input to the amplifier circuits 10B1 and 10B2 at the output stage can be limited.

[0186] You can also Fig.24 As shown in the modified example, a clamp circuit 200 is connected between the output node 12A of the primary amplifier circuit 10A and the balanced-unbalanced conversion circuit 55, and clamp circuits 201 and 202 are connected to the output nodes 12B1 and 12B2 of the output-stage amplifier circuits 10B1 and 10B2, respectively.

[0187] [Ninth embodiment]

[0188] Next, refer to Fig.25 , an amplifier according to a ninth embodiment will be described. In the amplifier according to the ninth embodiment, the clamp circuit 20 according to any one of the first to sixth embodiments can be used.

[0189] Fig.25 1 is an equivalent circuit diagram of an amplifier according to the ninth embodiment. The amplifier according to the ninth embodiment includes an amplifier circuit 10A at the primary stage and amplifier circuits 10BC and 10BP at the output stage. The amplifier circuits 10BC and 10BP constitute a Doherty amplifier circuit, and the amplifier circuit 10BC and the amplifier circuit 10BP are biased to operate as a carrier amplifier and a peak amplifier, respectively.

[0190] The output node 12A of the amplifier circuit 10A at the initial stage is connected to the input node 11BC of the amplifier circuit 10BC, and is connected to the input node 11BP of the amplifier circuit 10BP via the phase shifter 56. The output node 12BP of the amplifier circuit 10BP is connected to the impedance matching circuit 95, and the output node 12BC of the amplifier circuit 10BC is connected to the impedance matching circuit 95 via the phase shifter 57. The phase shifters 56 and 57 delay the phase of the high-frequency signal by 90°, for example. The high-frequency signal RFout is output from the impedance matching circuit 95.

[0191] A clamp circuit 20C is connected between the output node 12BC of the amplifier circuit 10BC operating as a carrier amplifier and the ground potential, and a clamp circuit 20P is connected between the output node 12BP of the amplifier circuit 10BP operating as a peak amplifier and the ground potential. For example, the clamp circuits 20C and 20P may be configured as those according to the first embodiment ( Figure 1 A) Second embodiment ( Figure 3 A) Embodiment 3 ( Figure 7 )、The fourth embodiment( Fig.10 )、5th embodiment( Fig.12 ), or a clamp circuit 20 of a modified example thereof.

[0192] The clamp circuits 20C and 20P limit the output power of the amplifier circuit 10BC operating as a carrier amplifier and the amplifier circuit 10BP operating as a peak amplifier, respectively.

[0193] Next, the excellent effects of the ninth embodiment are described.

[0194] In the ninth embodiment, for the clamp circuits 20C and 20P, for example, the clamp circuits according to the first embodiment ( Figure 1 A) Second embodiment ( Figure 3 A) Embodiment 3 ( Figure 7 )、The fourth embodiment( Fig.10 )、5th embodiment( Fig.12 ), or a clamp circuit 20 of a modified example thereof, the output power limit amount can be finely adjusted. Thus, the output power limit amount can be adjusted so that the output power of the amplifier circuits 10BC and 10BP at the output stage does not exceed the breakdown limit and satisfies the requested output.

[0195] Next, refer to Fig.26 as well as Fig. 27 , a modified example of the 9th embodiment is described. Fig.26 as well as Fig. 27 It is an equivalent circuit diagram of an amplifier according to a variation of the ninth embodiment.

[0196] You can also Fig.26 As shown in the modified example, the clamp circuit 20 is connected between the output node 12A of the first-stage amplifier circuit 10A and the phase shifter 56. The clamp circuit 20 has, for example, the same configuration as that according to the sixth embodiment ( Fig.16 A) or a modified example thereof. No clamp circuit is connected to any of the output nodes 12BC and 12BP of the amplifier circuits 10BC and 10BP of the output stage. The clamp circuit 20 limits the power of the high-frequency signal input to the amplifier circuits 10BC and 10BP of the output stage. Thus, the output power of the amplifier circuits 10BC and 10BP of the output stage can be limited.

[0197] You can also Fig. 27 As shown in the modified example, clamp circuit 20 is connected between output node 12A of amplifier circuit 10A at the first stage and phase shifter 56, and clamp circuits 20C and 20P are connected to output nodes 12BC and 12BP of amplifier circuits 10BC and 10BP at the output stage, respectively.

[0198] [10th embodiment]

[0199] Next, refer to Fig.28 , the amplifier according to the tenth embodiment is described. Next, the amplifier according to the ninth embodiment ( Fig.25 ) common structure, the description will be omitted.

[0200] Fig.28 is an equivalent circuit diagram of an amplifier according to the tenth embodiment. Fig.25 ), the amplifier circuit 10BC operating as a carrier amplifier of the Doherty amplifier circuit and the amplifier circuit 10BP operating as a peak amplifier are amplifier circuits for single-ended signals. In contrast, in the tenth embodiment, the carrier amplifier 10DC and the peak amplifier 10DP constituting the Doherty amplifier circuit each include a differential amplifier circuit. The phase shifter 56 is arranged on the input side of the carrier amplifier 10DC and the peak amplifier 10DP. The high-frequency signal RFin is input to the carrier amplifier 10DC, and is input to the peak amplifier 10DP via the phase shifter 56.

[0201] The carrier amplifier 10DC includes an amplifier circuit 10A at the primary stage, a balanced-unbalanced conversion circuit 55, and amplifier circuits 10B1 and 10B2 at the output stage. The structures thereof are similar to those of the amplifier according to the eighth embodiment ( Fig. 22 ) have the same structure as the amplifier circuit 10A at the primary stage, the balanced-unbalanced conversion circuit 55, and the amplifier circuits 10B1 and 10B2 at the output stage. However, the amplifier circuits 10B1 and 10B2 at the output stage are biased to operate as carrier amplifiers.

[0202] A clamp circuit 200 is connected between the amplifier circuit 10A at the primary stage and the balanced-unbalanced conversion circuit 55. Clamp circuits 201 and 202 are connected to the output nodes 12B1 and 12B2 of the amplifier circuits 10B1 and 10B2 at the output stage, respectively. The structure of the clamp circuit 200 is similar to that of the amplifier according to the modified example of the eighth embodiment ( Fig.23 ) has the same structure as the clamp circuit 200 of the embodiment. The structures of the clamp circuits 201 and 202 are the same as those of the amplifier according to the eighth embodiment ( Fig. 22 ) have the same structure as the clamping circuits 201 and 202.

[0203] The basic structure of the peak amplifier 10DP is the same as that of the carrier amplifier 10DC, but the amplifier circuits 10B1 and 10B2 at the output stage of the peak amplifier 10DP are biased so as to operate as peak amplifiers.

[0204] The high-frequency signal output from the amplifier circuit 10B1 of the carrier amplifier 10DC and phase-adjusted by the phase shifter 571 is synthesized with the high-frequency signal output from the amplifier circuit 10B1 of the peak amplifier 10DP, and input to one terminal of the primary coil of the balanced-unbalanced conversion circuit 58. Similarly, the high-frequency signal output from the amplifier circuit 10B2 of the carrier amplifier 10DC and phase-adjusted by the phase shifter 572 is synthesized with the high-frequency signal output from the amplifier circuit 10B2 of the peak amplifier 10DP, and input to the other terminal of the primary coil of the balanced-unbalanced conversion circuit 58. For the phase shifters 571 and 572, for example, transformers can be used.

[0205] The balanced-unbalanced conversion circuit 58 converts the differential signal into a single-ended signal. The converted single-ended signal is output as a high-frequency signal RFout.

[0206] Next, the excellent effects of the tenth embodiment will be described.

[0207] In the tenth embodiment, the carrier amplifier 10DC and the peak amplifier 10DP include clamp circuits 200, 201, and 202, respectively. Fig.24 ) Similarly, the output power limit amount of the amplifier circuits 10B1 and 10B2 of the output stages of the carrier amplifier 10DC and the peak amplifier 10DP can be finely adjusted. Thus, the output power limit amount can be adjusted so that the output power of the amplifier circuits 10B1 and 10B2 of the output stage does not exceed the breakdown limit and satisfies the requested output.

[0208] Next, a modification of the tenth embodiment will be described.

[0209] It can also be combined with the ninth embodiment ( Fig.25) Similarly, the clamp circuit 200 connected between the amplifier circuit 10A at the primary stage and the balanced-unbalanced conversion circuit 55 is omitted, and the clamp circuits 201 and 202 connected to the output nodes 12B1 and 12B2 of the amplifier circuits 10B1 and 10B2 at the output stage, respectively, are left. Fig.26 ) Similarly, the clamping circuits 201, 202 respectively connected to the output nodes 12B1, 12B2 of the amplifier circuits 10B1, 10B2 at the output stage are omitted, leaving the clamping circuit 200 connected between the primary amplifier circuit 10A and the balanced-unbalanced conversion circuit 55.

[0210] The above-mentioned embodiments are for illustration only. It is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed. The same effects brought about by the same structures in multiple embodiments will not be mentioned one by one in each embodiment. Furthermore, the present invention is not limited by the above-mentioned embodiments. For example, various changes, improvements, combinations, etc. can be performed, which is self-evident to those skilled in the art.

[0211] Description of Reference Numerals

[0212] 10, 10A, 10B, 10C: high frequency power amplifier circuit (amplifier circuit);

[0213] 10B1, 10B2: amplifier circuit constituting a differential amplifier circuit;

[0214] 10BC: an amplifier circuit operating as a carrier amplifier;

[0215] 10BP: Amplifier circuit that operates as a peak amplifier;

[0216] 10DC: carrier amplifier;

[0217] 10DP: Peak amplifier;

[0218] 11, 11A, 11B, 11BC, 11BP: input nodes;

[0219] 12, 12A, 12B, 12B1, 12B2, 12BC, 12BP, 12C: output nodes;

[0220] 20, 20A, 20B, 20C, 20P: clamping circuit;

[0221] 20D: Diode multi-stage clamping circuit;

[0222] 21: Resistor-connected transistor;

[0223] 22: Transistor;

[0224] 22B: base layer;

[0225] 22C: collector layer;

[0226] 22E: emitter layer;

[0227] 23: base-collector resistance element;

[0228] 24B: base electrode;

[0229] 24C: collector electrode;

[0230] 24E: emitter electrode;

[0231] 25: diode;

[0232] 25A: anode layer;

[0233] 25C: cathode layer;

[0234] 26A: anode electrode;

[0235] 26C: cathode electrode;

[0236] 30: Variable resistance circuit;

[0237] 31: Switching element;

[0238] 32: resistance element;

[0239] 40B: base wiring;

[0240] 40C: Collector wiring;

[0241] 40D: Wiring;

[0242] 40E: emitter wiring;

[0243] 50: choke;

[0244] 55: Balanced-unbalanced conversion circuit;

[0245] 56, 57: Phase shifter;

[0246] 58: Balanced-unbalanced conversion circuit;

[0247] 80: semiconductor substrate;

[0248] 81: epitaxial layer;

[0249] 81C: conductive area;

[0250] 81I: component separation area;

[0251] 90: high frequency signal source;

[0252] 92: Impedance matching circuit;

[0253] 93: load;

[0254] 95: Impedance matching circuit;

[0255] 200, 201, 202: clamping circuit;

[0256] 571, 572: Phase shifter.

Claims

1. A clamping circuit connected between a node through which a high-frequency signal passes and a ground potential, wherein: The clamp circuit includes a plurality of clamp elements connected in multiple stages. Each of the plurality of clamp elements is turned on when a voltage higher than the rising edge voltage is applied. At least one of the plurality of clamp elements is formed of a resistor-connected transistor including a bipolar transistor and a base-collector resistor element connected between a base and a collector.

2. The clamping circuit according to claim 1, wherein: All of the plurality of clamp elements are formed by the resistance-connected transistors.

3. The clamping circuit according to claim 1, wherein: At least one of the plurality of clamping elements is formed of a diode.

4. The clamping circuit according to claim 3, wherein: At least one of the diodes is formed by a diode-connected bipolar transistor.

5. The clamping circuit according to any one of claims 1 to 4, wherein: Also includes: The variable resistance circuit is connected in parallel or series with respect to the base-collector resistance element included in at least one of the clamping elements composed of the resistance-connected transistor among the multiple clamping elements, so as to change the resistance value between the base and the collector of the resistance-connected transistor.

6. The clamping circuit according to claim 5, wherein: The variable resistance circuit is connected in parallel with the base-collector resistance element and includes a switch element and a resistance element connected in series with each other.

7. The clamping circuit according to claim 5 or 6, wherein: The clamp element to which the variable resistance circuit is connected among the plurality of clamp elements is connected to a middle stage or an end on the ground potential side of the plurality of clamp elements connected in multiple stages.

8. The clamping circuit according to any one of claims 1 to 7, wherein: At least two of the plurality of clamp elements are formed of the resistance-connected transistors, and the resistance value of the base-collector resistance element is different between the at least two clamp elements formed of the resistance-connected transistors.

9. The clamping circuit according to any one of claims 1 to 8, wherein: If the peak value of the high-frequency voltage generated between the node and the ground potential exceeds a given voltage value, the high-frequency voltage is turned on to limit the increase in the peak value of the high-frequency voltage between the node and the ground potential.

10. An amplifier comprising: a first high-frequency power amplifier circuit that amplifies a high-frequency signal input from an input node and outputs the amplified signal from an output node; and The clamp circuit according to any one of claims 1 to 9 is connected between one of the input node and the output node of the first high-frequency power amplifier circuit and a ground potential.

11. The amplifier according to claim 10, wherein A second high-frequency power amplifier circuit is further provided, and a high-frequency signal amplified by the second high-frequency power amplifier circuit is input to an input node of the first high-frequency power amplifier circuit.

12. An amplifier comprising: The first high-frequency power amplifier circuit and the second high-frequency power amplifier circuit amplify the high-frequency signal input from the input node and output it from the output node; The two clamp circuits according to any one of claims 1 to 9, connected between the output node of the first high-frequency power amplifier circuit and the ground potential and between the output node of the second high-frequency power amplifier circuit and the ground potential, respectively; and Balanced-unbalanced conversion circuit converts single-ended signal into differential signal. The differential signal converted by the balanced-unbalanced conversion circuit is input to an input node of the first high-frequency power amplifier circuit and an input node of the second high-frequency power amplifier circuit, respectively.

13. An amplifier comprising: The first high-frequency power amplifier circuit, the second high-frequency power amplifier circuit, and the third high-frequency power amplifier circuit amplify the high-frequency signal input from the input node and output it from the output node; The clamp circuit according to any one of claims 1 to 9, connected between the output node of the third high-frequency power amplifier circuit and the ground potential; and The balanced-unbalanced conversion circuit converts the single-ended signal output from the output node of the third high-frequency power amplifier circuit into a differential signal. The differential signal converted by the balanced-unbalanced conversion circuit is input to an input node of the first high-frequency power amplifier circuit and an input node of the second high-frequency power amplifier circuit, respectively.

14. An amplifier comprising: The first high-frequency power amplifier circuit and the second high-frequency power amplifier circuit amplify the high-frequency signal input from the input node and output it from the output node; and The two clamp circuits according to any one of claims 1 to 9 are connected between the output node of the first high-frequency power amplifier circuit and the ground potential and between the output node of the second high-frequency power amplifier circuit and the ground potential, respectively. The first high-frequency power amplifier circuit and the second high-frequency power amplifier circuit are respectively a carrier amplifier and a peak amplifier of a Doherty amplifier circuit.

15. An amplifier comprising: The first high-frequency power amplifier circuit, the second high-frequency power amplifier circuit, and the third high-frequency power amplifier circuit amplify the high-frequency signal input from the input node and output it from the output node; The clamp circuit according to any one of claims 1 to 9, connected between the output node of the third high-frequency power amplifier circuit and the ground potential; and Phase shifter, The first high-frequency power amplifier circuit and the second high-frequency power amplifier circuit are respectively a carrier amplifier and a peak amplifier of a Doherty amplifier circuit. The high-frequency signal output from the output node of the third high-frequency power amplifier circuit is input to an input node of one of the first high-frequency power amplifier circuit and the second high-frequency power amplifier circuit, and is input to an input node of the other through the phase shifter.

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