Synchronous audio communication and bus power supply over multiple pairs of cables and connectors

Abstract

In some examples of networks and methods, a data network includes nodes. The nodes comprise a master node (MN) and at least one child node. Each node includes a node transceiver. The node transceiver is operable to perform data communication according to a first network protocol to power data through the first pair of conductors. The physical layer includes a cable segment between each node (e.g., a cable segment of a bus). Each cable segment includes multiple pairs of conductors (e.g., pairs) and connectors at each end (e.g., 8P8C connectors), but other connectors with multiple pairs of conductors may also be used. A first pair of conductors (e.g., pin 4 and pin 5 connected to an 8P8C connector) implements a first network protocol between nodes. One or more of the remaining pair conductors provide supplemental power to the node.

Description

[0001] Introduced by merging

[0002] This application claims priority to U.S. Non-Provisional Application No. 18 / 346,226, filed on July 1, 202e, “Synchronous Audio Communications and Bus Power Over Multi-Pair Cables and Connectors,” which claims priority to U.S. Provisional Application No. 63 / 357,767, filed on July 1, 2022, “Synchronous Audio Communications and Bus Power Over CAT Cables with 8P8C Connectors.” The entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to systems and devices in daisy chain networks and / or point-to-point connection networks. Background Art

[0004] As electronic components decrease in size and performance expectations increase, more components are being included in equipment that was previously uninstrumented or lightly instrumented. In some environments, the communications infrastructure used to exchange signals between these components (e.g., in vehicles) requires thick cable bundles.

[0005] This disclosure is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. Further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing this system with some aspects of the invention described in the remainder of this application with reference to the accompanying drawings. Summary of the invention

[0006] Disclosed herein are systems and techniques for synchronizing audio communications and bus power in a network bus via a cable having an 8P8C connector. The cable may be a variation of a CAT cable, such as a Category 5 (CAT5), Category 6 (CAT6), Category 7 (CAT7), or Category 8 (CAT8) cable, a shielded cable, an unshielded cable, and the cable may be an Ethernet cable. The connector may be an 8-position I 8-conductor (8P8C) connector, such as an RJ45 connector. The network bus may be a two-wire bus. In some examples, the network bus provided herein applies bus power in a phased and negotiated manner and shares differential communication line pairs with power and return current. This is in stark contrast to Power over Ethernet (PoE), which is asynchronous and packet-based. The audio clock synchronization communication system as described herein provides many advantages. For example, it is less complex and allows for shorter delays. In addition, the power on the data line allows the communication cable to be reused for power, thereby avoiding additional cables for power wiring. The cable connector combination is inexpensive, has good digital communication performance, and is readily available in many retail stores. Therefore, as described herein, it is also desirable to use it for synchronous audio communications. Therefore, a system and technology are provided herein to reduce the complexity of PoE by providing different power over data line (PoD) schemes with methods for protecting PoD devices when PoE PSD devices are plugged in and protecting PoE devices when PoD devices are plugged in. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be best understood by the following detailed description in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry standard practice, various features are not necessarily drawn to scale and are for illustration purposes only. Where scale is shown explicitly or implicitly, it is provided only as an illustrative example. In other embodiments, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion. For ease of description, like reference numerals denote like structural elements. In the drawings of the accompanying drawings, embodiments are illustrated by way of example and not limitation.

[0008] For a more complete understanding of the nature and advantages of the present invention, please refer to the following detailed description of preferred embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of an illustrative two-wire communication system in accordance with various embodiments;

[0010] Figure 2 According to various embodiments, it may be included in Figure 1 A block diagram of a node transceiver in a node of a system;

[0011] Figure 3 According to various embodiments, Figure 1 A diagram of a portion of a synchronization control frame for communications in a system;

[0012] Figure 4 According to various embodiments, Figure 1 A diagram of a superframe of communication in a system;

[0013] Figure 5 It shows various embodiments Figure 1 Example formats of synchronization control frames in different operation modes of the system;

[0014] Figure 6 It shows various embodiments Figure 1 Example formats of synchronization response frames of a system in different operation modes;

[0015] Figure 7 According to various embodiments Figure 2 A block diagram of the various components of the bus protocol circuit;

[0016] Figure 8-11 shows an example of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein;

[0017] Fig.12 A ring topology of a two-wire bus and a unidirectional communication scheme thereon are shown according to various embodiments;

[0018] Fig.13 is a device that can be used as a Figure 1 A block diagram of a node or host device in a system;

[0019] Fig.14 is a flow chart of simultaneous audio communications and bus power over CAT cable according to various embodiments;

[0020] Figures 15A-15C is a diagram showing a circuit for simultaneous audio communication and bus power over a two-wire bus using a CAT cable having an 8P8C connector;

[0021] Fig.16 is a diagram showing a connector for a local power supply node;

[0022] Figures 17A-17C is a diagram showing a circuit for synchronous audio communication over a two-wire bus using a CAT cable with an 8P8C connector. DETAILED DESCRIPTION

[0023] Disclosed herein are systems and techniques for synchronizing audio communications and bus power in a network bus via a cable having an 8P8C connector. The cable may be a shielded or unshielded CAT cable, such as a Category 5 (CAT5), Category 6 (CAT6), Category 7 (CAT7), or Category 8 (CAT8) cable, and the cable may be an Ethernet cable. The connector may be a shielded or unshielded 8-position / 8-conductor (8P8C) connector, such as an RJ45 connector. The network bus may be a two-wire bus. In some examples, the network bus provided herein applies bus power in a phased and negotiated manner, and shares differential communication line pairs with power and return current. This is in stark contrast to PoE, which is asynchronous and packet-based.

[0024] Generally speaking, audio connections in studios and stages are analog and therefore susceptible to noise and interference. Audio stages and recording studios are expected to transition from using traditional analog wiring (e.g., a guitar cable with a single mono signal) to digital connections using multi-channel audio signals on the same cable (e.g., the sound of each of the 6 strings on a guitar can be picked up individually and communicated as 6 separate audio channels on the same cable). Building automation and conference rooms use CAT cables with 8P8C (RJ45) connectors to connect ceiling microphone arrays and speakers with Ethernet at distances of up to 100 meters. But Ethernet is an asynchronous, packet-based communication and is therefore not suitable for audio. Ethernet packets must be resynchronized and resynthesized to the audio clock and audio phase of each end node. Packet-based communications are inefficient and add additional, undesirable latency.

[0025] An audio clock synchronous communication system offers many advantages. It is less complex and allows for shorter latency. It is also highly desirable to power over the data line so that the communication cable can be reused for power, thus avoiding additional cables for power wiring. IEEE standardized PoE is complex and requires specialized PSE (power supply equipment) and PD (powered device) to communicate / negotiate with the power pulses outside the Ethernet PHY-MAC layer. CAT cables with 8P8C (RJ45) connectors are ubiquitous in Ethernet connections, sometimes with PoE voltages as high as negative 57V. The cable-connector combination is inexpensive, has good digital communication performance, and is readily available in many retail stores. As a result, it is desirable for synchronous audio communications not only in conference rooms, but also on stage, audio studios, and other digital audio wiring applications.

[0026] Systems and techniques are provided herein to reduce the complexity of PoE by providing a different power over data line scheme (PoD) with methods to protect PoD devices when a PoE PSD device is inserted and PoE devices when a PoD device is inserted. The PoD circuit does not need to support the power voltage span of PoE when a PoE device is accidentally inserted, nor does it have the complexity of PoE. In PoE, the differential wires in a pair of wires are biased together for power and the other pair of wires is biased for return current. In contrast, PoD biases one wire of the power pair and uses the other pair of wires as return current. Unlike Ethernet, which uses more expensive transformers, cost-effective inductors are used to inject bias voltage into the communication lines. In addition, as described herein, in some examples, only one pair of wires is used for communication, allowing the other pair of wires to carry the negotiated high bus voltage without the need for low-pass filtering (and no transformer coupling).

[0027] As described in this article, the communication path on the communication line is high-pass filtered through a series capacitor, while on the same line, the bias is caused by a low-pass filter on one line of the differential line pair and returned by a low-pass filter on the other line. The next online node extracts power through a low-pass filter in the form of an inductor and communicates through a high-pass filter in the form of a series capacitor. The next online node uses the bus power from the differential communication line for the bus transceiver and storage device (such as EEPROM). The current-limited low-voltage bus bias is applied to the communication line pair through a voltage regulator and current-limiting device or directly by a current-limiting voltage regulator. These devices have a power good (PG) or similar signal that indicates good operation only when there is no overcurrent. Overcurrent at the output of such a device will also reduce the output voltage, thereby limiting the power consumption of the overcurrent protection.

[0028] In the detailed description below, reference is made to the accompanying drawings forming a part of this document, wherein like numbers refer to like parts throughout, and wherein embodiments that can be practiced are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered restrictive.

[0029] Various operations may be described in sequence as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily dependent on the order. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0030] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0031] Various components may be referenced or described herein in the singular (eg, "processor," "peripheral device," etc.), but this is only for ease of discussion, and any element referenced in the singular may include a plurality of such elements in accordance with the teachings herein.

[0032] The description uses the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," and the like used in the embodiments of the present disclosure are synonymous. As used herein, the term "circuitry" may refer to, be part of, or include application specific integrated circuits (ASICs), electronic and optical circuits, processors (shared, dedicated, or groups) and / or memories (shared, dedicated, or groups) that execute one or more software or firmware programs, combinational logic circuits, and / or other suitable hardware that provides the described functionality.

[0033] Figure 1 1 is a block diagram of an illustrative half-duplex two-wire communication system 100 according to various embodiments. The system 100 includes a host 110, a master node 102-1, and at least one child node 1022. Figure 1 , three child nodes (0, 1, and 2) are shown. Figure 1 The depiction of three sub-nodes 102 - 2 is merely illustrative, and the system 100 may include one, two, or more sub-nodes 102 - 2 as desired.

[0034] The master node 102-1 may communicate with the child node 102-2 via a two-wire bus 106. The bus 106 may include different two-wire bus links between adjacent nodes along the bus 106, connecting the nodes along the bus 106 in a daisy-chain manner. For example, Figure 1 As shown, bus 106 may include a link coupling master node 102-1 to subnode 0, a link coupling subnode 0 to subnode 1, and a link coupling subnode 1 to slave node 2. In some embodiments, the links of bus 106 may each be formed by a single twisted pair (e.g., an unshielded twisted pair). In some embodiments, the links of bus 106 may each be formed by a coaxial cable (e.g., the core provides the "positive" wire, the shield provides the "negative" wire, and vice versa). The two-wire bus links together provide a complete electrical path (e.g., forward and return current paths), so there is no need to use additional ground or voltage supply lines.

[0035] The host 110 may include a processor that programs the master node 102-1 and acts as an initiator and receiver of various paid loads transmitted along the bus 106. In some embodiments, for example, the host 110 may be or may include a microcontroller. In particular, the host 110 may be a host for inter-integrated circuit sound (I2S) communications that occur along the bus 106. The host 110 may communicate with the master node 102-1 via an I2S / time division multiplexing (TDM) protocol, a serial peripheral interface (SPI) protocol, and / or an inter-integrated circuit (I2C) protocol. In some embodiments, the master node 102-1 may be a transceiver located in the same housing as the host 110 (e.g., see below). Figure 2 Node transceiver 120 discussed). The master node 102-1 can be programmed by the host 110 via the I2C bus for configuration and readback, and can be configured to generate clocks, synchronization, and framing for all child nodes 102-2. In some embodiments, an extension of the I2C control bus between the host 110 and the master node 1021 can be embedded in the data stream transmitted over the bus 106, allowing the host 110 to directly access registers and status information of one or more child nodes 102-2, and to enable long-distance I2C to I2C communication to allow the host 110 to control peripheral devices 108. In some embodiments, an extension of the SPI control bus between the host 110 and the master node 1021 can be embedded in the data stream transmitted over the bus 106, allowing the host 110 to directly access registers and status information of one or more child nodes 102-2, and to allow SPI to SPI or SPI to I2C long-distance communication to allow the host 110 to control peripheral devices 108. In embodiments where system 100 is included in a vehicle, host 110 and / or master node 102 - 1 may be included in a front end of the vehicle.

[0036] The master node 102-1 may generate a "downstream" signal (e.g., a data signal, a power signal, etc., transmitted from the master node 102-1 along the bus 106) and receive an "upstream" signal (e.g., transmitted toward the master node 102-1 along the bus 106). The master node 102-1 may provide a clock signal for synchronous data transmission over the bus 106. As used herein, "synchronous data" may include data (e.g., an audio signal) that is continuously streamed at fixed time intervals between two consecutive transmissions to / from the same node along the bus 106. In some embodiments, the clock signal provided by the master node 1021 may be derived from the I2S input provided by the host 110 to the master node 102-1. The child node 102-2 may be an addressable network connection point that represents a possible destination of a data frame transmitted downstream or upstream on the bus 106. The child node 102-2 may also represent a possible source of a downstream or upstream data frame. The system 100 may allow control information and other data to be transmitted from one node to the next in both directions over the bus 106. One or more of the sub-nodes 102 - 2 may also be powered by signals transmitted via the bus 106 .

[0037] Specifically, each of the master node 102-1 and the child node 102-2 may include a positive upstream terminal (denoted as "AP"), a negative upstream terminal (denoted as "AN"), a positive downstream terminal (denoted as "BP"), and a negative downstream terminal (denoted as "BN"). The positive downstream terminal and the negative downstream terminal of the node may be coupled to the positive upstream terminal and the negative upstream terminal of the adjacent downstream node, respectively. Figure 1 As shown, the master node 102-1 may include positive and negative upstream terminals, but these terminals may not be used; in other embodiments, the master node 102-1 may not include positive and negative upstream terminals. Figure 1 The child node 2 in the bus may include positive and negative downstream terminals, but these terminals may not be used; in other embodiments, the last child node 102-2 along the bus may not include positive and negative downstream terminals.

[0038] As discussed in detail below, the master node 102-1 may periodically send synchronization control frames downstream, optionally along with data for one or more child nodes 102-2. For example, the master node 102-1 may send one synchronization control frame per 1024 bits (representing a superframe) at a frequency of 48kHz, resulting in an effective bit rate of 49.152Mbps on the bus 106. Other rates may be supported, including, for example, 44.1kHz. The synchronization control frame may allow the child node 102-2 to identify the start of each superframe, and may also be combined with physical layer coding / signaling to allow each child node 102 / 2 to derive its internal operating clock from the bus 106. The synchronization control frame may include a preamble for signaling the start of synchronization, as well as control fields that allow various addressing modes (e.g., normal, broadcast, discovery), configuration information (e.g., writing registers of the child node 102-2), transmission of I2C information, transmission of SPI information, remote control of certain general purpose input / output (GPIO) pins at the child node 102-2, and other services. A portion of the synchronization control frame following the preamble and payload data may be scrambled to reduce the likelihood that information in the synchronization control frame will be mistaken for a new preamble and to flatten the spectrum of associated electromagnetic emissions.

[0039] The synchronization control frame may be passed between the child nodes 1022 (optionally along with other data, which may come from the master node 102-1, but which may alternatively or alternatively come from one or more upstream child nodes 1022 or from the child node 102-2 itself) until it reaches the last child node 102-2 (i.e. Figure 1 1) a child node 102-2 that has been configured by the master node 102-1 as the last child node 102-2, or has identified itself as the last child node 102-2. After receiving the synchronization control frame, the last child node 102-2 may send a synchronization response frame, followed by any data allowed to be sent (e.g., 24-bit audio samples in a specified time slot). The synchronization response frame may be passed upstream between child nodes 102-2 (optionally together with data from a downstream child node 102-2), and based on the synchronization response frame, each child node 102-2 is able to identify the time slot (if any) in which the child node 102-2 is allowed to transmit.

[0040] In some embodiments, one or more subnodes 102-2 in the system 100 may be coupled to and communicate with a peripheral device 108. For example, the subnode 102-2 may be configured to read data from and / or write data to the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, SPI, and / or I2C protocols, as described below. Although "peripheral device 108" may be represented in the singular herein, this is only for ease of discussion, and a single subnode 102-2 may be coupled to zero, one, or more peripheral devices. Examples of peripheral devices that may be included in the peripheral device 108 may include a digital signal processor (DSP), a field programmable gate array (FPGA), an ASIC, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a codec, a microphone, a microphone array, a speaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an environmental condition sensor (e.g., a temperature, humidity, and / or gas sensor), a wired or wireless communication transceiver, a display device (e.g., a touch screen display), a user interface component (e.g., a button, a dial, or other control), a camera (e.g., a video camera), a storage device, or any other suitable device that sends and / or receives data. This article discusses several examples of different peripheral configurations in detail.

[0041] In some embodiments, peripheral device 108 may include any device configured for I2S communication; peripheral device 108 may communicate with associated subnode 102-2 via I2S protocol. In some embodiments, peripheral device 108 may include any device configured for I2C communication; peripheral device 108 may communicate with associated subnode 102-2 via I2C protocol. In some embodiments, peripheral device 108 may include any device configured for SPI communication; peripheral device 108 may communicate with associated subnode 102-2 via SPI protocol. In some embodiments, subnode 102-2 may not be coupled to any peripheral device 108.

[0042] The child node 102-2 and its associated peripheral device 108 may be contained in separate housings and coupled via a wired or wireless communication connection, or may be contained in a common housing. For example, a speaker connected as a peripheral device 108 may be connected to the hardware of the associated child node 102-2 (e.g., as described below). Figure 2 The node transceiver 120 discussed is packaged together so that the hardware of the associated sub-node 102-2 is contained within a housing that includes other speaker components. This may be the case for any type of peripheral device 108.

[0043] As described above, the host 110 can communicate with and control the master node 102-1 using a multi-channel I2S, SPI, and / or I2C communication protocol. For example, the host 110 can transmit data to a frame buffer (not shown) in the master node 102-1 via I2S, and the master node 102-1 can read the data from the frame buffer and transmit the data along the bus 106. Similarly, the master node 102-1 can store data received via the bus 106 in the frame buffer and then send the data to the host 110 via I2S.

[0044] Each child node 102-2 may have internal control registers that may be configured via communications from the master node 102-1. Some such registers will be discussed in detail below. Each child node 102-2 may receive downstream data and may resend data further downstream. Each child node 102-2 may receive and / or generate upstream data and / or retransmit data upstream and / or add data to an upstream transaction.

[0045] Communication along the bus 106 may occur in periodic superframes. Each superframe may begin with a downstream synchronization control frame; be divided into periods of downstream transmission (also referred to as a "downstream portion"), upstream transmission (also referred to as an "upstream portion"), and no transmission (the bus 106 is not driven); and end before transmitting another downstream synchronization control frame. The master node 102-1 may be programmed (by the host 110) to have multiple downstream portions to send to one or more child nodes 102-2, and multiple upstream portions to receive from one or more child nodes 102-2. Each child node 102-2 may be programmed (by the master node 102-1) to have multiple downstream portions to retransmit downward along the bus 106, multiple downstream portions to be consumed, multiple upstream portions to retransmit upward along the bus 106, and multiple upstream portions where the child node 102-2 may transmit data received from the child node 102-2 from the associated peripheral device 108. Referring below Figure 2-12 Communications along bus 106 are discussed in greater detail.

[0046] Embodiments of the communication system 100 disclosed herein are unique in conventional communication systems because all child nodes 102-2 may receive output data via the bus 106 within the same superframe (e.g., all child nodes 102-2 may receive the same audio sample without sampling delays between nodes 102). In conventional communication systems, data is buffered and processed in each node and then passed downstream to the next node in the next frame. Thus, in these conventional communication systems, the delay in data transmission depends on the number of nodes (each node adds a delay of one audio sample). In the communication system 100 disclosed herein, the bus 106 may add only one delay cycle, regardless of whether the first or last child node 102-2 receives the data. The same is true for upstream communications; data may be available at the upstream node 102 in the next superframe, regardless of which child node 102-2 provided the data.

[0047] In addition, in embodiments of the communication system 100 disclosed herein, downstream data (e.g., downstream audio data) can be placed on the bus 106 by the master node 102-1 or any child node 102-2 upstream of the receiving child node 102-2; similarly, upstream data (e.g., upstream audio data) can be placed on the bus 106 by any child node 102-2 downstream of the receiving node 102 (i.e., the master node 102-1 or the child node 102-2). This capability allows the child node 102-2 to provide upstream and downstream data at a specific time (e.g., a specific audio sample time). For audio data, the data can be received in the next audio sample of any downstream or upstream node 102 without further delay (except for slight processing delays within superframe boundaries). As further discussed herein, control messages (e.g., in a synchronization control frame (SCF)) can be transmitted to the last node 102 (addressing a specific node 102 or broadcasting), and an upstream response (e.g., in a synchronization response frame (SRF)) can be created by the last downstream node 102 within the same superframe. The nodes 102 addressed by the SCF change the contents of the upstream SRF with their own responses. Therefore, within the same audio sample, control and response can be fully performed on multiple nodes 102. This is also in contrast to conventional communication systems, in which sampling delays are incurred between nodes (for relaying messages from one node to another).

[0048] Each of the master node 102 - 1 and the child node 102 - 2 may include a transceiver to manage communications between components of the system 100 . Figure 2 According to various embodiments, it may be included in Figure 11 is a block diagram of a node transceiver 120 in a node (e.g., master node 102-1 or child node 102-2) of system 100. In some embodiments, node transceiver 120 may be included in each node of system 100, and a control signal may be provided to node transceiver 120 via a main (MAIN) pin to indicate whether node transceiver 120 acts as a master node (e.g., when MAIN pin is high) or as a child node (e.g., when MAIN pin is low).

[0049] The node transceiver 120 may include an upstream differential signaling (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 may be coupled to the above referenced Figure 1 The positive and negative upstream terminals discussed above, the downstream DS transceiver 124 may be coupled to the previously referenced Figure 1 The positive and negative downstream terminals are described. In some embodiments, the upstream DS transceiver 122 can be a low voltage DS (LVDS) transceiver and the downstream DS transceiver 124 can be an LVDS transceiver. Each node in the system 100 can be AC ​​coupled to the bus 106 and can transmit data signals along the bus 106 (e.g., via the upstream DS transceiver 122 and / or the downstream DS transceiver 124) using a predetermined form of DS (e.g., LVDS or multi-point LVDS (MLVDS) or similar signaling) with appropriate encoding to provide timing information on the bus 106 (e.g., differential Manchester encoding, bi-phase mark encoding, Manchester encoding, non-return to zero, phase inversion with run limit (NRZI) encoding, or any other suitable encoding).

[0050] The upstream DS transceiver 122 and the downstream DS transceiver 124 may communicate with the bus protocol circuit 126, and the bus protocol circuit 126 may communicate with the phase-locked loop (PLL) 128 and the voltage regulator circuit 130, among other components. When the node transceiver 120 is powered on, the voltage regulator circuit 130 may issue a "power good" signal, which is used by the PLL 128 as a power-on reset.

[0051] As described above, one or more child nodes 102-2 in the system 100 can receive power transmitted over the bus 106 simultaneously with the data. For power distribution (which is optional, as some child nodes 102-2 can be configured to only provide local power to them), the master node 102-1 can apply a DC bias on the bus link between the master node 102-1 and the child node 0 (e.g., connecting one downstream terminal to a voltage source provided by a voltage regulator through a low-pass filter and grounding the other downstream terminal). The DC bias can be a predetermined voltage, such as 5 volts, 8 volts, the voltage of a car battery, or a higher voltage. Each successive child node 102-2 can selectively tap its upstream bus link to recover power (e.g., using the voltage regulator circuit 130). This power can be used to power the child node 102-2 itself (and one or more peripheral devices 108 optionally coupled to the child node 1022). The child node 102-2 can also selectively bias the bus link downstream for the next child node 102-2 online using power recovered from the upstream bus link or from the local power supply. For example, subnode 0 may use a DC bias on an upstream link of bus 106 to restore power to subnode 0 itself and / or one or more associated peripheral devices 108 , and / or subnode 0 may recover power from an upstream link of bus 106 to bias a downstream link of bus 106 .

[0052] Therefore, in some embodiments, each node in the system 100 can provide power to the following downstream nodes via the downstream bus link. The power supply of the nodes can be performed in sequence. For example, after discovering and configuring subnode 0 via bus 106, master node 102-1 can instruct subnode 0 to power the downstream link of its bus 106 so as to power subnode 1; after discovering and configuring subnode 1, master node 102-1 can instruct subnode 1 to power the downstream link of its bus 106 so as to power subnode 2 (for additional subnodes 102-2 coupled to bus 106, and so on). In some embodiments, one or more of subnodes 102-2 can be locally powered, rather than powered from its upstream bus link, or can be locally powered in addition to being powered from its upstream bus link. In some such embodiments, the local power supply of a given subnode 102-2 can be used to provide power to one or more downstream subnodes.

[0053] In some embodiments, the upstream bus interface circuit 132 may be disposed between the upstream DS transceiver 122 and the voltage regulator circuit 130, and the downstream bus interface circuit 131 may be disposed between the downstream DS transceiver 124 and the voltage regulator circuit 130. Since each link of the bus 106 may carry both AC (signal) and DC (power) components, the upstream bus interface circuit 132 and the downstream bus interface circuit 131 may separate the AC and DC components, provide the AC component to the upstream DS transceiver 122 and the downstream DS transceiver 124, and provide the DC component to the voltage regulator circuit 130. The AC coupling of the line side of the upstream DS transceiver 122 and the downstream DS transceiver 124 substantially isolates the transceivers 122 and 124 from the DC component on the line to allow high-speed bidirectional communication. As described above, the DC component may be tapped to obtain power, and the upstream bus interface circuit 132 and the downstream bus interface circuit 131 may include ferrites, common mode chokes, or inductors, for example, to reduce the AC component provided to the voltage regulator circuit 130. In some embodiments, upstream bus interface circuit 132 may be included in upstream DS transceiver 122 , and / or downstream bus interface circuit 131 may be included in downstream DS transceiver 124 ; in other embodiments, the filtering circuits may be external to transceivers 122 and 124 .

[0054] The node transceiver 120 may include a transceiver 127 for I2S, TDM, and PDM communications between the node transceiver 120 and an external device 155. Although "external device 155" may be represented in the singular herein, this is only for ease of explanation, and multiple external devices may communicate with the node transceiver 120 via the I2S / TDM / PDM transceiver 127. As known in the art, the I2S protocol is used to carry pulse code modulation (PCM) information (e.g., between audio chips on a printed circuit board (PCB)). As used herein, "I2S / TDM" may refer to the use of TDM to expand the I2S stereo (2-channel) content to multiple channels. As known in the art, PDM may be used for sigma-delta converters, in particular, the PDM format may represent an oversampled 1-bit sigma-delta ADC signal before decimation. The PDM format is typically used as the output format of a digital microphone. The I2S / TDM / PDM transceiver 127 may communicate with the bus protocol circuit 126 and the pins used to communicate with the external device 155. Figure 2 Six pins are shown, BCLK, SYNC, DTX[1:0] and DRX[1:0]; the BCLK pin can be used for the I2S bit clock, the SYNC pin can be used for the I2C frame synchronization signal, and the DTX[1:0] and DRX[1:0] pins are used for sending and receiving data channels respectively. Figure 2Two transmit pins (DTX[1:0]) and two receive pins (DRX[1:0]) are shown in FIG, but any desired number of receive and / or transmit pins may be used.

[0055] When the node transceiver 120 is included in the master node 102-1, the external device 155 may include the host 110, and the I2S / TDM / PDM transceiver 127 may provide an I2S slave (regarding BCLK and SYNC), which may receive data from the host 110 and send data to the host 110 in synchronization with the I2S interface clock of the host 110. Specifically, the I2S frame synchronization signal may be received at the SYNC pin as an input from the host 110, and the PLL 128 may use the signal to generate a clock. When the node transceiver 120 is included in the child node 102-2, the external device 155 may include one or more peripheral devices 108, and the I2S / TDM / PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC), which may control I2S communication with the peripheral device 108. In particular, the I2S / TDM / PDM transceiver 127 can provide an I2S frame synchronization signal as an output at the SYNC pin. Registers in the node transceiver 120 can determine which and how many I2S / TDM channels are transmitted as data time slots on the bus 106. A TDM mode (TDMMODE) register in the node transceiver 120 can store a value of how many TDM channels fit between consecutive SYNC pulses on the TDM transmit or receive pin. Combined with knowledge of the channel size, the node transceiver 120 can automatically set the BCLK rate to match the number of bits within the sampling time (e.g., 48kHz).

[0056] The node transceiver 120 may include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. Although "external device 157" may be represented in the singular herein, this is only for ease of explanation, and multiple external devices may communicate with the node transceiver 120 via the I2C transceiver 129. As is known in the art, the I2C protocol uses clock (SCL) and data (SDA) lines to provide data transmission. The I2C transceiver 129 may communicate with the bus protocol circuit 126 and the pins for communicating with the external device 157. Figure 2Four pins are shown, ADRI, ADR2, SDA, and SCL; when the node transceiver 120 acts as an I2C slave (e.g., when it is included in the master node 102-1), ADRI and ADR2 can be used to modify the I2C address used by the node transceiver 120, and SDA and SCL are used for I2C serial data and serial clock signals, respectively. When the node transceiver 120 is included in the master node 102-1, the external device 157 can include the host 110, and the I2C transceiver 129 can provide an I2C slave that can receive programming instructions from the host 110. In particular, the I2C serial clock signal can be received at the SCL pin as an input from the host 110 for register access. When the node transceiver 120 is included in the child node 102-2, the external device 157 may include the peripheral device 108, and the I2C transceiver 129 may provide an I2C master device to allow the I2C transceiver to program one or more peripheral devices according to instructions provided by the host 110 and transmitted to the node transceiver 120 via the bus 106. Specifically, the I2C transceiver 129 may provide an I2C serial clock signal as an output at the SCL pin.

[0057] The node transceiver 120 may include a transceiver 136 for SPI communication between the node transceiver 120 and an external device 138. Although the "external device 138" may be referred to in the singular herein, this is only for ease of explanation, and multiple external devices may communicate with the node transceiver 120 via the SPI transceiver 136. As is known in the art, the SPI protocol uses slave select (SS), clock (BCLK), master output-slave input (MOSI), and master input-slave output (MISO) data lines to provide data transmission, and the pins corresponding to these four lines are as shown in FIG. Figure 2As shown. The SPI transceiver 136 can communicate with the bus protocol circuit 126 and the pin for communicating with the external device 138. When the node transceiver 120 is included in the master node 102-1, the external device 138 can include the host 110 or another external device, and the SPI transceiver 136 can provide a SPI slave device, which can receive and respond to commands from the host 110 or other external devices. When the node transceiver 120 is included in the child node 102-2, the external device 138 can include a peripheral device 108, and the SPI transceiver 136 can provide a SPI master to allow the SPI transceiver 136 to send commands to one or more peripheral devices 108. The SPI transceiver 136 may include a read data first-in-first-out (FIFO) buffer and a write data FIFO buffer. The read data FIFO buffer can be used to collect data read from other nodes 102, and can be read by the external device 138 when the external device 138 sends an appropriate read command. The write data FIFO buffer may be used to collect write data from the external device 138 before transmitting the write data to another device.

[0058] The node transceiver 120 may include an interrupt request (IRQ) pin that communicates with the bus protocol circuit 126. When the node transceiver 120 is included in the master node 102-1, the bus protocol circuit 126 may provide an event-driven interrupt request to the host 110 via the IRQ pin. When the node transceiver 120 is included in the child node 102-2 (e.g., when the MSTR pin is low), the IRQ pin may be used as a GPIO pin with interrupt request capability. In addition Figure 2 In addition to the pins shown in , the node transceiver 120 may also include other pins (eg, as described below).

[0059] The system 100 may operate in any of a number of different operating modes. The nodes on the bus 106 may each have a register indicating which operating mode is currently enabled. Examples of various operating modes that may be implemented are described below. In the standby operating mode, bus activity is reduced to achieve global power savings; the only service required is a minimum downstream preamble to maintain PLL synchronization for each node (e.g., PLL 128). In the standby operating mode, read and write operations over the bus 106 are not supported. In the discovery operating mode, the master node 102-1 may send a predetermined signal along the bus 106 and wait for an appropriate response to map the topology of the child nodes 102-2 distributed along the bus 106. In the normal operating mode, the child node 102-2 may access full registers and may also access peripheral devices 108 over the bus 106. The normal mode may be globally configured by the host 110, with or without synchronized upstream data, and with or without synchronized downstream data.

[0060] Figure 3 1 is a diagram of a portion of a synchronization control frame 180 for communication in the system 100 according to various embodiments. Specifically, the synchronization control frame 180 can be used for data clock recovery and PLL synchronization, as described below. As described above, since communication on the bus 106 can occur in both directions, the communication can be time-multiplexed into a downstream portion and an upstream portion. In the downstream portion, the synchronization control frame and the downstream data can be sent from the master node 102-1, and in the upstream portion, the synchronization response frame and the upstream data can be sent from each child node 102-2 to the master node 102-1. The synchronization control frame 180 can include a preamble 182 and control data 184. Each child node 1022 can be configured to use the preamble 182 of the received synchronization control frame 180 as a time base for feeding to the PLL 128. To facilitate this, the preamble 182 does not follow the "rules" of the valid control data 184, so it can be easily distinguished from the control data 184.

[0061] For example, in some embodiments, the communication along bus 106 can be encoded using a clock-first, zero-difference Manchester encoding scheme. According to this encoding scheme, each bit time starts with a clock transition. If the data value is zero, the encoded signal transitions again in the middle of the bit time. If the data value is 1, the encoded signal does not transition again. Figure 5 The preamble 182 shown in FIG. 1 may violate the encoding protocol (e.g., by having clock transitions that do not occur at the beginning of bit times 5, 7, and 8), which means that the preamble 182 may not match any legal (e.g., correctly encoded) pattern of the control data 184. Furthermore, the preamble 182 cannot be reproduced by taking a legal pattern for the control data 184 and forcing the bus 106 high or low for a single bit time or multiple bit periods. Figure 5 The preamble 182 shown in FIG. 1 is illustrative only, and the synchronization control frame 180 may include different preambles 182 that may violate the encoding used by the control data 184 in any suitable manner.

[0062] The bus protocol circuit 126 may include a differential Manchester decoder circuit that operates on a clock recovered from the bus 106 and detects the synchronization control frame 180 to send a frame synchronization indicator to the PLL 128. In this manner, the synchronization control frame 180 may be detected without using a system clock or a higher speed oversampling clock. Thus, the child node 102-2 may receive a PLL synchronization signal from the bus 106 without requiring a crystal clock source at the child node 102-2.

[0063] As described above, communications along bus 106 may occur in periodic superframes. Figure 4 is a diagram of a superframe 190 according to various embodiments. Figure 6 As shown, a superframe may begin with a synchronization control frame 180. When the synchronization control frame 180 is used as a timing source for the PLL 128, the frequency at which the superframe is transmitted (the "superframe frequency") may be the same as the synchronization signal frequency. In some embodiments in which audio data is transmitted along the bus 106, the superframe frequency may be the same as the audio sampling frequency used in the system 100 (e.g., 48 kHz or 44.1 kHz), but any suitable superframe frequency may be used. Each superframe 190 may be divided into a downstream transmission period 192, an upstream transmission period 194, and a no-transmission period 196 (e.g., when the bus 106 is not driven).

[0064] exist Figure 4 , superframe 190 is shown as having an initial period 192 for downstream transmission and a later period 194 for upstream transmission. The downstream transmission period 192 may include a synchronization control frame 180 and X downstream data time slots 198, where X may be zero. As described above, substantially all signals on bus 106 may be line coded, and synchronization signals are forwarded downstream from master node 102-1 to the last child node 102-2 (e.g., child node 102-2C) in the form of a synchronization preamble 182 in the synchronization control frame 180. Downstream TDM synchronization data may be included in the X downstream data time slots 198 following the synchronization control frame 180. The downstream data slots 198 may have equal widths. As described above, PLL 128 may provide a clock that a node uses to time communications on bus 106. In some embodiments where bus 106 is used to transmit audio data, PLL 128 may operate at multiples of the audio sampling frequency (e.g., the audio sampling frequency is 1024 times, resulting in 1024 bit clocks in each superframe).

[0065] The period of upstream transmission 194 may include a synchronization response frame 197 and Y upstream data time slots 199, where Y may be zero. In some embodiments, each child node 102-2 may consume a portion of downstream data time slots 198. The last child node (e.g., Figure 1 The child nodes 102-2 in the superframe 190 may respond with a synchronization response frame 197 (after a predetermined response time stored in the register of the last child node). The upstream TDM synchronization data may be added by each child node 102-2 to the upstream data slot 199 directly after the synchronization response frame 197. The upstream data slots 199 may have equal widths. A child node 102-2 that is not the last child node (e.g., Figure 1 Child nodes 0 and 1) in may replace the received synchronization response frame 197 with their own upstream responses.

[0066] As described above, each downstream transmission may be preceded by a synchronization control frame 180. In some embodiments, the length of the synchronization control frame 180 may be 64 bits, although any other suitable length may be used. As described above, the synchronization control frame 180 may begin with a preamble 182. In some embodiments, when the child node 102-2 retransmits the synchronization control frame 180 to the downstream child node 102-2, the preamble 182 may be generated by the transmitting child node 102-2 rather than being retransmitted.

[0067] The control data 184 of the synchronization control frame 180 may include fields containing data for controlling transactions on the bus 106. Examples of these fields are discussed below. Figure 5 Some embodiments are shown in FIG. Figure 5 Example formats of synchronization control frames 180 in normal mode, I2C mode, and discovery mode are shown according to various embodiments. In some embodiments, a completely different preamble 182 or synchronization control frame 180 may be used in standby mode so that the child node 102-2 does not need to receive all synchronization control frames 180 before sending a transition to normal mode.

[0068] In some embodiments, the synchronization control frame 180 may include a count (CNT) field. The CNT field may have any suitable length (e.g., 2 bits) and may be incremented (modulo the length of the field) from the value used in the previous superframe. A child node 102-2 that receives an unexpected CNT value may be programmed to return an interrupt.

[0069] In some embodiments, the synchronization control frame 180 may include a node addressing mode (NAM) field. The NAM field may have any suitable length (e.g., 2 bits) and may be used to control access to registers of child nodes 102-2 via bus 106. In normal mode, registers of child nodes 102-2 may be read from and / or written to based on the ID of child nodes 102-2 and the address of the register. Broadcast transactions are writes that should be performed by each child node 102-2. In some embodiments, the NAM field may provide four node addressing modes, including "none" (e.g., data is not addressed to any particular child node 102-2), "normal" (e.g., data is unicast to a particular child node 102-2 specified in the address field discussed below), "broadcast" (e.g., addressed to all child nodes 102-2), and "discovery".

[0070] In some embodiments, the synchronization control frame 180 may include an I2C field. The I2C field may have any suitable length (e.g., 1 bit) and may be used to indicate that the downstream transmission period 192 includes an I2C transaction. The I2C field may indicate that the host 110 has provided an instruction to remotely access the peripheral device 108, which acts as an I2C slave device relative to the associated child node 102-2.

[0071] In some embodiments, the synchronization control frame 180 may include a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to indicate which child node is being addressed for normal and I2C access. In discovery mode, this field may be used to program the identifier of the newly discovered child node 102-2 in the node ID register of the child node 102-2. As described below, when the master node 102-1 discovers the child node 102-2, each child node 102-2 in the system 100 may be assigned a unique ID. In some embodiments, the master node 102-1 does not have a node ID, while in other embodiments it may have a node ID. In some embodiments, a child node 102-2 (e.g., Figure 1 0) will be child node 0, and each successive child node 102-2 will have a number that is 1 higher than the previous child node. However, this is merely illustrative, and any suitable child node identification system may be used.

[0072] In some embodiments, the synchronization control frame 180 may include a read / write (RW) field. The RW field may have any suitable length (eg, 1 bit) and may be used to control whether a normal access is a read (eg, RW=1) or a write (eg, RW==0).

[0073] In some embodiments, the synchronization control frame 180 may include an address field. The address field may have any suitable length (e.g., 8 bits) and may be used to address a specific register of the child node 102-2 via the bus 106. For I2C transactions, the address field may be replaced with I2C control values, such as START / STOP, WAIT, RW, and DATA VLD. For discovery transactions, the address field may have a predetermined value (e.g., Figure 5 shown).

[0074] In some embodiments, the synchronization control frame 180 may include a data field. The data field may have any suitable length (e.g., 8 bits) and may be used for normal, I2C, and broadcast writes. The RESPCYCS value multiplied by 4 may be used to determine how many cycles a newly discovered node should be allowed to pass between the start of a received synchronization control frame 180 and the start of a transmitted synchronization response frame 197. When the NAM field indicates discovery mode, the node address and data fields discussed below may be encoded as a RESPCYCS value that, when multiplied by a suitable optional multiplier (e.g., 4), indicates in bits the time from the end of the synchronization control frame 180 to the start of the synchronization response frame 197. This allows the newly discovered child node 102-2 to determine the appropriate time slot for upstream transmission.

[0075] In some embodiments, the synchronization control frame 180 may include a cyclic redundancy check (CRC) field. The CRC field may have any suitable length (e.g., 16 bits) and may be used to transmit a CRC value of the control data 184 of the synchronization control frame 180 following the preamble 182. In some embodiments, the CRC may be calculated according to a CCITT-CRC error detection scheme.

[0076] In some embodiments, at least a portion of the synchronization control frame 180 between the preamble 182 and the CRC field may be scrambled to reduce the likelihood that the bit sequence in that interval will periodically match the preamble 182 (and thus may be misinterpreted by the child node 102-2 as the beginning of a new superframe 190), as well as to reduce electromagnetic radiation as described above. In some such embodiments, the CNT field of the synchronization control frame 180 may be used by the scrambling logic to ensure that the scrambled field is scrambled differently between each superframe. Various embodiments of the system 100 described herein may omit scrambling.

[0077] In addition to or in lieu of the scrambling and / or error coding techniques described above, other techniques may be used to ensure that the preamble 182 can be uniquely identified by the child node 102-2, or to reduce the likelihood that the preamble 182 will appear elsewhere in the synchronization control frame 180. For example, a longer synchronization sequence may be used to reduce the likelihood that the specific encoding of the remainder of the synchronization control frame 180 will match it. Additionally or alternatively, the remainder of the synchronization control frame may be constructed so that the synchronization sequence cannot occur, such as by fixing a "0" or "1" value at an appropriate position.

[0078] The master node 102-1 may send read and write requests to the child node 102-2, including requests specific to communication on the bus 106 and I2C requests. For example, the master node 102-1 may send a read and write request (indicated using the RW field) to one or more designated child nodes 1022 (using the NAM and Node fields), and may indicate whether the request is a request to the child node 102-2 that is specific to the bus 106, an I2C request to the child node 102-2, or an I2C request to be passed to an I2C-compatible peripheral device 108 coupled to the child node 102-2 at one or more I2C ports of the child node 102-2.

[0079] Turning to upstream communications, a synchronization response frame 197 may begin each upstream transmission. In some embodiments, the length of the synchronization response frame 197 may be 64 bits, but any other suitable length may be used. The synchronization response frame 197 may also include a preamble, as described above with reference to the preamble 182 of the synchronization control frame 180, followed by a data portion. At the end of the downstream transmission, the last child node 102-2 on the bus 106 may wait until the RESPCYCS counter expires and then begin transmitting the synchronization response frame 197 upstream. If the upstream child node 102-2 has been targeted by a normal read or write transaction, the child node 102-2 may generate its own synchronization response frame 197 and replace the frame received from the downstream. If any child node 102-2 does not see a synchronization response frame 197 from a downstream child node 102-2 at the expected time, the child node 102-2 will generate its own synchronization response frame 197 and begin sending it upstream.

[0080] The data portion of the synchronization response frame 197 may include fields containing data for transmitting response information back to the master node 102-1. Examples of these fields are discussed below. Figure 6 Some embodiments are shown in FIG. Figure 6 Example formats of the synchronization response frame 197 in normal mode, I2C mode, and discovery mode according to various embodiments are shown.

[0081] In some embodiments, the synchronization response frame 197 may include a count (CNT) field. The CNT field may have any suitable length (eg, 2 bits) and may be used to transmit the value of the CNT field in a previously received synchronization control frame 180.

[0082] In some embodiments, the synchronization response frame 197 may include an acknowledgment (ACK) field. The ACK field may have any suitable length (e.g., 2 bits) and may be inserted by the child node 102-2 to acknowledge a command received in a previous synchronization control frame 180 when the child node 102-2 generates the synchronization response frame 197. Example indicators that may be transmitted in the ACK field include wait, acknowledge, not acknowledge (NACK), and retry. In some embodiments, the size of the ACK field may be set to be used by the child node 102-2 to send an acknowledgement that it has received and processed the broadcast message (e.g., by sending a broadcast acknowledgement to the master node 102-1). In some such embodiments, the child node 102-2 may also indicate whether the child node 102-2 has data to transmit (e.g., for demand-based upstream transmission, such as non-TDM input from a keyboard or touch screen, or for priority upstream transmission, such as when the child node 102-2 wishes to report an error or emergency).

[0083] In some embodiments, the synchronization response frame 197 may include an I2C field. The I2C field may have any suitable length (eg, 1 bit) and may be used to transmit the value of the I2C field in a previously received synchronization control frame 180.

[0084] In some embodiments, the synchronization response frame 197 may include a node field. The node field may have any suitable length (eg, 4 bits) and may be used to send the ID of the child node 102-2 that generated the synchronization response frame 197.

[0085] In some embodiments, the synchronization response frame 197 may include a data field. The data field may have any suitable length (e.g., 8 bits), and its value may depend on the type of transaction and the ACK response of the child node 1022 that generates the synchronization response frame 197. For a discovery transaction, the data field may include the value of the RESPCYCS field in the previously received synchronization control frame 180. When the ACK field indicates NACK, or when the synchronization response frame 197 is responding to a broadcast transaction, the data field may include a broadcast acknowledgement (BA) indicator (where the last child node 102-2 may indicate whether the broadcast write was received without error), a discovery error (DER) indicator (indicating whether the newly discovered child node 102-2 in the discovery transaction matches the existing child node 102-2), and a CRC error (CER) indicator (indicating whether the NACK is caused by a CRC error).

[0086] In some embodiments, the synchronization response frame 197 may include a CRC field. The CRC field may have any suitable length (eg, 16 bits) and may be used to send a CRC value for the portion of the synchronization response frame 197 between the preamble and the CRC field.

[0087] In some embodiments, synchronization response frame 197 may include an interrupt request (IRQ) field. The IRQ field may have any suitable length (eg, 1 bit) and may be used to indicate that an interrupt has been signaled from child node 102-2.

[0088] In some embodiments, the synchronization response frame 197 may include an IRQ node (IRQNODE) ​​field. The IRQNODE field may have any suitable length (e.g., 4 bits) and may be used to send the ID of the child node 102-2 that has signaled the interrupt presented by the IRQ field. In some embodiments, the child node 102-2 that generates the IRQ field inserts its own ID into the IRQNODE field.

[0089] In some embodiments, the synchronization response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have any suitable length (eg, 4 bits) and may be used to transmit a CRC value for the IRQ and IRQNODE fields.

[0090] In some embodiments, the synchronization response frame 197 may include an IRQ field, an IRQNODE field, and a CRC-4 field as the last bits (e.g., the last 10 bits) of the synchronization response frame 197. As described above, these interrupt-related fields may have CRC protection in the form of CRC-4 (and therefore not protected by the previous CRC field). Any child node 102-2 that needs to send an interrupt signal to the master node 102-1 will insert its interrupt information into these fields. In some embodiments, a child node 102-2 with an interrupt pending may have a higher priority than any child node 102-2 downstream that also has an interrupt pending state. The last child node 102-2 along the bus 106 (e.g., Figure 1 The child node 2 in the last child node 102-2 can always fill these interrupt fields. If the last child node 102-2 has no pending interrupt, the last child node 102-2 can set the IRQ bit to 0, set the IRQNODE field to its node ID, and provide a correct CRC-4 value. For convenience, the synchronous response frame 197 that communicates the interruption can be referred to as an "interrupt frame" in this article.

[0091] In some embodiments, at least a portion of the synchronization response frame 197 between the preamble 182 and the CRC field may be scrambled to reduce transmission. In some such embodiments, the CNT field of the synchronization response frame 197 may be used by scrambling logic to ensure that the scrambled field is scrambled differently between each superframe. Various embodiments of the system 100 described herein may omit scrambling.

[0092] In addition to or in lieu of the scrambling and / or error coding techniques described above, other techniques may be used to ensure that the preamble 182 can be uniquely identified by the child node 102-2, or to reduce the likelihood that the preamble 182 will appear elsewhere in the synchronization response frame 197. For example, a longer synchronization sequence may be used to reduce the likelihood that the particular encoding of the remainder of the synchronization response frame 197 will match it. Additionally or alternatively, the remainder of the synchronization response frame may be structured so that the synchronization sequence cannot occur, such as by placing a fixed "0" or "1" value on the appropriate bit.

[0093] Figure 7 According to various embodiments Figure 2 102-2, associated with a synchronous control frame, or an I2C device when the bus protocol circuit 126 is included in the master node 102-1) and the control circuit 154 is a block diagram of a bus protocol circuit 126. The bus protocol circuit 126 may include a control circuit 154 to control the operation of the node transceiver 120 according to the protocol of the bus 106 described herein. Specifically, the control circuit 154 can control the generation of synchronization frames for transmission (e.g., synchronization control frames or synchronization response frames as described above), the processing of received synchronization frames, and the execution of control operations specified in the received synchronous control frames. The control circuit 154 may include programmable registers as described below. The control circuit 154 can create and receive synchronization control frames, react appropriately to received messages (e.g., when the bus protocol circuit 126 is included in the child node 102-2, associated with a synchronization control frame, or when the bus protocol circuit 126 is included in the master node 102-1, associated with an I2C device), and adjust the framing to different operating modes (e.g., normal, discovery, standby, etc.).

[0094] When the node transceiver 120 is preparing data for transmission along the bus 106, the preamble circuit 156 can be configured to generate a preamble for the synchronization frame for transmission and receive the preamble from the received synchronization frame. In some embodiments, the downstream synchronization control frame preamble can be sent by the master node 102-1 once every 1024 bits. As described above, one or more child nodes 102-2 can synchronize with the downstream synchronization control frame preamble and generate a local phase-aligned master clock from the preamble.

[0095] The CRC insertion circuit 158 ​​may be configured to generate one or more CRCs for the synchronization frames for transmission. The frame / compression circuit 160 may be configured to obtain input data from the I2S / TDM / PDM transceiver 127 (e.g., from a frame buffer associated with the transceiver 127), the I2C transceiver 129, and / or the SPI transceiver 136, optionally compress the data, and optionally generate parity bits or error correction codes (ECC) for the data. The multiplexer (MUX) 162 may multiplex the preamble, synchronization frames, and data from the preamble circuit 156 into a stream for transmission. In some embodiments, the transmission stream may be scrambled by the scrambling circuit 164 before transmission.

[0096] For example, in some embodiments, the frame / compression circuit 160 may apply a floating point compression scheme. In such embodiments, the control circuit 154 may send 3 bits to indicate how many repeated sign bits there are in the number, followed by the sign bit and N-4 data bits, where N is the size of the data to be transmitted over the bus 106. The master node 102-1 may configure the use of data compression when desired.

[0097] In some embodiments, the received stream entering the node transceiver 120 can be descrambled by the descrambling circuit 166. The demultiplexer (DEMUX) 168 can demultiplex the preamble, synchronization frame, and data from the received stream. The CRC check circuit 159 on the receiving side can check whether the received synchronization frame has a correct CRC. When the CRC check circuit 159 identifies a CRC failure in the incoming synchronization control frame 180, the control circuit 154 can be notified of the failure, and any control command in the control data 184 of the synchronization control frame 180 will not be executed. When the CRC check circuit 159 identifies a CRC failure in the incoming synchronization response frame 197, the control circuit 154 can be notified of the failure, and an interrupt can be generated to be transmitted to the host 110 in an interrupt frame. The deframing / decompression circuit 170 can accept received data, optionally check its parity, optionally perform error detection and correction (e.g., single error correction-double error detection (SECDED)), optionally decompress the data, and can write the received data to the I2S / TDM / PDM transceiver 127 (e.g., a frame buffer associated with the transceiver 127), the I2C transceiver 129, and / or the SPI transceiver 136.

[0098] As described above, upstream and downstream data may be transmitted along bus 106 in TDM data time slots within superframe 190. Control circuit 154 may include registers dedicated to managing these data slots on bus 106, several examples of which are discussed below. When control circuit 154 is included in master node 102-1, the values ​​in these registers may be programmed into control circuit 154 by host 110. When control circuit 154 is included in child node 102-2, the values ​​in these registers may be programmed into control circuit 154 by master node 102-1.

[0099] In some embodiments, the control circuit 154 may include a downstream time slot (DNSLOTS) register. When the node transceiver 120 is included in the master node 102-1, the register may hold the value of the total number of downstream data time slots. The register may also define the number of data time slots that will be used by the I2S / TDM / PDM transceiver 127 in the master node 102-1 for combining I2S / TDM / CDM reception. In the child node 102-2, the register may define the number of data time slots that are passed downstream to the next child node 102-2 before or after adding the locally generated downstream time slots, as discussed in further detail below with reference to LDNSLOTS.

[0100] In some embodiments, control circuit 154 may include a local downstream time slot (LDNSLOTS) register. This register may not be used in master node 102-1. In child node 102-2, this register may define the number of data time slots that child node 102-2 will use without retransmission. Or, this register may define the number of time slots that child node 102-2 can contribute to the downstream link of bus 106.

[0101] In some embodiments, the control circuit 154 may include an upstream time slot (UPSLOTS) register. In the master node 102-1, this register may hold the value of the total number of upstream data time slots. This register may also define the number of time slots that the I2S / TDM / PDM transceiver 127 in the master node 102-1 will use for I2S / TDM transmissions. In the child node 102-2, this register may define the number of data slots that are passed upstream before the child node 1022 begins to add its own data.

[0102] In some embodiments, the control circuit 154 may include a local upstream time slot (LUPSLOTS) register. This register may not be used in the master node 102-1. In the child node 102-2, this register may define the number of data time slots that the child node 102-2 will add to the data received from the downstream before sending it upstream. This register may also define the number of data time slots that the I2S / TDM / PDM transceiver 127 in the child node 102-2 will use to combine the I2S / TDM / CDM reception.

[0103] In some embodiments, the control circuit 154 may include a broadcast downstream time slot (BCDNSLOTS) register. This register may not be used in the master node 102-1. In the child node 102-2, this register may define the number of broadcast data time slots. In some embodiments, the broadcast data time slot may always appear at the beginning of the data field. The data in the broadcast data time slot can be used by multiple child nodes 102-2 and can be passed downstream in all child nodes 102-2, whether they are used or not.

[0104] In some embodiments, the control circuit 154 may include a time slot format (SLOTFMT) register. This register may define the data format for upstream and downstream transmissions. The data size of the I2S / TDM / PDM transceiver 127 may also be determined by this register. In some embodiments, the valid data size includes 8, 12, 16, 20, 24, 28, and 32 bits. This register may also include bits to enable floating point compression of downstream and upstream traffic. When floating point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size on the bus 106. When the data slot is enabled, all nodes in the system 100 may have the same SLOTFMT value, and the nodes may be programmed via a broadcast write so that all nodes will be updated with the same value.

[0105] Figure 8-11 1 shows an example of information exchange along bus 106 according to various embodiments of the bus protocol described herein. Specifically, Figure 8-11 An embodiment is shown in which each sub-node 102-2 is coupled to one or more speakers and / or one or more microphones as peripherals 108. This is merely illustrative, as any desired arrangement of peripherals 108 may be coupled to any particular sub-node 102-2 in accordance with the techniques described herein.

[0106] first, Figure 8 Signaling and timing considerations for bidirectional communications on bus 106 are shown according to various embodiments. Figure 8The child nodes 102-2 depicted in FIG. 1 have different numbers of sensor / actuator elements, and thus different amounts of data may be sent to or received from each child node 102-2. Specifically, child node 1 has two elements, child node 4 has four elements, and child node 5 has three elements, and thus the data transmitted by the master node 102-1 includes two time slots for child node 1, four time slots for child node 4, and three time slots for child node 5. Similarly, child node 0 has three elements, child node 2 has three, child node 3 has three elements, child node 6 has one element, and child node 7 has four elements, and thus the data transmitted upstream by these child nodes 102-2 includes a corresponding number of time slots. It should be noted that there need not be a one-to-one correlation between elements and time slots. For example, a microphone array having three microphones included in a peripheral device 108 may include a DSP that combines signals from the three microphones (and possibly also information received from the master node 102-1 or other child nodes 1022) to produce a single data sample, which may correspond to a single time slot or multiple time slots, depending on the type of processing.

[0107] exist Figure 8 In , the master node 102-1 sends an SCF followed by data from the speaker coupled to a particular child node 102-2 (SD). Each successive child node 1022 forwards the SCF and also forwards at least any data addressed to a downstream child node 102-2. A particular child node 102-2 may forward all data, or may delete data addressed to that child node 102-2. When the last child node 102-2 receives the SCF, the child node 102-2 may optionally send an SRF followed by any data that the child node 102-2 is permitted to send. Each successive child node 102-2 forwards the SRF along with any data from the downstream child node 102-2 and optionally inserts data from one or more microphones coupled to the particular child node 102-2 (MD). In . Figure 8 In the example of Figure 8 ) sends data and sends data from child nodes 7, 6, 3, 2, and 0 (in Fig. 9 The microphone array (shown in the figure) receives data.

[0108] Fig. 9 Schematically illustrates dynamically removing data from downstream transmissions and inserting data into upstream transmissions from the perspective of downstream DS transceiver 124 in accordance with various embodiments. Fig. 9 In Figure 8As shown, master node 102-1 sends the SCF, followed by the data (SD) of subnodes 1, 4, and 5 in reverse order (e.g., subnode 5's data is followed by subnode 4's data, which is followed by subnode 1's data, etc.) (see the row labeled MAIN). When subnode 1 receives the transmission, subnode 1 deletes its own data and forwards only the SCF to subnode 2, followed by the data of subnodes 5 and 4. Subnodes 2 and 3 forward the data intact (see the row labeled SUB 2), so that the data forwarded by subnode 1 is received by subnode 4 (see the row labeled SUB 3). Subnode 4 deletes its own data and forwards only the SCF to subnode 5, followed by the data of subnode 5, and similarly, subnode 5 deletes its own data and sends only the SCF to subnode 6. Subnode 6 forwards the SCF to subnode 7 (see the row labeled SUB 6).

[0109] At this point, child node 7 sends the SRF and its data to child node 6 (see the row labeled SUB 6). Child node 6 forwards the SRF along with the data from child node 7 and its own data to child node 5, which in turn sends the SRF along with the data from child nodes 6 and 7 to child node 4. Child node 4 has no data to add, so it simply forwards the data to child node 3 (see the row labeled SUB 3), which forwards the data along with its own data to child node 2 (see the row labeled SUB 2). Child node 1 has no data to add, so it forwards the data to child node 0, which forwards the data along with its own data. As a result, master node 102-1 receives the SRF and subsequently receives data from child nodes 7, 6, 3, 2, and 0 (see the row labeled MAIN).

[0110] Fig.10 Another example of dynamically removing data from a downstream transmission and inserting data into an upstream transmission from the perspective of a downstream DS transceiver 124 is shown. Fig. 9 As shown, although Fig.10 In FIG. 1 , the child nodes 102 - 2 are coupled with sensors and actuators as peripheral devices 108 , so that the master node 102 - 1 sends data downstream to all child nodes 102 - 2 and receives data from all child nodes 102 - 2 . Fig.10 In the , data is sorted according to the node address of its destination or source. The data slots marked as "Y" can be used for data integrity checking or data correction.

[0111] Fig.11 Another example of dynamically removing data from a downstream transmission and inserting data into an upstream transmission from the perspective of a downstream DS transceiver 124 is shown. Fig. 9 As shown, although Fig.11In the example, data is transmitted downstream and upstream in order rather than in reverse order. The buffering at each child node 102-2 allows data to be selectively added, deleted and / or forwarded.

[0112] As described above, each child node 102-2 may remove data from a downstream or upstream transmission and / or may add data to a downstream or upstream transmission. Thus, for example, a master node 102-1 may send a separate data sample to each of a plurality of child nodes 102-2, and each such child node 102-2 may remove its data sample and forward only the data intended for a downstream child node 102-2. On the other hand, a child node 102-2 may receive data from a downstream child node 102-2 and forward that data along with the additional data. One advantage of transmitting as little information as necessary is that the amount of power consumed by the system 100 as a whole is reduced.

[0113] The system 100 may also support broadcast transmissions (and multicast transmissions) from the master node 102-1 to the child nodes 102-2, particularly by configuring the downstream time slot usage of the child nodes 102-2. Each child node 102-2 may process the broadcast transmission and pass it to the next child node 102-2, although a particular child node 102-2 may "consume" the broadcast message (i.e., not pass the broadcast transmission to the next child node 102-2).

[0114] The system 100 may also support upstream transmissions (e.g., from a particular child node 102-2 to one or more other child nodes 102-2). Such upstream transmissions may include unicast, multicast, and / or broadcast upstream transmissions. Through upstream addressing, as described above with reference to downstream transmissions, a child node 102-2 may determine whether to delete data from an upstream transmission and / or whether to pass an upstream transmission to a next upstream child node 102-2 based on the configuration of the upstream timeslot usage of the child node 102-2. Thus, for example, in addition to passing data to the master node 1021, data may also be passed by a particular child node 102-2 to one or more other child nodes 102-2, or as an alternative to passing data to the master node 102-2. For example, such a child-child relationship may be configured via the master node 102-1.

[0115] Thus, in various embodiments, the child node 102-2 can operate as an active / intelligent repeater node with the ability to selectively forward, discard, and add information. The child node 102-2 can generally perform such functions without having to decode / check all data, because each child node 102-2 knows the relevant time slots in which it will receive / send data, and can therefore delete data from or add data to the time slots. Although the child node 102-2 may not need to decode / check all data, the child node 102-2 can generally re-time the data it sends / forwards. This can improve the robustness of the system 100.

[0116] In some embodiments, bus 106 can be configured for unidirectional communication in a ring topology. For example, Fig.12 An arrangement 1200 of a master node 102-1 and four child nodes 102-2 in a ring topology according to various embodiments is shown, and signaling and timing considerations for unidirectional communication in the arrangement 1200 are shown. In such an embodiment, the node transceiver 120 in the node may include a receive-only transceiver (MAIN IN) and a transmit-only transceiver (MAIN OUT) instead of two bidirectional transceivers for upstream and downstream communications. Fig.12 In the link layer synchronization scheme shown, the master node 102-1 sends the SCF 180, optionally followed by the "downstream" data 120-2 for the three speakers coupled to the respective child nodes 102-2 (the data for the different speakers may be arranged in any suitable order, as described above with reference to Figure 8-11 ), and each successive child node 102-2 forwards the synchronization control frame 180 and any "upstream" data from the previous child node 102-2 and its own "upstream" information to provide an "upstream" signal 1204 (e.g., the data from the eight different microphones may be arranged in any suitable order, as described above with reference to Figure 8-11 discussed).

[0117] As described herein, data may be communicated between elements of system 100 in any of a variety of ways. In some embodiments, data may be sent upstream by child node 102-2 (e.g., using data slot 199) or downstream by child node 102-2 or master node 102-1 (e.g., using data slot 198) as part of a set of synchronized data slots. The amount of such data may be adjusted by varying the number of bits in a data slot or including additional data slots. Data may also be communicated within system 100 by inclusion in synchronization control frame 180 or synchronization response frame 197. Data transferred in this manner may include I2C control data from the host 110 (with responses from the peripheral device 108 associated with the child node 102-2); access to registers of the child node 102-2 (e.g., for discovering and configuring slots and interfaces), which may include write access from the host 110 / master node 102-1 to the child node 102-2 and read access from the child node 102-2 to the host 110 / master 102-1; and event signaling from the peripheral device 108 to the host 110 via interrupts. In some embodiments, a GPIO pin may be used to pass information from the child node 1022 to the master node 102-1 (e.g., by having the master node 102-1 poll the GPIO pin via I2C, or by having the node transceiver 120 of the child node 102-2 generate an interrupt at an interrupt request pin). For example, in some such embodiments, the host 110 can send information to the master node 102-1 via I2C, and the master node 102-1 can then send the information to the child node 102-2 via the GPIO pin. Any type of data transmitted over the bus 106 discussed herein can be transmitted using any one or more of these communication paths. Other types of data and data communication techniques within the system 100 may be disclosed herein.

[0118] The embodiments of the present disclosure may be implemented into a system using any suitable hardware and / or software to configure as desired. Fig.13 A device 1300 is schematically shown according to various embodiments, which may be used as a host or a node (eg, host 110, master node 102-1, or child node 102-2) in system 100. As shown in FIG. Fig.13 1 shows multiple components included in the device 1300, but any one or more of these components may be omitted or duplicated according to application requirements.

[0119] Furthermore, in various embodiments, the device 1300 may not include Fig.13, but the device 1300 may include interface circuitry for coupling to one or more components. For example, the device 1300 may not include the display device 1306, but may include display device interface circuitry (e.g., a connector and driver circuitry), to which the display device 1306 may be coupled. In another set of examples, the device 1300 may not include the audio input device 1324 or the audio output device 1308, but may include audio input or output device interface circuitry (e.g., a connector and supporting circuitry), to which the audio input device 1324 or the audio output device 1308 may be coupled.

[0120] According to any embodiment disclosed herein, the device 1300 may include a node transceiver 120 for managing communications along the bus 106 when the device 1300 is coupled to the bus 106. The device 1300 may include a processing device 1302 (e.g., one or more processing devices), which may be included in the node transceiver 120 or separate from the node transceiver 120. As used herein, the term "processing device" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1302 may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptographic processors, or any other suitable processing devices. The device 1300 may include a memory 1304, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile storage (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive.

[0121] In some embodiments, memory 1304 may be used to store working and permanent copies of programming instructions to cause device 1300 to perform any suitable technique disclosed herein. In some embodiments, machine-accessible media (including non-transitory computer-readable storage media), methods, systems, and devices for performing the above techniques are illustrative examples of embodiments disclosed herein for communicating over a two-wire bus. For example, instructions may be stored on a computer-readable medium (e.g., memory 1304) that, when executed by one or more processing devices included in processing device 1302, cause device 1300 to perform any technique disclosed herein.

[0122] In some embodiments, the device 1300 may include another communication chip 1312 (e.g., one or more other communication chips). For example, the communication chip 1312 may be configured to manage wireless communications for data transmission to and from the device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation over a non-solid medium. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not.

[0123] The communication chip 1312 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), Long Term Evolution (LTE) project and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an abbreviation for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. One or more communication chips 1312 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The one or more communication chips 1312 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The one or more communication chips 1312 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 1312 may operate according to other wireless protocols. The device 1300 may include an antenna 1322 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0124] In some embodiments, the communication chip 1312 can manage wired communications using protocols other than the protocols of the bus 106 described herein. Wired communications can include electrical, optical, or any other suitable communication protocol. Examples of wired communication protocols that can be enabled by the communication chip 1312 include Ethernet, controller area network (CAN), I2C, media-oriented systems transport (MOST), or any other suitable wired communication protocol.

[0125] As described above, the communication chip 1312 may include a plurality of communication chips. For example, the first communication chip 1312 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth, and the second communication chip 1312 may be dedicated to long-range wireless communication such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 1312 may be dedicated to wireless communication, and the second communication chip 1312 may be dedicated to wired communication.

[0126] Device 1300 may include battery / power circuitry 1314. Battery / power circuitry 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of device 1300 to an energy source separate from device 1300 (e.g., AC line power, voltage provided by a car battery, etc.). For example, battery / power circuitry 1314 may include the battery / power circuitry described above with reference to FIG. Figure 2 The upstream bus interface circuit 132 and the downstream bus interface circuit 131 are discussed and can be charged by the bias voltage on the bus 106.

[0127] Device 1300 may include a display device 1306 (or corresponding interface circuitry as described above). Display device 1306 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0128] Device 1300 may include an audio output device 1308 (or corresponding interface circuitry as described above). Audio output device 1308 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0129] Device 1300 may include an audio input device 1324 (or corresponding interface circuitry as described above). Audio input device 1324 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0130] Device 1300 may include a GPS device 1318 (or corresponding interface circuitry as described above). GPS device 1318 may communicate with a satellite-based system and may receive the location of device 1300, as is known in the art.

[0131] Device 1300 may include another output device 1310 (or corresponding interface circuitry as described above). Examples of other output devices 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. In addition, any suitable peripheral device in the peripheral devices 108 discussed herein may be included in another output device 1310.

[0132] The device 1300 may include another input device 1320 (or corresponding interface circuitry as described above). Examples of other input devices 1320 may include an accelerometer, a gyroscope, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, or a radio frequency identification (RFID) reader. In addition, any suitable one of the sensors or peripherals 108 discussed herein may be included in another input device 1320.

[0133] Any suitable device among the display, input, output, communication, or storage devices described above with reference to device 1300 may be used as peripheral device 108 in system 100. Alternatively or additionally, suitable devices among the display, input, output, communication, or storage devices described above with reference to device 1300 may be included in a host (e.g., host 110) or a node (e.g., master node 102-1 or child node 102-2).

[0134] Elements of the system 100 may be selected and configured to provide audio and / or light control via the bus 106. In some embodiments, the system 100 may be configured to function as a light control system in a vehicle or other environment, with a lighting device (e.g., a stripline light emitting diode (LED) or other LED device) used as a peripheral device 108 communicating with a node 102 along the bus 106; data may be communicated via the bus 106 to control the color, intensity, duty cycle, and / or other parameters of the lighting device. In some embodiments, the system 100 may be configured to function as an audio control system in a vehicle or other environment, with a microphone or other device including an accelerometer used as a peripheral device 108 communicating with a node 102 along the bus 106; data from the accelerometer may be communicated via the bus 106 to control other peripheral devices 108 along the bus 106. For example, a large spike in acceleration data or other predetermined acceleration data pattern may be used to trigger a processing device coupled to a node 102 to produce a sound effect, such as a cowbell or drumbeat; the sound effect may be output by a speaker coupled to the processing device and / or a speaker coupled to another node 102 along the bus 106. Some embodiments of system 100 may combine any of the lighting control and / or audio control techniques disclosed herein.

[0135] Although the various embodiments described above describe the system 100 in a vehicle setting, this is merely illustrative, and the system 100 may be implemented in any desired setting. For example, in some embodiments, a "suitcase" implementation of the system 100 may include a portable housing that includes the required components of the system 100; such an implementation may be particularly suitable for portable applications, such as a portable karaoke or entertainment system.

[0136] Figure 14-1 8 shows an example system and technique for synchronous audio communication and bus powering via a CAT cable with an 8P8C connector. The cable can be a shielded or unshielded TIA CAT cable, such as a Category 5 (CAT5), Category 6 (CAT6), Category 7 (CAT7), or Category 8 (CAT8) cable, and the cable can be an Ethernet cable. The connector can be an 8-position / 8-conductor (8P8C) shielded or unshielded connector, such as an RJ45 connector. The network bus can be a two-wire bus. (For example, in an embodiment of system 100). In some examples, the network bus provided herein applies bus power in a phased and negotiated manner and shares differential communication line pairs with power and return. This is in stark contrast to PoE, which is asynchronous and packet-based.

[0137] Generally speaking, audio connections in studios and stages are analog and therefore susceptible to noise and interference. Audio stages and recording studios are expected to transition from using traditional analog wiring (e.g., a guitar cable with a single mono signal) to digital connections using multi-channel audio signals on the same cable (e.g., the sound of each of the 6 strings on a guitar can be picked up individually and communicated as 6 separate audio channels on the same cable). Building automation and conference rooms use CAT cables with 8P8C (RJ45) connectors to connect ceiling microphone arrays and speakers with Ethernet at distances of up to 100 meters. But Ethernet is an asynchronous, packet-based communication and is therefore not suitable for audio. Ethernet packets must be resynchronized and resynthesized to the audio clock and audio phase of each end node. Packet-based communications are inefficient and add additional, undesirable latency.

[0138] An audio clock synchronous communication system offers many advantages. It is less complex and allows for shorter latency. It is also highly desirable to provide power over the data line, so that the communication cable can be reused for power, thus avoiding additional cables for power wiring. IEEE standardized PoE is complex and requires specialized PSE and PD to communicate / negotiate with the power pulses outside the Ethernet PHY-MAC layer. CAT cables with 8P8C (RJ45) connectors are ubiquitous in Ethernet connections, sometimes with PoE voltages as high as negative 57V. The cable-connector combination is inexpensive, has good digital communication performance, and is readily available in many retail stores. As a result, it is desirable for synchronous audio communications not only in conference rooms, but also on stage, audio studios, and other digital audio wiring applications.

[0139] Systems and techniques are provided herein to reduce the complexity of PoE by providing a different scheme for power over data lines (PoD) with methods to protect PoD devices when a PoE PSE device is inserted and PoE devices when the PoD device is not inserted. The PoD circuit does not need to support the power voltage span of PoE when a PoE device is accidentally inserted, nor does it have the complexity of PoE. In PoE, the differential wires in a pair of wires are biased together for power and the other pair of wires is biased for return current. In contrast, PoD biases one wire of the power pair and uses the other pair of wires as return current. Unlike Ethernet, which uses more expensive transformers, cost-effective inductors are used to inject bias voltage into the communication lines. In addition, as described herein, in some examples, only one pair of wires is used for communication, allowing the other pair of wires to carry the negotiated high bus voltage without the need for low-pass filtering (and no transformer coupling).

[0140] The communication path on the communication line is high pass filtered by a series capacitor, while on the same line, the bias is caused by a low pass filter on one line of the differential line pair and returned by a low pass filter on the other line. The next online node extracts power through a low pass filter in the form of an inductor and communicates through a high pass filter in the form of a series capacitor. The next online node uses the bus power from the differential communication line for the bus transceiver and storage devices (such as EEPROM). A current limited low voltage bus bias is applied to the communication line pair through a voltage regulator and current limiting device or directly by a current limited voltage regulator. These devices have a PG or similar signal that will only signal good operation when there is no overcurrent. Overcurrent at the output of such a device will also reduce the output voltage, thereby limiting the power consumption of the overcurrent protection.

[0141] In various implementations, a method for providing simultaneous audio communications and bus power over a CAT cable with an 8P8C connector includes several steps. First, current is limited and a low voltage bus bias is applied to the communication wire pair. In some examples, the low voltage bus bias is applied with a slow ramp. An overcurrent event (e.g., a shorted wire) prevents entry to the next step, and periodic retries may be attempted after a waiting period. Connecting to an Ethernet device is considered an overcurrent event because there is a short circuit in the communications transformer on the differential wire pair.

[0142] Secondly, start communication and discover the next online node. If communication cannot be established, it is likely that there is no connection to a valid node. After waiting for a while, you can try to retry periodically from the first step.

[0143] Third, read the next in-line memory (e.g., EEPROM) to obtain information about the node and node capabilities, including power capabilities. If it does not match the expected content, there may be an unsupported device. After waiting for a while, you can try to retry from the first step periodically.

[0144] Fourth, apply high voltage and high power to the other bus, depending on the power supply capabilities of the next online node. This can be performed as part of rediscovery, and it may involve a PFET or NFET and a charge pump with a slow ramp mode to prevent excessive current consumption during the charging of the capacitors of the bus-powered nodes. Line current protection can be applied through a sense series resistor to prevent overcurrent conditions if the connector is not handled properly. Line diagnostics connected to the sense resistor and FET switches can determine if there is a break or short circuit. If there is a line diagnostic problem, you can try to retry from step 1 periodically after waiting for a period of time.

[0145] Fifth, once the high voltage is provided, the next in-line node can power the device with that voltage and can provide a derived low voltage current limited bias to the following link to repeat the process with the following node, thereby discovering and even powering multiple daisy-chained nodes.

[0146] The above sequence uses a current-limited low-current, low-voltage source to test the link. Therefore, this method prevents overcurrent from damaging the Ethernet transformer (when an Ethernet device is accidentally plugged in) or creating a fire hazard in the event of a hard short. Figures 15A-15C , 16 and 17A-17C, the pinout is used such that if a PoE device is plugged into a PoD device, it will also immediately see a short circuit and withdraw power to the connector.

[0147] Fig.14 1400 is a flowchart of a method for a discovery sequence applied at a master node of a network bus. First, a low voltage, low current bias is applied to the downstream communication line (if not previously applied). Then, it is determined whether a power good (or similar) signal from a low voltage, low current voltage regulator is present. The PG signal indicates that there is no overcurrent. In some examples, the method searches for a PG signal within a selected time period, and if no PG signal is detected within the selected time period, it is determined that there is no PG signal. If there is no PG signal, the method jumps to the last step, which periodically (e.g., every second) retries the method from the first step. If a PG signal is present, a downstream node is discovered. Then, it is determined whether the downstream node discovery is successful. If the downstream node discovery is unsuccessful, the method jumps to the last step as described above.

[0148] If the downstream node discovery is successful, the method continues by reading the memory contents (e.g., EEPROM contents) of the discovered downstream node to obtain node identification and node capability information. Node capabilities may include whether the node is locally powered or bus powered, and an indication of whether high voltage is used, as well as the amount of power used to operate the node.

[0149] Once the node information is read, it is determined whether the discovered downstream node is supported. If the downstream node is not supported, the method jumps to the last step as described above. If the downstream node is supported, it is determined whether the downstream node uses a high bus power voltage and whether the requested high bus power pressure can be provided. If the node does use a high bus power voltage and can provide the requested high bus power, the method continues to attempt to apply a high voltage to the 8P8C connector pin that carries the high voltage. This may also be part of the rediscovery. Line diagnostics are performed to determine if there are any overcurrent issues. If there are any overcurrent issues (or if the line diagnostics are not normal), the method jumps to the penultimate step and turns off the downstream high voltage bus power, and then continues with the last step as described above. If the line diagnostics are normal and there are no overcurrent issues, the downstream node is fully initialized, and in some examples, the peripheral devices are enabled. Similarly, if the downstream node does not use a high bus power voltage, the method skips the high voltage application and line diagnostics steps and continues to fully initialize the downstream node.

[0150] Next, it is determined whether HV=1 or the downstream node is locally powered and whether there are more nodes to discover. If not, the bus is fully discovered and the method ends. In some examples, the method can still be retried periodically to check if other nodes have been added. If so, the downstream node will become the node that discovers the next downstream node and the method will restart from the beginning.

[0151] Figures 15A-15C is a block diagram of a system for synchronizing audio communication and bus power according to various embodiments of the present disclosure. Specifically, Fig.15A A master node 1502 is shown connected to a bus supply subnode 1504 via an 8P8C connector 1506. The 8P8C connector includes eight pins arranged in four pairs. In various examples, pin 1 is paired with pin 2, pin 3 is paired with pin 6, pin 4 is paired with pin 5, and pin 7 is paired with pin 8. In some examples, pins 2 and 3 are connected to each other but biased differently. In some examples, pins 4 and 5 form a communication channel. The twist of pins 4 and 5 is tight.

[0152] An Ethernet cable is used, but bus biasing for Ethernet or PoE is not used. Therefore, a typical Ethernet connector plugged into connector 1506 will see a short circuit. For example, pins 1 and 2 of connector 1506 form a twisted pair, with pin 1 connected to ground and pin 2 having a positive power supply. However, in a typical Ethemet connector, pins 1 and 2 go into a transformer, so it is transformer coupled. Therefore, if the master node 1502 is plugged into a typical Ethemet connector, it will see a short circuit between pins 1 and 2 because it will check the transformer. Therefore, if the master node or child node of the present disclosure is plugged into a typical Ethemet connector, a short circuit will occur. Similarly, if a PoE device is plugged into connector 1806, it will see a short circuit.

[0153] Fig. 15B Detailed architecture of the master node 1502 according to various embodiments of the present disclosure is shown. Fig. 15C Detailed architecture of a bus powered subnode 1504 is shown in accordance with various embodiments of the present disclosure.

[0154] exist Fig. 15B In the example, a voltage regulator (e.g., a 5V voltage regulator) or a current limiter is used to ensure that when there is a short circuit, the bias is as weak as possible (e.g., 50mA maximum) and the circuit is turned off. The bias (e.g., 50mA) is sufficient to power the child nodes and, in some examples, the EEPROM. The EEPROM can provide information about the node, as described above with respect to Fig.14 as described in the method.

[0155] Once the child node is found and approved, the NFET (NFET1) connected to pins 2, 3, and 7 can provide a voltage to provide bus power. For example, the voltage can be 24 volts. The voltage provides the full bus power capability to the child node. In addition, if Fig. 15C As shown, the voltage drives a voltage regulator (eg, a 5V regulator) coupled to the next child node, and when the next child node is discovered and approved, the NFET in the child node may be turned on to provide voltage to the next child node.

[0156] Fig.16is a diagram showing an architecture for isolation on the A side of a local power supply node according to various embodiments of the present disclosure. The subnode SN can use a local power supply instead of a bus power supply. Such a local power supply can be a DC power supply from a wall-mounted transformer with a rectifier (simplified as a transformer in the local power supply diagram). In such a node, a supplementary bus power supply is not used, but wiring may or may not be provided. Here, a differential signal transformer on the communication line ensures electrical isolation of the subnode from the upstream subnode. The signal transformer consists of two windings facing the connector and two windings facing the transceiver. The winding facing the transceiver is directly (or indirectly, such as through a capacitor) connected at the midpoint and capacitively coupled to a local ground or a local bias point. The other end of the winding is connected to the transceiver as an AC coupled (through a transformer) communication signal. The outer tail of the winding facing the connector is connected to the connector. The inner tail of the winding facing the connector is an AC coupled slot capacitor and provides a resistive termination to match the impedance of the cable. The inner tail of the winding facing the connector is also connected (through a resistor) to the optocoupler LED. This allows the secondary side of the optocoupler to sense the bus bias (“A-side sensing”). It uses this as a power enable signal to the voltage regulator or power gating device of the locally powered node. This is a method of achieving galvanically isolated remote power by combining galvanic isolation, differential and common mode line termination, and bus bias sensed by the upstream node. The upstream node only provides the bus bias when it wants to enable the downstream node.

[0157] Figures 17A-17C is a diagram showing the architecture of a local power supply subnode. Fig.16 and 17A -17C, a locally powered subnode includes an optocoupler that acts as a wake-up for the subnode, so the node is not powered unless turned on.

[0158] In various examples, the master node can include a negative side (low side) switch so that line diagnostics can be performed.

[0159] In some examples, the NFET in the main node can include a charge pump to make the NFET more efficient. If the voltage builds up too much due to the current, the switch can be opened to prevent further voltage buildup.

[0160] Likewise, in the master node, while looking for a short to ground through the VSENSEP and VSENSEN pins, both the positive and negative wires are charged with a bias voltage and a limited current is applied to ground. Now without the N-side switch, the load capacitor connection to the 24V supply is now differential. The load capacitor is raised to ground to avoid false detection of a short to ground. Because the differential capacitor is charged, more current is provided. A diode and resistor are included to raise VSENSEP to more than 1 volt from ground. Once it is determined that there is no short, 24 volts is applied to the NFET, and the diode and resistor help prevent the 24 volts from flowing back to VIN.

[0161] Select Example

[0162] Example 1 provides a system for synchronous communication and power supply via a network bus, including: a master node, a sub-node, and an eight-pin connector.

[0163] Example 2 includes the subject matter according to any of the preceding and / or following embodiments, and

[0164] Example 3 includes the subject matter according to any of the preceding and / or following examples, and further provides that the child node is coupled to a peripheral device in any two-wire communication system disclosed herein.

[0165] Example 4 provides a method according to any of the preceding and / or following examples, wherein the peripheral device includes one or more microphones.

[0166] Example 5 provides a system according to any of the preceding and / or following examples, further comprising a two-wire bus, wherein the memory is located on a network bus subnode.

[0167] Changes and implementation

[0168] Thus, having described several aspects and embodiments of the present technology, it should be understood that various changes, modifications, and improvements will be readily made by those of ordinary skill in the art. These changes, modifications, and improvements are intended to be within the spirit and scope of the technology described in this application. For example, those of ordinary skill in the art will readily envision various other means and / or structures for performing the functions described herein and / or obtaining the results and / or one or more advantages, and each of these changes and / or modifications is considered to be within the scope of the embodiments described herein.

[0169] Those skilled in the art will recognize, or be able to ascertain using only routine experimentation, many equivalents to the specific embodiments described herein. Therefore, it should be understood that the above-described embodiments are presented by way of example only, and that within the scope of the appended claims and their equivalents, embodiments of the invention may be practiced in a manner other than that specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and / or methods described herein, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the scope of the present disclosure.

[0170] The above summarizes the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person of ordinary skill in the art (PHOSITA) to better understand the various aspects of the present disclosure. Certain well-understood terms and underlying technologies and / or standards may be referenced without detailed description. It is expected that PHOSITA will have or have access to background knowledge or information on these technologies and standards sufficient to practice the teachings of the present disclosure.

[0171] PHOSITA will understand that they can easily use this disclosure as a basis for designing or modifying other processes, structures or variations to achieve the same purposes and / or the same advantages of the embodiments described herein. PHOSITA will also recognize that such equivalent constructions will not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to this document without departing from the spirit and scope of the present disclosure.

[0172] The above embodiments may be implemented in any of a variety of ways. One or more aspects and embodiments of the present application involving the execution of a process or method may utilize program instructions executable by a device (eg, a computer, processor, or other device) to perform or control the process or method.

[0173] In this regard, the various inventive concepts may be embodied as a computer-readable storage medium (or multiple computer-readable storage media) (e.g., a computer memory, one or more floppy disks, optical disks, optical disks, tapes, flash memory, circuit configurations in field programmable gate arrays or other semiconductor devices, or other tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement one or more of the various embodiments described above.

[0174] The computer readable medium may be transportable so that the program stored thereon can be loaded onto one or more different computers or other processors to implement the above-mentioned various aspects. In some embodiments, the computer readable medium may be a non-transitory medium.

[0175] Note that the activities discussed above with reference to the accompanying drawings apply to any integrated circuit involved in signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), particularly those that can execute specialized software programs or algorithms, some of which may be related to processing digitized real-time data.

[0176] In some cases, the teachings of the present disclosure may be encoded into one or more tangible, non-transitory computer-readable media having executable instructions stored thereon that, when executed, instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. Where the teachings herein are at least partially embodied in a hardware device (such as an ASIC, IP block, or SoC), the non-transitory media may include a hardware device programmed with logic to perform the methods or functions disclosed herein. These teachings may also be practiced in the form of register transfer level (RTL) or other hardware description languages ​​(such as VHDL or Verilog), which may be used to program a manufacturing process to produce the disclosed hardware elements.

[0177] In example implementations, at least some parts of the processing activities outlined herein may also be implemented in software. In certain embodiments, one or more of these features may be implemented in hardware provided outside the elements of the disclosed drawings, or may be merged in any appropriate manner to achieve the desired function. Various components may include software (or reciprocating software) that may be coordinated to achieve the operations described herein. In other embodiments, these elements may include any suitable algorithm, hardware, software, component, module, interface, or an object that contributes to its operation.

[0178] Any appropriately configured processor component can execute any type of instruction associated with data to implement the operations detailed herein. Any processor disclosed herein can convert an element or article (e.g., data) from one state or thing to another state and thing. In another example, some activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein can be a certain type of programmable processor, programmable digital logic (e.g., FPGA, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), including digital logic, software, code, electronic instructions, flash memory, optical disk, CD-ROM, DVD-ROM, magnetic card or optical card ASIC, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.

[0179] In operation, the processor may store information in any suitable type of non-transitory storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or, where appropriate, in any other suitable component, device, element, or object based on specific needs. In addition, based on specific needs and implementations, information tracked, sent, received, or stored in the processor may be provided in any database, register, table, cache, queue, control list, or storage structure, all of which may be referenced in any suitable time frame.

[0180] Any memory items discussed herein should be interpreted as being included in the broad sense of the term "memory". Similarly, any potential processing elements, modules, and machines described herein should be interpreted as being included in the broad sense of "microprocessor" or "processor". In addition, in various embodiments, the processors, memories, network cards, buses, storage devices, related peripherals, and other hardware elements described herein may be implemented by processors, memories, and other related devices that are configured by software or firmware to emulate or virtualize the functions of these hardware elements.

[0181] Furthermore, it should be understood that a computer may be implemented in any of a variety of forms, such as, by way of non-limiting example, a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. In addition, a computer may be embedded in a device that is not generally considered a computer but has appropriate processing capabilities, including a personal digital assistant (PDA), a smart phone, a mobile phone, an iPad, or any other suitable portable or fixed electronic device.

[0182] In addition, a computer may have one or more input and output devices. These devices may be used, among other things, to present a user interface. Examples of output devices that may be used to provide a user interface include a printer or display screen for visual presentation of output, and a speaker or other sound generating device for auditory presentation of output. Examples of input devices that may be used for a user interface include a keyboard and a pointing device, such as a mouse, a touch pad, and a digitizing tablet. As another example, a computer may receive input information through speech recognition or other audible formats.

[0183] Such computers can be interconnected by one or more networks of any suitable form, including local area networks or wide area networks, such as enterprise networks, and intelligent networks (IN) or the Internet. Such networks can be based on any suitable technology and can operate according to any suitable protocol, and can include wireless networks or wired networks.

[0184] Computer executable instructions may be in various forms, such as program modules that are executed by one or more computers or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Typically, in various embodiments, the functionality of program modules may be combined or distributed as desired.

[0185] The term "program" or "software" is used in this article in a general sense to refer to any type of computer code or computer executable instruction set that can be used to program a computer or other processor to implement the above-mentioned various aspects. In addition, it should be understood that according to one aspect, one or more computer programs that perform the methods of the present application when executed do not need to reside on a single computer or processor, but can be distributed in a modular manner among multiple different computers or processors to implement various aspects of the present application.

[0186] In addition, the data structure may be stored in a computer-readable medium in any suitable form. To simplify the description, the data structure may be shown as having fields that are related by position in the data structure. This relationship can also be achieved by allocating storage space for the fields, which has locations in the computer-readable medium that convey the relationship between the fields. However, any suitable mechanism can be used to establish the relationship between the information in the fields of the data structure, including by using pointers, tags, or other mechanisms that establish relationships between data elements.

[0187] When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0188] The computer program logic that implements all or part of the functions described herein is embodied in various forms, including but not limited to source code form, computer executable form, hardware description form, and various intermediate forms (e.g., mask works or forms generated by assemblers, compilers, linkers, or locators). In one example, the source code includes a series of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages ​​such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML, for various operating systems or operating environments. The source code can define and use various data structures and communication messages. The source code can be in a computer executable form (e.g., by an interpreter), or the source code can be converted (e.g., via a translator, assembler, or compiler) into a computer executable format.

[0189] In some embodiments, any number of the circuits in the figures may be implemented on a board of the associated electronic device. The board may be a general purpose circuit board that can house various components of the electronic system within the electronic device and may also provide connectors for other peripheral devices. More specifically, the board may provide electrical connections through which other components of the system may communicate electrically. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), storage elements, etc. may be appropriately coupled to the board based on specific configuration requirements, processing requirements, computer design, etc.

[0190] Other components, such as external memory, additional sensors, audio / video display controllers, and peripherals, can be connected to the board via cables as plug-in cards or integrated into the board itself. In another example embodiment, the circuits of the accompanying drawings can be implemented as stand-alone modules (e.g., devices with related components and circuits configured to perform a specific application or function) or as plug-in modules inserted into dedicated hardware of an electronic device.

[0191] Note that through many of the examples provided herein, interactions may be described in terms of two, three, four, or more electrical components. However, this is done for clarity and example purposes only. It should be understood that the system may be integrated in any suitable manner. Along similar design alternatives, any of the illustrated components, modules, and elements in the accompanying drawings may be combined in a variety of possible configurations, all of which are clearly within the broad scope of the present disclosure.

[0192] In some cases, it may be easier to describe one or more functions of a given set of flows by referencing only a limited number of electrical components. It should be understood that the drawings and the circuits they teach are readily scalable to accommodate a large number of components and more complex / intricate arrangements and configurations. Therefore, the examples provided should not limit the scope of the circuits or inhibit their broad teachings that may be applied to countless other architectures.

[0193] In addition, as described, some aspects may be embodied as one or more methods. The actions performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed that perform actions in a sequence different from the sequence shown, which may include performing some actions simultaneously, even though shown as sequential actions in an exemplary embodiment.

[0194] Explanation of terms

[0195] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms. Unless the context clearly requires otherwise, throughout the specification and claims:

[0196] The words “include”, “including”, etc. shall be construed as being inclusive rather than exclusive or exhaustive; that is, in the sense of “including but not limited to”.

[0197] “Connected,” “coupled,” or any variation thereof, refers to any direct or indirect connection or coupling between two or more elements; the coupling or connection between the elements may be physical, logical, or a combination thereof.

[0198] When used to describe this Specification, the words “herein,” “above,” “hereunder,” and words of similar import shall refer to this Specification as a whole and not to any particular portion of this Specification.

[0199] “Or” refers to a list of two or more items and covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0200] The singular forms "a", "an" and "the" are intended to include any appropriate plural forms.

[0201] Words indicating directions, such as "vertical," "lateral," "horizontal," "upward," "downward," "forward," "backward," "inward," "outward," "perpendicular," "lateral," "left," "right," "front," "backward," "top," "bottom," "below," "above," "lower," etc., used in this specification and any appended claims, if any, depend on the specific orientation of the device being described and illustrated. The subject matter described herein can assume a variety of alternative orientations. Accordingly, these directional terms are not strictly defined and should not be narrowly interpreted.

[0202] Unless expressly stated to the contrary, the indefinite articles "a," "an," and "an" used in the specification and claims should be understood to mean "at least one."

[0203] The phrase "and / or" used herein in the specification and claims should be understood to mean "one or both" of the elements so coupled, i.e., elements that are present in combination in some cases and separate in other cases. Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so coupled.

[0204] In addition to the elements expressly identified by the "and / or" clause, other elements may optionally be present, whether or not related to those elements expressly identified. Thus, as a non-limiting example, in one embodiment, when used in conjunction with open language such as "comprising," a reference to "A and / or B" may refer to only A (optionally including elements other than B); in another embodiment only B (optionally including elements other than A); in another embodiment both A and B (optionally including other elements); etc.

[0205] As used herein in the specification and claims, the phrase "at least one" refers to a list of one or more elements and should be understood to refer to at least one element selected from any one or more elements in the list of elements, but does not necessarily include at least one of each element specifically listed in the list of elements, nor does it exclude any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than the elements specifically identified in the list of elements referred to by the phrase "at least one", whether or not these elements are related to those specifically identified elements.

[0206] Thus, as a non-limiting example, in one embodiment, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently "at least one of A and / or B") may refer to at least one, optionally including multiple A, with no B present (and optionally including elements other than B); in another embodiment, may refer to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in another embodiment, may refer to at least one (optionally including more than one) A and at least one, optionally including more than one B (and optionally including other elements); etc.

[0207] As used herein, the term "between" is intended to be inclusive unless otherwise stated. For example, "between A and B" includes A and B unless otherwise stated.

[0208] In addition, the words and terms used herein are for description only and should not be considered as limiting. The words "include", "comprising", or "having", "containing", "involving" and their variations used herein are intended to include the items listed below and their equivalents as well as additional items.

[0209] In the claims and the above description, all transitional phrases, such as "includes", "comprising", "carrying", "having", "containing", "involving", "holding", "consisting of", etc., shall be understood as open-ended, i.e., meaning including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively.

[0210] Numerous other changes, substitutions, alterations, and modifications may be ascertained by those skilled in the art, and this disclosure is intended to embrace all such changes, substitutions, alterations, modifications, and modifications that fall within the scope of the appended claims.

[0211] To assist the United States Patent and Trademark Office (USPTO) and any reader of any patent that issues from this application in interpreting the claims appended hereto, applicants wish to note that applicants: (a) do not intend to invoke 35 U.S.C. § 112(f) as it existed on the date of filing this application, unless the words “for” or “with” are specifically used in a particular claim; and (b) do not intend that any statement in this disclosure should limit the present disclosure in any manner not reflected in the appended claims.

[0212] Therefore, the present invention should not be considered as limited to the specific embodiments described above. After reading this disclosure, those skilled in the art to which the present invention is directed will easily understand various modifications, equivalent processes, and numerous structures to which the present invention may be applicable.

[0213] Example Embodiments

[0214] Example 1. A system for synchronous audio communication and bus power over a network bus, comprising: a master node having a power supply, a transceiver, and a field effect transistor; a sub-node; and an eight-pin connector between the master node and the bus node; wherein the master node and the sub-node communicate via the eight-pin connector, and wherein the master node supplies power to the sub-node via the eight-pin connector.

[0215] Example 1A: The system of Example 1, wherein the subnode is a first subnode, wherein the network bus includes a plurality of daisy-chain nodes including the first subnode, wherein the master node transmits power to at least a second subnode in the daisy-chain nodes through the first subnode.

[0216] In some examples of networks and methods, a data communication network includes a plurality of nodes 102. The nodes 102 include a master node (MN) 102-1 / 1502 and at least one child node 102-2 / 1504 (SN i =SN0,…SN x ). Each node 102 includes a node transceiver 120. The node transceiver 120 is operable to perform data communications according to a first network protocol for powering data via a pair of conductors (e.g., conductors of bus 106). The physical layer includes a cable segment between each node 120 (e.g., a cable segment of bus 106). Each cable segment includes multiple pairs of conductors (e.g., pair 1510) and connectors at each end (e.g., 8P8C connector 1520, but other connectors with multiple pairs of conductors may also be used). The first pair of conductors 1510a (e.g., connected to pin 4 and pin 5 of 8P8C connector 1520) implements the first network protocol between nodes. One or more of the remaining pairs of conductors (e.g., 1510b, 1510c) provide supplemental power to the node 102.

[0217] In some examples, the supplemental power source is a parallel power source on the remaining pairs (e.g., 1510b, 1510c, and the pair connected to pin 3 and pin 6 of the 8P8C connector 1520). In some examples, the connector is an eight-position eight-contact (8P8C) connector 1520. In some such examples, pin 4 and pin 5 of each 8P8C connector 1520 correspond to the first pair 1510a. In some examples, the first network protocol is an automotive audio bus (A2B).

[0218] In some examples, each SN 102-2 also includes a memory (e.g., EEPROM 1530). The memory communicates with a corresponding node transceiver 120 (e.g., AD2437 1540). The memory stores thereon configuration information for each SN 102-2, identifying at least the power characteristics of each SN 102-2. In these examples, the network also includes a supplemental power supply (e.g., VREG1 ADP2360 1550) and a host processor (e.g., MCU / DSP / USBi host 1560). The host processor communicates with i) the supplemental power supply (e.g., VREG1 ADP2360 1550), ii) the MN 102-1, and iii) one or more SNs 102-2 in series using a first network protocol via the MN 102-1 and the physical layer. The main processor is operable to cooperate with the MN 102-1 and each given SN 102-2 to gradually apply the first power to the first pair (e.g., 1510a) to each given SN 102-2 downstream (e.g., first SN0, then SN1, etc.). The main processor then uses the applied first power to read the configuration information of the given SN 102-2 from the memory (e.g., 1530) of the given SN 102-2. The main processor then determines whether the given SN 102-2 needs supplemental power based on the read configuration information. After determining that the given SN 102-2 needs supplemental power, the main processor applies supplemental power through a supplemental power supply (e.g., VREG1 ADP2360 1550) and the remaining pairs. In some examples, the main processor is separate from the MN 102-1. In some examples, the first protocol power and the supplemental power come from a source integrated with the node transceiver 120, and in some examples, one or more of the first protocol power and any supplemental power come from separate devices.

[0219] In some such examples, the host processor may be further operable to detect whether a favorable power condition exists on the first pair (e.g., 1510a) after applying the first power. Then, upon determining that a favorable power condition exists on the first pair and before reading the configuration information, the host processor may discover the given SN 102-2 via the first protocol. In these examples, the condition for reading the first configuration information is discovering the given SN 102-2.

[0220] In some examples, the steps of this multi-step process (detecting favorable power conditions at the next child node, reading characteristics of the next child node, increasing supplemental power in the next child node) can be performed in other orders and combinations, including other combinations of power sources. In general, the example method is to confirm that the first protocol node (rather than an incompatible node) is located at the downstream multiple pairs of connectors, and then identify the characteristics of the downstream child nodes (including power requirements), and use a combination of the first protocol power and the supplemental power to meet these power requirements.

Claims

1. A data communication network, comprising: Multiple nodes, including a master node (MN) and at least one child node (SN i =SN0,...SN x ), each node comprising a node transceiver operable to perform data communications according to a first network protocol to power data over a pair of conductors; and The physical layer, which includes cable segments between each node, each cable segment includes multiple pairs of conductors and connectors at each end, in: A first pair of conductors implements a first network protocol between the nodes; and The remaining pairs of conductors provide supplemental power to the node.

2. The data communications network of claim 1, wherein the supplemental power is parallel power across the remaining pairs.

3. The data communications network of claim 1, wherein the connector is an eight-position eight-contact (8P8C) connector.

4. A data communication network according to claim 3, wherein pin 4 and pin 5 of each 8P8C connector correspond to the first pair.

5. The data communications network of claim 1, wherein the first network protocol is an Automobile Audio Bus (A2B).

6. The data communication network according to claim 1, wherein: Each SN also includes a memory, wherein: Communicate with the corresponding node transceiver, and storing thereon configuration information of each SN, at least identifying power characteristics of each SN; and The network also includes: Supplemental power supply; and Main processor: i) communicating with the supplemental power source, ii) communicating with the MN and ii) communicating with one or more SNs in series via the MN and the physical layer using the first network protocol; and Cooperate with the MN and each given SN, and perform the following operations step by step to each given SN downstream: applying a first power to the first pair; reading configuration information of the given SN from a memory of the given SN using the applied first power; Based on the read configuration information, determining whether the given SN needs supplemental power; Applied upon determining that the given SN requires supplemental power via the supplemental power source and the remaining pair.

7. A data communication network according to claim 6, wherein: The main processor is also operative to: After applying the first power, detecting whether a favorable power condition exists on the first pair; and Upon determining that favorable power conditions exist on the first pair and before reading the configuration information, discovering a given SN via a first protocol; and A condition for reading the first configuration information is to discover the given SN.

8. A method for data communication network operation, comprising: In data communication networks, these include: Multiple nodes, including a master node (MN) and at least one child node (SN i =SN0,...SN x ), each node comprising: a node transceiver operable to perform data communications according to a first network protocol to power data over a pair of conductors; and a memory, the memory being in communication with the corresponding node transceiver and storing thereon configuration information of the SN, at least identifying a power characteristic of the SN; a physical layer comprising a cable segment between each node, each cable segment comprising a plurality of pairs of conductors and a connector at each end, wherein a first pair of the plurality of pairs implements the first network protocol between the nodes; and the remaining pairs provide supplemental power to the nodes; Supplemental power supply; and a main processor, i) communicating with the supplemental power source, ii) communicating with the MN, and ii) communicating with one or more SNs in series via the MN and the physical layer using the first network protocol; Cooperate with the MN and each given SN, and perform the following operations step by step to each given SN downstream: applying a first power to the first pair; reading configuration information of the given SN from a memory of the given SN using the applied first power; Based on the read configuration information, determining whether the given SN needs supplemental power; Applied upon determining that the given SN requires supplemental power via the supplemental power source and the remaining pair.

9. A data communication network according to claim 8, wherein: The method further includes: After applying the first power, detecting whether a favorable power condition exists on the first pair; and upon determining that favorable power conditions exist on the first pair and before reading the configuration information, discovering a given SN; and A condition for reading the first configuration information is to discover the given SN.

10. The data communications network of claim 8, wherein the supplemental power is parallel power across the remaining pairs.

11. The data communications network of claim 8, wherein the connector is an eight position eight contact (8P8C) connector.

12. The data communication network of claim 11, wherein pin 4 and pin 5 of each 8P8C connector correspond to the first pair.

13. The data communications network of claim 8, wherein the first network protocol is the Automobile Audio Bus (A2B).

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