A MEMS accelerometer with low parasitic capacitance and its fabrication method

Abstract

This application belongs to the field of inertial sensor technology, specifically disclosing a low-parasitic capacitance MEMS accelerometer and its fabrication method. This application utilizes a hollowed-out region formed on the back of the pickup electrode, directly opposite the substrate, reducing the facing area between the pickup electrode and the upper cover silicon substrate, thus lowering parasitic capacitance. Furthermore, a grounding plate is placed between the pickup electrodes, shielding the relative movement between the excitation electrode and the upper cover silicon substrate, further reducing the influence of parasitic capacitance between the excitation electrode and the silicon substrate. Through a thin-film support structure combined with plasma dry etching, a hollowed-out region is formed on the back of the MEMS accelerometer pickup electrode. This fabrication method is simple, applicable to various capacitive MEMS accelerometers or gravimeters, and has good compatibility and practicality.

Description

Technical Field

[0001] This application belongs to the field of inertial sensor technology, and more specifically, relates to a MEMS accelerometer with low parasitic capacitance and its fabrication method. Background Technology

[0002] MEMS (Micro Electro-Mechanical System) capacitive accelerometers, especially high-precision accelerometers with ng and sub-ng resolution, typically employ a silicon-glass bonding structure, with a glass substrate as the top cover and a silicon substrate as the spring oscillator. However, glass substrates are incompatible with the CMOS (Complementary Metal Oxide Semiconductor) process used in integrated circuits (ICs), thus limiting the integration of MEMS accelerometers with IC readout circuits and hindering device miniaturization. Furthermore, glass substrates increase the difficulty of wafer-level packaging, further impeding mass production.

[0003] An all-silicon structure (with both the top cover and the spring oscillator made of silicon) can effectively solve the above problems, but it has serious parasitic capacitance issues, which can lead to reduced sensitivity and increased background noise. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a MEMS accelerometer with low parasitic capacitance and its fabrication method, aiming to solve the problem of severe parasitic capacitance in existing MEMS accelerometers.

[0005] To achieve the above objectives, in a first aspect, this application provides a MEMS accelerometer with low parasitic capacitance, including a spring oscillator structure and a top cover plate;

[0006] The upper cover plate, along the direction facing the spring oscillator structure, includes, in sequence: a silicon substrate, a metal thin film, an insulating support thin film, and several pickup electrodes;

[0007] Both the silicon substrate and the metal thin film have hollowed-out areas, and the hollowed-out areas are directly opposite at least one pickup electrode.

[0008] Preferably, the width of the hollowed-out area is greater than the width of the pickup electrode.

[0009] Preferably, the cutout areas on the silicon substrate and the metal thin film are of equal or unequal width.

[0010] Preferably, a ground electrode is provided between adjacent pickup electrodes, and the distance between the ground electrode and the pickup electrode is less than the width of the excitation electrode in the spring oscillator structure.

[0011] Preferably, the insulating support film has a multilayer composite structure.

[0012] To achieve the above objectives, in a second aspect, this application provides a method for fabricating a MEMS accelerometer with low parasitic capacitance as described in the first aspect, comprising:

[0013] S1. Prepare the upper cover plate and spring oscillator structure separately;

[0014] S2. Connect the spring oscillator structure to the upper cover plate through the anchoring area.

[0015] Preferably, the preparation of the upper cover plate is as follows:

[0016] (1) A metal thin film is deposited on a silicon substrate using physical vapor deposition as a stop layer for deep silicon etching.

[0017] (2) A multilayer film is deposited on the metal film obtained in step (1) using chemical vapor deposition to serve as an insulating support film;

[0018] (3) Using the stripping process, pick-up electrodes and grounding electrodes are simultaneously fabricated on the insulating support film obtained in step (2), and physical isolation is achieved through layout design;

[0019] (4) Perform plasma dry etching on the back of the patterned silicon wafer obtained in step (3) to form a hollow area on the back of the pickup electrode.

[0020] (5) Remove the photoresist used as a dry etching mask in step (4) and the metal film obtained in step (1) located in the cutout area.

[0021] Preferably, step (3) includes:

[0022] (3.1) The silicon substrate obtained in step (2) is coated with photoresist using a spin coating process, and the metal electrode pattern is transferred onto the silicon wafer using an exposure method.

[0023] (3.2) Place the exposed silicon wafer in a developing solution for development;

[0024] (3.3) A metal thin film is deposited on the wafer using physical vapor deposition. Pick-up electrodes and ground electrodes are fabricated simultaneously. Physical isolation is achieved through layout design to realize different functions.

[0025] (3.4) The silicon wafer is immersed in acetone solution for metal stripping, cleaned with isopropanol, ethanol and deionized water, and dried with nitrogen.

[0026] Preferably, step (4) includes:

[0027] (4.1) The back of the silicon wafer obtained in step (3) is coated with photoresist using a homogenization process, and the pattern to be etched is transferred onto the silicon wafer using an exposure method.

[0028] (4.2) Place the exposed silicon wafer in a developing solution for development;

[0029] (4.3) Plasma dry etching is performed on the back of the wafer to form a hollow area on the back of the pickup electrode.

[0030] Preferably, the spring oscillator structure and the upper cover plate are bonded by gold-tin eutectic bonding, direct wafer bonding, or anodic bonding.

[0031] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art:

[0032] (1) This application provides a MEMS accelerometer with low parasitic capacitance. By forming a hollow area on the back of the pickup electrode, the area between the pickup electrode and the silicon substrate of the upper cover is reduced, thereby reducing parasitic capacitance. In addition, a grounding plate is provided between the pickup electrodes to shield the relative movement between the excitation electrode and the silicon substrate of the upper cover, further reducing the influence of parasitic capacitance between the excitation electrode and the silicon substrate.

[0033] (2) This application provides a method for fabricating a MEMS accelerometer with low parasitic capacitance. By using a thin film support structure and combining plasma dry etching, a hollow area is formed on the back of the MEMS accelerometer pickup electrode. This fabrication method is simple and applicable to various capacitive MEMS accelerometers or gravimeters, and has good compatibility and practicality. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a low parasitic capacitance MEMS accelerometer structure provided in an embodiment of this application.

[0035] Figure 2 This is a detailed process flow diagram of the top cover plate provided in the embodiments of this application.

[0036] Figure 3 This is a detailed process flow diagram of the spring oscillator structure provided in the embodiments of this application.

[0037] Figure 4 This is a schematic diagram showing the key dimensions of the top cover plate provided in the embodiments of this application.

[0038] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0039] 101-Frame, 102-Support beam, 103-Modible mass block, 104-Silicon oxide, 105-Ground plane, 106-Silicon oxide, Excitation electrodes-107, 108, 109, 110, 201-Anchoring area, 202-Silicon substrate, 203-Metal thin film, 204-Support thin film, Pickup electrodes-205, 206, 207-Ground electrode, 208-Knockout area. Detailed Implementation

[0040] For ease of understanding, the English abbreviations and related technical terms used in the embodiments of this application will be explained and described below.

[0041] The embodiments of this application are described below with reference to the accompanying drawings.

[0042] like Figure 1 As shown, this application provides a MEMS accelerometer with low parasitic capacitance, including: a spring oscillator structure and a top cover plate.

[0043] The spring oscillator structure is integrally machined and includes a frame 101, a support beam 102, a movable mass block 103, silicon oxide 104 and 106, a grounding plane 105, and excitation electrodes 107 to 110.

[0044] The movable mass block 103 is connected to the frame 101 via the support beam 102. Silicon oxide 104 is deposited on the movable mass block 103 to achieve electrical isolation between the ground plane 105 and the movable mass block 103. Silicon oxide 106 is deposited on the ground plane 105 to achieve electrical isolation between the excitation electrodes 107-110 and the ground plane 105. Among them, the excitation electrodes 107 and 109 are connected to the external positive voltage, and the excitation electrodes 108 and 110 are connected to the external reverse voltage.

[0045] Support beam 102 includes, but is not limited to, springs. Movable mass block 103 can move left and right, with a range of movement of tens of μm. 104 and 106 can be made of silicon oxide or silicon nitride, and the materials can be the same or different.

[0046] The upper cover plate includes: a silicon substrate 202, a metal thin film 203, a support thin film 204, pickup electrodes 205 and 206, a ground electrode 207, and a hollow area 208.

[0047] The metal thin film 203 is located between the silicon substrate 202 and the support film 204, the pickup electrodes 205 and 206 are located on the support film, the ground electrode 207 is located between the pickup electrodes 205 and 206, and there is a cutout area 208 above the pickup electrodes 205 and 206.

[0048] It should be noted that when the width of the cutout area is slightly larger than the width of the pickup electrode 205, the reduction effect of the integrated capacitance is better, generally referring to a difference of more than 10 micrometers.

[0049] It should be noted that the height of the cutout area is greater than 10 micrometers, and the greater the height, the better the reduction in integrated capacitors.

[0050] Pickup electrode 205 is located between excitation electrodes 107 and 108, forming a pair of differential capacitors, and pickup electrode 206 is located between excitation electrodes 109 and 110, forming another pair of differential capacitors. Figure 1 The image only shows two pairs of differential capacitors schematically; in reality, MEMS accelerometers contain 10 to 80 pairs of differential capacitors.

[0051] The spring oscillator structure is connected to the upper cover plate through the anchoring area 201. The connection methods include, but are not limited to, direct wafer bonding, anodic bonding, and eutectic bonding.

[0052] In the sensing process of an all-silicon accelerometer, the voltage change generated by the pickup electrode can be described by the following equation:

[0053]

[0054] Among them, C x C y C represents the sensing capacitance between excitation electrodes 107 and 108 and pickup electrode 205, respectively. p3 C represents the parasitic capacitance between the pickup electrode 205 and the upper cover silicon substrate 202. p4 C represents the parasitic capacitance between the upper cover silicon substrate 202 and the spring oscillator frame 101. p5 C p6 C represents the parasitic capacitance between the excitation electrodes 107 and 108 and the upper cover silicon substrate 202, respectively. p7 This represents the parasitic capacitance between the pickup electrode 205 and the ground electrode 206.

[0055] Parasitic capacitance C p3 C p5 C p6 C has the greatest impact on the sensing process. p3 Depending on the face-to-face area between the pickup electrode 205 and the upper cover silicon substrate 202, C p5 C p6 Depending on the relative motion between the excitation electrodes 107 and 108 and the upper cover silicon substrate 202 during the movement, C during the actual movement p5 ≠C p6 .

[0056] The top cover plate reduces parasitic capacitance by forming a hollow area 208 on the back of the pickup electrode 205, thereby reducing the face-to-face area between the pickup electrode and the top cover silicon substrate 202. The grounding plate 207 shields the relative movement between the excitation electrodes 107 and 108 and the top cover silicon substrate 202 during movement, thus reducing C p5 =C p6 This reduces parasitic capacitance.

[0057] like Figure 2 As shown, the specific process flow of the top cover plate provided in this application is as follows:

[0058] S1: A metal thin film 203 of Ti material with a thickness of 200 nm is deposited on a silicon substrate using physical vapor deposition as a stop layer for deep silicon etching.

[0059] S2: A three-layer thin film 204 of silicon oxide / silicon nitride / silicon oxide with a thickness of 500nm / 500nm / 2500nm is deposited on the metal thin film obtained in S1 using chemical vapor deposition to serve as the support structure for the pickup electrodes 205 and 206.

[0060] S3: Pickup electrodes 205 and 206 and ground electrode 207 are simultaneously fabricated on the insulating film obtained in S2 using a stripping process. The material is Cr / Au, and the thickness is 40nm / 200nm. They are physically isolated through layout design to achieve different functions.

[0061] S4: Perform plasma dry etching on the patterned back of the silicon wafer obtained in S3 to form a hollow area 208 on the back of the pickup electrode;

[0062] S5: Remove the photoresist used as a dry etching mask in S4 and the metal film obtained in S1 located in the cutout area.

[0063] Furthermore, S1 specifically includes the following steps:

[0064] S101: The silicon substrate is organically cleaned sequentially with acetone, isopropanol, ethanol and deionized water, and then dried with nitrogen to complete the initial cleaning.

[0065] S102: The silicon wafers after preliminary cleaning are further cleaned with oxygen plasma;

[0066] S103: Deposit a 200nm thick Ti thin film on the cleaned silicon substrate using physical vapor deposition.

[0067] The metal material can be titanium, aluminum, or chromium, as well as other metals that are easy to remove.

[0068] Furthermore, S2 specifically includes the following steps: depositing a three-layer thin film of silicon oxide / silicon nitride / silicon oxide on the metal thin film obtained in S1 using chemical vapor deposition as a support structure for the pickup electrode, with a thickness of 500nm / 500nm / 2500nm.

[0069] The support structure can be a single-layer or multi-layer thin film, including silicon oxide, silicon nitride, or other films with support capabilities. Multi-layer thin films can achieve stress compensation to a certain extent and control silicon wafer warpage, and are therefore more commonly used.

[0070] Furthermore, S3 specifically includes the following steps:

[0071] S3.1: The silicon substrate obtained in S2 is coated with photoresist using a spin coating process, and the metal electrode pattern is transferred onto the silicon wafer using an exposure method;

[0072] S3.2: Place the exposed silicon wafer in the developing solution for development;

[0073] S3.3: A Cr 40nm / Au 200nm thin film is deposited on the wafer using physical vapor deposition. Pick-up electrodes and ground electrodes are fabricated simultaneously, and physical isolation is achieved through layout design to realize different functions.

[0074] S3.4: Immerse the silicon wafer in acetone solution for metal stripping, clean it with isopropanol, ethanol and deionized water, and dry it with nitrogen.

[0075] It should be noted that the distance between the ground electrode and the pickup electrode needs to be less than the width of the excitation electrode to ensure that the ground electrode can shield the relative movement between the excitation electrode and the silicon substrate of the upper cover plate.

[0076] Furthermore, S4 specifically includes the following steps:

[0077] S4.1: Apply photoresist to the back of the silicon wafer obtained in S3 using a homogenization process, and transfer the pattern to be etched onto the silicon wafer using an exposure method;

[0078] S4.2: Place the exposed silicon wafer in the developing solution for development;

[0079] S4.3: Plasma dry etching is performed on the back of the wafer to form a hollow area on the back of the pickup electrode.

[0080] It should be noted that the width of the cutout area on the back of the pickup electrode should be greater than the width of the pickup electrode itself, thereby reducing the face-to-face area between the pickup electrode and the top silicon substrate, and thus reducing parasitic capacitance.

[0081] Furthermore, S5 specifically includes the following steps:

[0082] S5.1: Use oxygen plasma to clean the silicon wafer to remove the photoresist that has been hardened by dry etching;

[0083] S5.2: Dissolve the photoresist with acetone solution, then clean it with isopropanol, ethanol and deionized water;

[0084] S5.3: Soak the silicon wafer in a metal etching solution to remove the metal in the area cut out after S4 obtained in S1; clean it with deionized water and dry it with nitrogen.

[0085] like Figure 3 As shown, the specific process flow of the spring oscillator structure provided in this application is as follows:

[0086] S6: Ground plane 105 is fabricated on a silicon substrate with a 300nm oxide layer using a lift-off process. The material is Ti / Au and the thickness is 40nm / 200nm.

[0087] S7: A silicon oxide thin film 106 with a thickness of 1700 nm is deposited on the ground plane prepared in S6 using chemical vapor deposition as an insulating layer between the excitation electrode and the ground plane.

[0088] S8: A deep silicon etching window is opened on the silicon oxide film deposited in S7 using reactive ion etching.

[0089] S9: Excitation electrodes 107-110 are fabricated on the silicon wafer obtained in S8 using a lift-off process. The material is Ti / Au, and the thickness is 40nm / 200nm.

[0090] S10: The silicon wafer obtained in S9 is etched by plasma dry etching to obtain a spring oscillator structure.

[0091] The spring oscillator structure is connected to the upper cover plate through the anchoring area 201, and the connection method is gold-tin eutectic bonding.

[0092] Example

[0093] like Figure 4 As shown, the key dimensions of the top cover plate include: a silicon wafer thickness of 500 micrometers, a cutout area width of 80 μm, a pickup electrode width of 60 μm, a grounding electrode metal width of 30 μm, a metal film thickness of 20 nm, and an insulating support film thickness of 3500 nm. Specifically, it consists of three thin films: 500 nm silicon oxide, 500 nm silicon nitride, and 2500 nm silicon oxide.

[0094] In this embodiment, the silicon wafer used in S6 has a thickness of 500μm, and the bonding temperature during the gold-tin eutectic bonding connection is 300℃ for 5 minutes.

[0095] After preparation, the parasitic capacitance between the pickup electrode and the ground electrode was tested using an LCR meter. The parasitic capacitance was 924 pF without this application and 70 pF with this application, which is a reduction of 13.2 times.

[0096] Scale factor tests were conducted on the all-silicon accelerometer. Without this application, the accelerometer's scale factor was 1407 V / g; with this application, the scale factor was 9336 V / g, representing a 6.63-fold increase. Specifically, without a ground electrode, the scale factor was 6300 V / g; using a ground electrode increased the scale factor by 1.48 times.

[0097] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0098] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0099] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the components can rotate relative to each other after connection. "Sliding connection" refers to a connection where the components can slide relative to each other after connection. The directional terms mentioned in the embodiments of this application, such as "top," "bottom," "inner," "outer," "left," and "right," are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0100] Furthermore, the mathematical concepts mentioned in the embodiments of this application, such as symmetry, equality, parallelism, and perpendicularity, are limitations specific to the current technological level, rather than absolute and strict mathematical definitions. Slight deviations are permissible; approximations of symmetry, equality, parallelism, and perpendicularity are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0101] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A MEMS accelerometer with low parasitic capacitance, characterized in that, Includes a spring oscillator structure and an upper cover plate; The upper cover plate, along the direction facing the spring oscillator structure, includes, in sequence: a silicon substrate, a metal thin film, an insulating support thin film, and several pickup electrodes; Both the silicon substrate and the metal thin film have hollowed-out areas, and the hollowed-out areas are directly opposite at least one pickup electrode.

2. The MEMS accelerometer as described in claim 1, characterized in that, The width of the hollowed-out area is greater than the width of the pickup electrode.

3. The MEMS accelerometer as described in claim 1, characterized in that, The cutout areas on the silicon substrate and the metal thin film may be of equal or unequal width.

4. The MEMS accelerometer as described in any one of claims 1 to 3, characterized in that, A grounding electrode is provided between adjacent pickup electrodes, and the distance between the grounding electrode and the pickup electrode is less than the width of the excitation electrode in the spring oscillator structure.

5. The MEMS accelerometer as described in any one of claims 1 to 3, characterized in that, The insulating support film has a multi-layer composite structure.

6. A method for fabricating a low parasitic capacitance MEMS accelerometer as described in any one of claims 1 to 5, characterized in that, include: S1. Prepare the upper cover plate and spring oscillator structure separately; S2. Connect the spring oscillator structure to the upper cover plate through the anchoring area.

7. The preparation method according to claim 6, characterized in that, The preparation of the upper cover plate is as follows: (1) A metal thin film is deposited on a silicon substrate using physical vapor deposition as a stop layer for deep silicon etching. (2) A multilayer film is deposited on the metal film obtained in step (1) using chemical vapor deposition to serve as an insulating support film; (3) Using the stripping process, pick-up electrodes and grounding electrodes are simultaneously fabricated on the insulating support film obtained in step (2), and physical isolation is achieved through layout design; (4) Perform plasma dry etching on the back of the patterned silicon wafer obtained in step (3) to form a hollow area on the back of the pickup electrode. (5) Remove the photoresist used as a dry etching mask in step (4) and the metal film obtained in step (1) located in the cutout area.

8. The preparation method according to claim 7, characterized in that, Step (3) includes: (3.1) The silicon substrate obtained in step (2) is coated with photoresist using a spin coating process, and the metal electrode pattern is transferred onto the silicon wafer using an exposure method. (3.2) Place the exposed silicon wafer in a developing solution for development; (3.3) A metal thin film is deposited on the wafer using physical vapor deposition. Pick-up electrodes and ground electrodes are fabricated simultaneously. Physical isolation is achieved through layout design to realize different functions. (3.4) The silicon wafer is immersed in acetone solution for metal stripping, cleaned with isopropanol, ethanol and deionized water, and dried with nitrogen.

9. The preparation method according to claim 7, characterized in that, Step (4) includes: (4.1) The back of the silicon wafer obtained in step (3) is coated with photoresist using a homogenization process, and the pattern to be etched is transferred onto the silicon wafer using an exposure method. (4.2) Place the exposed silicon wafer in a developing solution for development; (4.3) Plasma dry etching is performed on the back of the wafer to form a hollow area on the back of the pickup electrode.

10. The preparation method according to claim 6, characterized in that, The spring oscillator structure and the upper cover plate are bonded by gold-tin eutectic bonding, direct wafer bonding, or anodic bonding.

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