Logic analyzer, chip and data processing method

Abstract

The invention provides a logic analyzer, a chip and a data processing method, and the logic analyzer comprises a data sampling module which is in communication connection with a core particle and is used for continuously obtaining to-be-detected data of the core particle in real time; the trigger detection module is used for outputting a trigger enable signal when the to-be-detected data meet a trigger condition and representing the to-be-detected data as trigger data; the data storage module is used for continuously and temporarily storing the to-be-tested data in real time; wherein the data storage module is further used for representing the part of to-be-tested data stored before the trigger data, the trigger data and the part of to-be-tested data stored after the trigger data as test data according to the current physical address of the trigger enable signal and the trigger data stored in the data storage module, and fixedly storing the test data. According to the logic analyzer, the chip and the data processing method provided by the invention, the debuggeability of the chip can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a logic analyzer, a chip and a data processing method. Background Art

[0002] With the rapid development of modern integrated circuit technology, the functions and architecture of chips have become increasingly complex. Modern chips support a variety of complex operations and tasks in terms of functionality, and their architectures tend to be multi-core or even heterogeneous computing architectures. This complexity requires higher design precision and debugging technology to ensure coordination between different functional modules and optimal performance.

[0003] At present, logic analyzers are mainly used for debugging FPGA (Field-Programmable Gate Array) circuits, but are rarely used in application-specific integrated circuits and other complex chips. Their functions are often limited and can only meet basic needs. They do not have the ability to cope with complex debugging scenarios. After capturing the key signal, it is impossible to obtain the capture signal depth before and after dynamically adjusting the timing of the key signal, that is, dynamically adjusting the size of the test data to be captured, which limits the flexibility and depth of debugging. How to effectively improve the debuggability of chips has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0004] The object of the present invention is to provide a logic analyzer, a chip and a data processing method, which can effectively improve the debuggability of the chip.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a logic analyzer, comprising:

[0007] A data sampling module, connected to the core particle for continuous and real-time acquisition of the data to be tested of the core particle;

[0008] A trigger detection module, used to output a trigger enable signal when the data to be tested meets the trigger condition, and represent the data to be tested as trigger data; and

[0009] A data storage module, used for temporarily storing the data to be tested continuously and in real time;

[0010] Among them, the data storage module is also used to represent and fixedly store part of the data to be tested stored before the trigger data, the trigger data, and part of the data to be tested stored after the trigger data according to the trigger enable signal and the current physical address of the trigger data stored in the data storage module.

[0011] In one embodiment of the present invention, the data sampling module includes at least one multiplexer group, and the multiplexer group includes at least one multiplexer; the multiplexer is communicatively connected to the multiplex transmission channel of the core particle, and is used to select a sampling signal from the multiplex transmission channel for output; the sampling signals within the same clock cycle constitute the data to be tested.

[0012] In one embodiment of the present invention, the trigger detection module includes:

[0013] trigger channels, the number of which corresponds to the number of bits of the data to be tested, and the data signal of each bit of the data to be tested is transmitted to the corresponding trigger channel; and

[0014] The trigger register is used to configure the trigger condition of each of the trigger channels, and output the trigger enable signal when the data signals in all the trigger channels meet the corresponding trigger conditions.

[0015] In one embodiment of the present invention, the data storage module further includes:

[0016] A storage unit, used for temporarily storing the data to be tested continuously and in real time;

[0017] A write trigger counting unit, used for calculating the first physical address of the test data according to the current physical address of the trigger data stored in the storage unit;

[0018] A FIFO buffer unit, used for storing the first physical address; and

[0019] A write operation control unit is used to store the test data in the storage unit in fixed order according to the trigger enable signal and the first physical address.

[0020] In one embodiment of the present invention, when the number of storage spaces in the storage unit is one, the write trigger counting unit is used to calculate the first physical address according to the size of the storage space and the current physical address, so that the test data is fixedly stored in sequence from the first physical address in the order of the physical addresses until the storage space is full.

[0021] In one embodiment of the present invention, when the number of storage spaces in the storage unit is multiple:

[0022] The write trigger counting unit is used to calculate the first physical address of the corresponding test data according to the size of a certain storage space and the current physical address of a certain trigger data, so that the corresponding test data is fixedly stored in sequence from the first physical address according to the order of the physical addresses until a certain storage space is filled;

[0023] After the test data is fixedly stored in a certain storage space, the write operation control unit temporarily stores other data to be tested in the next storage space until the next trigger data appears. The write trigger counting unit is used to calculate the first physical address of the corresponding test data according to the size of the next storage space and the current physical address of the next trigger data, so that the corresponding test data is fixedly stored in sequence from the first physical address in the order of the physical addresses until the next storage space is full.

[0024] In one embodiment of the present invention, a write trigger counter is configured in the write trigger counting unit, and the write trigger counter is used to count each time a trigger enable signal is detected, and when the count reaches a preset number of times, a write completion signal is output and transmitted to the host, wherein the preset number of times is equal to the amount of storage space in the storage unit.

[0025] In one embodiment of the present invention, the data storage module also includes a read operation control unit, which is used to read the first physical address stored in the FIFO cache unit according to a read enable signal of the host; the storage unit is used to read the corresponding test data to the host according to the first physical address.

[0026] In one embodiment of the present invention, the data storage module also includes a read trigger counting unit, in which a read trigger counter is configured. The read trigger counter is used to count when the test data in each storage space of the storage unit is completely read out, and when the count reaches a preset number of times, a read completion signal is output and transmitted to the host.

[0027] The present invention also provides a chip, including a logic analyzer and a core particle.

[0028] The present invention also provides a chip data processing method, comprising:

[0029] Continuously and in real time obtain the test data of the core particle;

[0030] When the data to be tested meets the trigger condition, a trigger enable signal is output, and the data to be tested is represented as trigger data;

[0031] According to the trigger enable signal and the current physical address of the trigger data storage, part of the test data stored before the trigger data, the trigger data, and part of the test data stored after the trigger data are represented as test data and fixedly stored.

[0032] As described above, the present invention provides a data processing method for a logic analyzer, which greatly enhances the applicability and test effect in complex scenarios through a variety of flexible trigger conditions, negative delay capture capability, and efficient data storage. It can accurately capture and analyze key signals, which helps developers quickly locate problems and conduct in-depth troubleshooting.

[0033] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0035] Figure 1 is a schematic diagram of a logic analyzer in one embodiment of the present invention;

[0036] Figure 2 is a schematic diagram of a data sampling module in one embodiment of the present invention;

[0037] Figure 3 is a schematic diagram of a trigger detection module in one embodiment of the present invention;

[0038] Figure 4 A schematic diagram of a data storage module according to an embodiment of the present invention;

[0039] Figure 5 Schematic diagram of a test data writing process in one embodiment of the present invention.

[0040] In the figure: 100, data sampling module; 110, multiplexer;

[0041] 200, trigger detection module; 210, trigger channel; 220, trigger register;

[0042] 300, data storage module; 310, register cache unit; 320, storage unit; 321, first storage space; 322, second storage space; 330, write operation control unit; 340, write trigger counting unit; 350, address management unit; 360, FIFO cache unit; 370, read operation control unit; 380, read trigger counting unit; 390, state management unit;

[0043] 400. Host. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] See also Figure 1 The present invention discloses a chip, on which a plurality of core particles and a logic analyzer can be integrated. The logic analyzer can be connected to the observed interface signal (Ucie IP) inside the chip, and can be used to test the core particles. The logic analyzer can include a data sampling module 100, a trigger detection module 200, and a data storage module 300. Among them, the data sampling module 100 can be connected to the core particle for communication, and is used to obtain the test data of the core particle in real time, and the test data refers to the signal that needs to be debugged inside the core particle. The trigger detection module 200 can be used to output a trigger enable signal when a certain test data meets the trigger condition, and represent the test data that meets the trigger condition as trigger data. The data storage module 300 can continuously and temporarily store the test data in real time. The data storage module 300 can also be used to represent part of the test data stored before the trigger data, the trigger data, and part of the test data stored after the trigger data as test data according to the trigger enable signal and the current physical address of the trigger data stored in the data storage module, and store them fixedly.

[0046] See also Figure 2 In one embodiment, the data sampling module 100 and the core particles can be connected through a UCIe link communication. The data sampling module 100 can select those signals that need to be monitored and analyzed from the 256 independent sampling signals (Data[255:0], Data 0~Data 255) transmitted from different core particles through the UCIe interface according to specific debugging requirements. Among them, different sampling signals can come from different transmission channels to carry independent data information between different modules. Each transmission channel can be used to transmit different types of sampling signals, such as control information, status indication or actual data load. Through this design, the sampling signals that need to be monitored can be flexibly selected during chip debugging, the debugging efficiency can be improved, and the problem can be quickly located and solved.

[0047] See also Figure 2In one embodiment, the data sampling module 100 may include at least one multiplexer group. Each multiplexer group may select and output one sampling signal from 256 independent sampling signals. The number of multiplexer groups may be one or more. When the number of multiplexer groups is one, one sampling signal may be outputted to form the data to be tested. When the number of multiplexer groups is more than one, multiple sampling signals may be outputted to form the data to be tested.

[0048] See also Figure 2 In one embodiment, the multiplexer group may include at least one multiplexer 110. The input end of the multiplexer 110 may be communicatively connected to the multiplexed transmission channels of the multiple core particles, and is used to select a sampling signal from the multiplexed transmission channels for output. The number of multiplexers 110 may be unlimited. For example, when the number of multiplexers 110 is one, its input end may be communicatively connected to 256 transmission channels of the multiple core particles at the same time. When the number of multiplexers 110 is three, the input end of the first multiplexer may be communicatively connected to the first 128 transmission channels, the input end of the second multiplexer may be communicatively connected to the last 128 transmission channels, and the input end of the third multiplexer may be communicatively connected to the output end of the first multiplexer and the output end of the second multiplexer, respectively, and finally output a sampling signal.

[0049] See also Figure 2In one embodiment, the number of multiplexers 110 in the multiplexer group is 17 as an example. The input end of the first multiplexer can be connected to the 16 transmission channels of Data 0 to Data 15 to select one sampling signal for output. The input end of the second multiplexer can be connected to the 16 transmission channels of Data 16 to Data 31 to select one sampling signal for output. Similarly, the input end of the sixteenth multiplexer can be connected to the 16 transmission channels of Data 239 to Data 255 to select one sampling signal for output. The input end of the sixteenth multiplexer can be connected to the output end of the first to sixteenth multiplexers at the same time to select one sampling signal for output. Among them, the input ends of the first to sixteenth multiplexers can also receive a multiplex selection signal (debug_address_g0[3:0]), and the multiplex selection signal can be configured by the host 400 through the APB bus to perform the first level selection. The input end of the seventeenth multiplexer can also receive a selection signal (debug_address_g0[7:4]), which can be configured by the host 400 through the APB bus to perform a second level selection. The host 400 refers to a processor, an upper software system, a host computer, etc., and is not limited here.

[0050] See also Figure 2 In one embodiment, the number of multiplexer groups is two as an example. The sampling signal output by the first multiplexer group can be expressed as DEBUG_SIGNAL_G0. The sampling signal output by the second multiplexer group can be expressed as DEBUG_SIGNAL_G1. DEBUG_SIGNAL_G0 and DEBUG_SIGNAL_G1 can be 16-bit signals. DEBUG_SIGNAL_G0 and DEBUG_SIGNAL_G1 in the same clock cycle can constitute the data to be tested.

[0051] See also Figure 3 In one embodiment, the trigger detection module 200 can obtain the test data output by the data sampling module 100 in real time, and detect the test data to determine whether it meets the trigger condition. The trigger detection module 200 can include a trigger channel 210 and a trigger register 220.

[0052] See also Figure 3In one embodiment, the number of trigger channels 210 may correspond to the number of bits of the data to be tested. For example, when the data to be tested is a 32-bit signal, the number of trigger channels 210 may be 32 (Data_in[0] to Data_in

[31] ). For another example, when the data to be tested is a 64-bit signal, the number of trigger channels 210 may be 64 (Data_in[0] to Data_in

[63] ). Each trigger channel 210 may correspond to a bit of the data to be tested. After the data to be tested is acquired, the data signal of the corresponding bit may be transmitted to the corresponding trigger channel 210 for detection according to the bit of the data to be tested.

[0053] In one embodiment, the trigger register 220 may be used to configure the trigger condition of each trigger channel 210. Specifically, the host 400 may configure the trigger condition of each trigger channel 210 through the corresponding software and the trigger register 220. The trigger conditions of different trigger channels 210 may be the same or different.

[0054] In one embodiment, the user can set the trigger conditions of different trigger channels 210 through the host 400 to select the data to be tested under specific conditions for capture. For example, every 4 bits in the trigger register 220 (tri_mode[127:0]) are used to set the trigger conditions of a trigger channel 210. For example, tri_mode[3:0] represents the control signal of the trigger condition of the first trigger channel 210. tri_mode[7:4] represents the control signal of the trigger condition of the second trigger channel 210. Similarly, tri_mode[127:124] represents the control signal of the trigger condition of the 32nd trigger channel 210. Each control signal can be 4-bit data to detect the signal state of the data signal. Among them, 0000 can represent that the signal state of the data signal is not concerned. 0001 can represent that the signal state of the data signal is low level (0). 0010 can represent that the signal state of the data signal is high level (1). 0011 can represent that the signal state of the data signal is rising edge. 0100 can represent that the signal state of the data signal is a falling edge. 0101 can represent that the signal state of the data signal is an edge change, where the edge change refers to a rising edge or a falling edge. The specific setting of the above signal states may not be limited as long as it can meet specific test requirements.

[0055] In one embodiment, the trigger register 220 can detect whether each data signal meets the trigger condition configured by the software. For example, the trigger condition of Data_in[0] is set to a falling edge trigger. If Data_in[0] is detected to be 0 level, the corresponding bit_en[0] is set to 1, indicating that the data signal has met the trigger condition. For another example, the trigger condition of Data_in[0] is set to a signal transition trigger. If a rising edge or a falling edge is detected, bit_en[0] will also be set to 1. Each data signal has an independent bit_en[i] to indicate whether the data signal meets the trigger condition.

[0056] In one embodiment, the trigger register 220 can perform a logic operation on the output of each trigger channel 210, so as to realize a comprehensive trigger condition between different trigger channels 210. In this embodiment, the trigger register 220 can perform an AND operation on the outputs of 32 trigger channels 210, and when the data signal of each bit of the data to be tested meets the trigger condition in the corresponding trigger channel 210, it can be considered that the data to be tested meets the trigger condition, and a trigger enable signal (trigger_en) is output.

[0057] See also Figure 4 In one embodiment, the data storage module 300 can be used to store the test data in a fixed manner and read it out to the host 400. The data storage module 300 may include a register cache unit 310, a storage unit 320, a write operation control unit 330, a write trigger counting unit 340, an address management unit 350, a FIFO cache unit 360, a read operation control unit 370, a read trigger counting unit 380, and a state management unit 390.

[0058] In one embodiment, the register buffer unit 310 may be used to perform synchronization operations on the data to be tested, and write the buffered data to be tested into the storage unit 320 .

[0059] In one embodiment, the storage unit 320 can continuously and in real time temporarily store the data to be tested cached in the register cache unit 310. Since the data to be tested is written into the register cache unit 310 in real time, before the trigger detection module 200 outputs the trigger enable signal, the data to be tested can be written into the storage space of the storage unit 320 in sequence according to the timing. After the storage space of the storage unit 320 is full, new data to be tested can continue to be written into the storage unit 320 by overwriting.

[0060] In one embodiment, the write operation control unit 330 can be used to write the corresponding test data into the storage unit 320 according to the trigger enable signal. Specifically, when the trigger detection module 200 determines that a certain test data meets the trigger condition, the trigger enable signal can be output. Since the test data is written continuously in real time, at this time, the write operation control unit 330 can represent part of the test data stored before the trigger data, the trigger data, and part of the test data stored after the trigger data as test data according to the trigger enable signal and the current physical address of the trigger data stored in the storage unit 320, and store them fixedly in the storage unit 320, and the test data will not be overwritten in the current test link.

[0061] In one embodiment, a first write counter and a second write counter may be configured in the write trigger counting unit 340. The first write counter may be used to calculate the first physical address of the corresponding test data according to the physical address of the trigger data stored in the storage unit 320. The second write counter may be used to calculate the last physical address of the corresponding test data according to the current physical address of the trigger data stored in the storage unit 320.

[0062] In one embodiment, the storage unit 320 can store 256 groups of test data for explanation. After the trigger data is written into the storage unit 320, the serial number of the physical address where the trigger data is stored in the storage unit 320 can be represented as 238. At this time, the trigger data can be set in the middle position to accurately and continuously read the key data for positioning. That is, the number of the partial test data before the trigger data can be 128 groups, and the number of the partial test data after the trigger data can be 127 groups. The serial number of the first physical address of the test data can be represented as 110. The serial number of the last physical address of the test data can be represented as 109.

[0063] In one embodiment, the address management unit 350 may be used to obtain a first physical address and a last physical address, and store the first physical address in the FIFO buffer unit 360 in sequence.

[0064] In one embodiment, the storage unit 320 may include at least one storage space. When the number of storage spaces is one, the write trigger counting unit 340 may calculate the first physical address according to the size of the storage space and the current physical address of the trigger data stored in the storage space, so that the corresponding test data fills the storage space.

[0065] Furthermore, when there are multiple storage spaces, the write trigger counting unit 340 can calculate the first physical address of the corresponding test data according to the size of a storage space and the current physical address of a trigger data stored in a storage space, so that the corresponding test data can fill a storage space. After filling a storage space, the write operation control unit 330 can temporarily store other test data in the next storage space. When the trigger detection module 200 outputs the next trigger enable signal, that is, when the next trigger data appears, the write trigger counting unit 340 can also be used to calculate the first physical address of the corresponding test data according to the size of the next storage space and the current physical address of the next trigger data, so that the corresponding test data can be fixedly stored in sequence from the first physical address in the order of physical addresses until the next storage space is filled.

[0066] See also Figure 5 In one embodiment, the storage unit 320 includes two storage spaces, and the two storage spaces are divided into a first storage space 321 and a second storage space 322. The first storage space 321 and the second storage space 322 can both store 256 sets of test data. The serial number of the physical address in the first storage space 321 can be expressed as 0 to 255. The serial number of the physical address in the second storage space 322 can be expressed as 256 to 511.

[0067] Further, when the trigger detection module 200 sends the first trigger enable signal, the corresponding trigger data can be stored in the current physical address with a sequence number of 238. At this time, the part of the test data before the trigger data can be stored in the physical addresses with sequence numbers of 110 to 237 in sequence. The part of the test data after the trigger data can be stored in the physical addresses with sequence numbers of 239 to 255 and 0 to 109 in sequence. At this time, the sequence number 110 can be stored in the FIFO buffer unit 360.

[0068] Furthermore, during the process of writing the test data to the first storage space 321, and when the data is not completely written, if the trigger detection module 200 sends out the next trigger enable signal, the write operation control unit 330 may consider the trigger enable signal to be invalid and does not need to process the trigger enable signal until the test data is completely written to the first storage space 321, and if the trigger detection module 200 sends out the next trigger enable signal again.

[0069] Furthermore, after the test data is completely written into the first storage space 321, the test data stored in the first storage space 321 cannot be overwritten, and the new test data can be written into the second storage space 322. When the trigger detection module 200 sends the next trigger enable signal, the corresponding trigger data can be stored in the current physical address with sequence number 387. At this time, part of the test data before the corresponding trigger data can be stored in the physical addresses with sequence numbers 259 to 386 in sequence. Part of the test data after the corresponding trigger data is stored in the physical addresses with sequence numbers 388 to 511 and 256 to 258 in sequence. At this time, sequence number 387 can be stored in the FIFO buffer unit 360, and the timing of sequence number 387 is after sequence number 110.

[0070] In one embodiment, a write trigger counter may be further configured in the write trigger counting unit 340. The write trigger counter may count each time a valid trigger enable signal is detected, and output a write completion signal (debug_busy) when the count reaches a preset number of times, wherein the preset number of times is equal to the number of divided storage spaces.

[0071] In one embodiment, the read operation control unit 370 can be used to receive a read enable signal from the host 400, and read the first physical address stored in the FIFO buffer unit 360 in sequence according to the read enable signal. The storage unit 320 can be used to read the corresponding test data to the host 400 according to the first physical address.

[0072] Specifically, after the host 400 sends the first read enable signal to the read operation control unit 370, the read operation control unit 370 can read the first first physical address stored in the FIFO buffer unit 360, that is, 110, in a timing sequence. Subsequently, the FIFO buffer unit 360 can send the first first physical address to the storage unit 320 through the address management unit 350, and read the test data stored in the first storage space 321 to the host 400. The read order can be read out according to the order in which the test data is stored in the first storage space 321. The address of the read test data can be the same as the address stored in the first storage space 321.

[0073] Further, after the host 400 sends a second read enable signal to the read operation control unit 370, the read operation control unit 370 can read the second first physical address stored in the FIFO buffer unit 360, that is, 387, in a timing sequence. Subsequently, the FIFO buffer unit 360 can send the second first physical address to the storage unit 320 through the address management unit 350, and read the test data stored in the second storage space 322 to the host 400. The order of reading can be read out according to the order in which the test data is stored in the second storage space 322. The address of the read test data can be the same as the address stored in the second storage space 322.

[0074] In one embodiment, a read trigger counter may be configured in the read trigger counting unit 380. The read trigger counter may count when the test data in each storage space of the storage unit 320 is completely read out, and output a read completion signal when the count reaches a preset number.

[0075] In one embodiment, the state management unit 390 may receive a write completion signal, a read completion signal, data stored in a write trigger counter, and data stored in a read trigger counter. The state management unit 390 may receive a read instruction from the host 400 and transmit corresponding signals / data to the host 400 according to the read instruction.

[0076] It can be seen that the above scheme can be applied to test requirements in different scenarios, and its design will not affect the main functions of the system. Due to its simple interface and easy integration, it can be easily integrated into existing designs, and can be flexibly applied in various complex scenarios to meet a variety of test requirements. Through the flexible configuration of the trigger times by the software, users can adjust the captured trigger conditions according to the test requirements, which helps to cope with the specific needs in different test scenarios and enhances applicability. The collected test data has the "negative delay" capability, which can store and capture the data signal before the trigger point. By capturing the data before and after the trigger point, especially the data before the trigger, the background information that caused the event can be better understood. This negative delay capability is particularly useful for analyzing the premonition signals before the fault and the occurrence process of complex events. The trigger conditions are flexible and diverse, supporting edge jump trigger, Boolean trigger equation, level trigger, and multi-channel Boolean operation synchronous trigger. These trigger conditions can be configured according to different scenarios and design requirements to ensure that important data can be accurately located in complex and changeable designs. The storage circuit can store signal waveforms of multiple clock cycles and store these data in the internal buffer for analysis, which can provide sufficient historical data for further analysis and help capture long-term signal behavior. At the same time, it supports displaying captured signal waveforms or other data as graphics or waveforms through simulation or host computers. Through intuitive visualization results, developers can more easily analyze the behavior of digital signals, especially when troubleshooting, which can provide more accurate analysis results. This visualization capability improves development efficiency and makes signal analysis and fault diagnosis more transparent and clear.

[0077] The present invention also discloses a chip data processing method, which can be applied to the above chip to test the internal interface of the chiplet. The data processing method may include:

[0078] Step S10, acquiring the test data of the core particle in real time;

[0079] Step S20: when the data to be tested meets the trigger condition, output a trigger enable signal, and represent the data to be tested as trigger data;

[0080] Step S30: According to the trigger enable signal and the current physical address of the trigger data storage, part of the test data stored before the trigger data, the trigger data, and part of the test data stored after the trigger data are represented as test data and stored fixedly.

[0081] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A logic analyzer, characterized in that: include: A data sampling module, connected to the core particle for continuous and real-time acquisition of the data to be tested of the core particle; A trigger detection module, used to output a trigger enable signal when the data to be tested meets the trigger condition, and represent the data to be tested as trigger data; as well as A data storage module, used for temporarily storing the data to be tested continuously and in real time; Among them, the data storage module is also used to represent and fixedly store part of the data to be tested stored before the trigger data, the trigger data, and part of the data to be tested stored after the trigger data according to the trigger enable signal and the current physical address of the trigger data stored in the data storage module.

2. The logic analyzer according to claim 1, characterized in that: The data sampling module includes at least one multiplexer group, and the multiplexer group includes at least one multiplexer; the multiplexer is communicatively connected to the multiplex transmission channel of the core particle, and is used to select a sampling signal from the multiplex transmission channel for output; the sampling signals within the same clock cycle constitute the data to be tested.

3. The logic analyzer according to claim 1, characterized in that: The trigger detection module comprises: trigger channels, the number of which corresponds to the number of bits of the data to be tested, and the data signal of each bit of the data to be tested is transmitted to the corresponding trigger channel; and The trigger register is used to configure the trigger condition of each of the trigger channels, and output the trigger enable signal when the data signals in all the trigger channels meet the corresponding trigger conditions.

4. The logic analyzer according to claim 1, characterized in that: The data storage module also includes: A storage unit, used for temporarily storing the data to be tested continuously and in real time; A write trigger counting unit, used for calculating the first physical address of the test data according to the current physical address of the trigger data stored in the storage unit; A FIFO buffer unit, used for storing the first physical address; and A write operation control unit is used to store the test data in the storage unit in fixed order according to the trigger enable signal and the first physical address.

5. The logic analyzer according to claim 4, characterized in that: When the number of storage spaces in the storage unit is one, the write trigger counting unit is used to calculate the first physical address according to the size of the storage space and the current physical address, so that the test data is fixedly stored in sequence from the first physical address in the order of the physical addresses until the storage space is full.

6. The logic analyzer according to claim 4, characterized in that: When the number of storage spaces in the storage unit is multiple: The write trigger counting unit is used to calculate the first physical address of the corresponding test data according to the size of a certain storage space and the current physical address of a certain trigger data, so that the corresponding test data is fixedly stored in sequence from the first physical address according to the order of the physical addresses until a certain storage space is filled; After the test data is fixedly stored in a certain storage space, the write operation control unit temporarily stores other data to be tested in the next storage space until the next trigger data appears. The write trigger counting unit is used to calculate the first physical address of the corresponding test data according to the size of the next storage space and the current physical address of the next trigger data, so that the corresponding test data is fixedly stored in sequence from the first physical address in the order of the physical addresses until the next storage space is full.

7. The logic analyzer according to claim 4, characterized in that: The write trigger counting unit is configured with a write trigger counter, which is used to count each time a trigger enable signal is detected, and when the count reaches a preset number of times, output a write completion signal and transmit it to the host, wherein the preset number of times is equal to the amount of storage space in the storage unit.

8. The logic analyzer according to claim 4, characterized in that: The data storage module also includes a read operation control unit, which is used to read the first physical address stored in the FIFO cache unit according to a read enable signal of the host; the storage unit is used to read the corresponding test data to the host according to the first physical address.

9. The logic analyzer according to claim 8, characterized in that: The data storage module also includes a read trigger counting unit, in which a read trigger counter is configured. The read trigger counter is used to count when the test data in each storage space of the storage unit is completely read out, and when the count reaches a preset number of times, a read completion signal is output and transmitted to the host.

10. A chip, characterized in that: The invention comprises a logic analyzer and a chip according to any one of claims 1 to 9.

11. A chip data processing method, characterized in that: include: Continuously and in real time obtain the test data of the core particle; When the data to be tested meets the trigger condition, a trigger enable signal is output, and the data to be tested is represented as trigger data; According to the trigger enable signal and the current physical address of the trigger data storage, part of the test data stored before the trigger data, the trigger data, and part of the test data stored after the trigger data are represented as test data and fixedly stored.

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