Multi-means combined soft defect fault positioning method for large-scale integrated circuit

Abstract

The invention belongs to the field of integrated circuit fault analysis, and particularly relates to a large-scale integrated circuit multi-means combined soft defect fault positioning method, which comprises the following steps of: narrowing a multi-input vector range by adopting a dichotomy, and quickly determining a part of logic vectors associated with a fault phenomenon; the method comprises the following steps: dividing an internal transistor of a large-scale integrated circuit into a plurality of functional modules according to functions, and testing each functional module in a grading manner in combination with a nanoprobe and a dichotomy under the excitation of a part of logic vectors associated with a fault phenomenon; for the screened abnormal function modules, whether transistor faults or / and connecting line faults exist or not is judged; if a transistor fault or / and a connecting line fault exist, scanning the fault transistor and an accessory line by adopting an SEM, slicing a fault part by adopting an FIB, and observing the fault morphology by adopting a TEM; according to the method, the positioning range is effectively narrowed, fault excitation conditions are refined, soft errors in a large range are converted into hard errors in a small range, and then fault points are quickly positioned.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit fault analysis, and in particular relates to a large-scale integrated circuit multi-means joint soft defect fault location method. Background Art

[0002] Integrated circuit defects can be divided into hard defects and soft defects. Hard defects mainly refer to defects whose fault phenomena are stable and do not change with changes in the environment and test conditions, while soft defects mainly refer to defects whose fault phenomena change with changes in the environment and test conditions. At present, the industry mainly uses methods such as Photon Emission Microscopy (PEM), Optical Beam Induced Resistance Change (OBIRCH), Optical Beam Induced Current (OBIC), and Dynamic Thermal Laser Stimulation (D-TLS) to locate electrical performance faults in integrated circuits. The working principles of the equipment required for various positioning methods and their applicable fault positioning ranges are subject to specific limitations. For example, PEM and OBIRCH are mainly used to locate hard defects with obvious leakage in integrated circuits, while D-TLS uses the thermal effect of lasers to heat soft defects in semiconductor integrated circuits, and changes the physical properties of the soft defect fault point with the laser thermal effect to change the integrated circuit test results, and then locates the soft defects according to the physical position of the laser beam scanning point when the test results change. For large-scale integrated circuits, which integrate millions of transistors, the method of locating soft defects by scanning one by one through D-TLS technology is not feasible, and not all soft defects are sensitive to the thermal effect of lasers. At the same time, the electrical performance fault location method needs to be combined with the physical structure fault location method in real time, such as scanning electron microscopy (Scanning electron Microscopy, SEM), focused ion beam (Focused Ion Beam, FIB), transmission electron microscopy (Transmission electron microscopy, TEM), energy dispersive X-ray spectrometer (Energy Dispersive X-Ray Spectroscopy, EDX), etc., to finally locate the cause of the electrical performance failure. Therefore, there is currently no fast and efficient method in the industry for locating soft defects in large-scale integrated circuits. Summary of the invention

[0003] In view of the fact that there is no fast and efficient method for locating soft defects in large-scale integrated circuits, the present invention proposes a multi-method combined soft defect fault locating method for large-scale integrated circuits, which specifically includes the following steps:

[0004] On the software input vector, the binary search method is used to narrow the range of multiple input vectors and quickly identify some logic vectors associated with the fault phenomenon;

[0005] In terms of circuit hardware structure, the internal transistors of the LSI are divided into multiple functional modules according to their functions. Under the stimulation of some logic vectors associated with the fault phenomenon, the nanoprobe probe and the dichotomy method are combined to test each functional module in a hierarchical manner.

[0006] For the abnormal function modules screened out, determine whether there is a transistor fault and / or a connection line fault;

[0007] If there is a transistor failure or / and a connecting line failure, the faulty transistor and the accessory circuits are scanned by SEM, the faulty part is sliced ​​by FIB, and then the fault morphology is observed by TEM. In addition, the material composition is analyzed by EDX to obtain the cause of the electrical performance failure.

[0008] Compared with the prior art, the present invention has the following beneficial effects:

[0009] 1. For soft defects in integrated circuits, especially soft defects in large-scale integrated circuits, the fault phenomenon is unstable and there is no clear positioning method;

[0010] 2. The method of using D-TLS to scan integrated circuits point by point for positioning is not feasible for large-scale integrated circuits;

[0011] 3. Based on the actual analysis and positioning case summary, this method proposes a dichotomy analysis based on the logic structure of large-scale integrated circuits, refines the non-focused soft fault phenomenon of large-scale integrated circuits, effectively narrows the fault range, and focuses the large-scale soft faults into small-scale hard faults;

[0012] 4. Using nanoprobe to monitor the electrical performance of structures within a smaller range after binary analysis can further reduce the scope of the fault.

[0013] 5. Combine nanoprobe, IV curve tracer, and OBIRCH equipment to further confirm the small-scale fault point, and then combine FIB and EDX methods to perform destructive physical structure analysis on the extremely small-scale fault point. The multi-method combined analysis method can efficiently and accurately locate the fault point and provide clear materials for fault cause analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1It is a flow chart of a method for locating soft defects in a large-scale integrated circuit by multiple means according to the present invention;

[0015] Figure 2 It is a schematic diagram of the structure of a large-scale integrated circuit;

[0016] Figure 3 A schematic diagram of a fault line with a reduced range after logical vector positioning in one embodiment of the present invention;

[0017] Figure 4 The nanoprobe combined with IV curve test results after positioning the circuit structure of the present invention;

[0018] Figure 5 The nanoprobe combined with OBIRCH test results after positioning the circuit structure of the present invention;

[0019] Figure 6 This is the physical structure positioning result of the fault point using FIB combined with EDX in the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The present invention proposes a multi-method joint soft defect fault location method for large-scale integrated circuits, which specifically includes the following steps:

[0022] On the software input vector, the binary search method is used to narrow the range of multiple input vectors and quickly identify some logic vectors associated with the fault phenomenon;

[0023] In terms of circuit hardware structure, the internal transistors of the LSI are divided into multiple functional modules according to their functions. Under the stimulation of some logic vectors associated with the fault phenomenon, the nanoprobe probe and the dichotomy method are combined to test each functional module in a hierarchical manner.

[0024] For the abnormal function modules screened out, determine whether there is a transistor fault and / or a connection line fault;

[0025] If there is a transistor failure or / and a connecting line failure, the faulty transistor and the accessory circuits are scanned by SEM, the faulty part is sliced ​​by FIB, and then the fault morphology is observed by TEM. In addition, the material composition is analyzed by EDX to obtain the cause of the electrical performance failure.

[0026] In the face of the unfocused soft fault phenomenon of large-scale integrated circuits and the long line length that is difficult to locate, the present invention proposes a dichotomy analysis based on the logical structure of large-scale integrated circuits, which effectively narrows the positioning range, refines the fault excitation conditions, and converts soft errors in a large range into hard errors in a small range. The OBIRCH fault location method is combined with the thermal excitation effect to determine the small-range hard error fault point, and then FIB and EDX physical analysis methods are used to quickly and accurately locate the soft defects in large-scale integrated circuits.

[0027] This embodiment uses Figure 1 The scheme of the present invention is described by taking the circuit structure of as an example. Figure 2 To give a schematic diagram of a large-scale integrated circuit structure, Figure 2 The main function of the circuit structure given is to receive multi-bit serial data through the input TTL port, receive and store the data in the dedicated digital function circuit, and distribute the data through the multi-channel RS-422 output interface circuit after passing the verification. Under the control of the input data signal Data1, the clock signal CLK, the chip select signal CP and other signals, the 1152-bit serial data is serially shifted between 1152 cascaded D flip-flops D0~D1151, and after passing the verification, it is cached by the TR1~TR23 registers and then distributed and output.

[0028] The binary search method is an algorithm widely used in mathematics and computer science. Its basic principle is to find the solution to the problem by continuously halving the problem size, thereby quickly narrowing the search scope. In circuit fault detection, the binary search method can be extended to a method of segmenting the circuit and locating faults at the logic level.

[0029] Multiple logic vectors are quickly checked using binary search to find the faulty data bit that does not match the vector range of the input data, determine the abnormal logic vector, and find that the faulty data always follows a certain data bit.

[0030] Table 1. Quick check list by binary method

[0031]

[0032]

[0033] The structure of the small-scale fault line located by the logic vector binary test is as follows: Figure 3 , nanoprobe is used to verify the four possibilities and determine the abnormal line part. For line structures with more possibilities, the binary method can also be used for judgment.

[0034] Nanoprobe was used to scan the IV curves of test points A and B of the abnormal circuit to confirm the abnormal phenomenon. Then, 0.2V / 0.635mA was added to test points A and B for OBIRCH test. The test results showed that there was an obvious bright spot between test points A and B, indicating that there was abnormal leakage current at that location.

[0035] The abnormal leakage current position located by OBIRCH was observed by FIB sample preparation, and physical element analysis was performed using EDX. It was found that there was an unetched titanium (Ti) bridge between the two metallized aluminums, and there was excess tungsten (W).

[0036] Specifically, this embodiment proposes a specific implementation method of a multi-method joint soft defect fault location method for a large-scale integrated circuit of the present invention, which specifically includes the following steps:

[0037] This time, we first used the binary search method on the software input vector to narrow the range of multiple input vectors, quickly identify a small number of logic vectors associated with the fault phenomenon, and increase the frequency and probability of soft defects in the optical emission positioning process under the condition of fixing the input of the small number of logic vectors that cause the failure of the large-scale integrated circuit.

[0038] Secondly, in terms of circuit hardware structure, millions of transistors inside large-scale integrated circuits are classified into functional modules. Under the stimulation of a small number of logic vectors associated with the fault phenomenon, nanoprobe probes and dichotomy are combined to test functional modules in stages, narrowing the scope of internal chip circuit faults to the functional module level. Internal integrated circuit faults can be divided into transistor faults and connection line faults. Transistor faults can be divided into power supply anomalies, gate oxide leakage, and active area anomalies. The above anomalies are normalized. Connection line faults will cause transistor power supply anomalies, resulting in transistor output anomalies. Power supply anomalies will cause transistor working state anomalies, resulting in transistor output anomalies. Gate oxide leakage will cause transistor gate control anomalies, resulting in uncontrolled transistor output. Active area anomalies will cause transistor carrier state anomalies, resulting in transistor output anomalies. Considering that the output of the previous transistor provides gate voltage for the next transistor, the transistor gate voltage is tested on the chip hardware circuit structure to further narrow the fault scope to the gate level.

[0039] Subsequently, nanoprobe is used to locate the previously normalized connection lines, gate voltage of the previous device, source voltage, and leakage voltage associated with the transistor with abnormal gate voltage. OBIRCH is used for laser thermal scanning of the metal wire part, and PEM is used for light emission positioning of the transistor part to locate the fault at the transistor level.

[0040] After locating the transistor-level fault, it is necessary to combine the physical structure fault location method, use SEM to scan the faulty transistor and its accessory circuits, use FIB to slice the faulty part and then use TEM to observe the fault morphology, and combine EDX to perform material composition analysis to finally locate the cause of the electrical performance failure.

[0041] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-method joint soft defect fault location method for large-scale integrated circuits, characterized in that: The specific steps include: On the software input vector, the binary search method is used to narrow the range of multiple input vectors and quickly identify some logic vectors associated with the fault phenomenon; In terms of circuit hardware structure, the internal transistors of the LSI are divided into multiple functional modules according to their functions. Under the stimulation of some logic vectors associated with the fault phenomenon, the nanoprobe probe and the dichotomy method are combined to test each functional module in a hierarchical manner. For the abnormal function modules screened out, determine whether there is a transistor fault and / or a connection line fault; If there is a transistor failure or / and a connecting line failure, the faulty transistor and the accessory circuits are scanned by SEM, the faulty part is sliced ​​by FIB, and then the fault morphology is observed by TEM. In addition, the material composition is analyzed by EDX to obtain the cause of the electrical performance failure.

2. The multi-method joint soft defect fault location method for large-scale integrated circuits according to claim 1 is characterized in that: When the binary search method is used to narrow the range of multiple input vectors, the input and output of the trigger and register are judged whether they are within the set range based on the input-output relationship of the logic vector. If the relationship between the input and output of a logic vector is not within the set range, the logic vector is determined to be a logic vector associated with the fault.

3. The method for locating soft defects in a large-scale integrated circuit by multiple means according to claim 1, characterized in that: When the logic vector is determined to be a logic vector associated with a fault, the devices between the input and output of the logic device are divided using a binary method, and the input and output of each device are used as test points to test whether there is an abnormality in the input and output between the two test points.

4. The multi-method joint soft defect fault location method for large-scale integrated circuits according to claim 1 is characterized in that: Nanoprobe is used to perform probe testing and positioning on the connection lines, gate voltage of the previous device, source voltage, and leakage voltage associated with the transistor with abnormal gate voltage. OBIRCH is used for laser thermal scanning of the metal line part, and PEM is used for light emission positioning of the transistor part.

5. The multi-method joint soft defect fault location method for large-scale integrated circuits according to claim 4 is characterized in that: Considering that the output of the previous stage transistor provides the gate voltage for the subsequent stage transistor, the transistor gate voltage is tested on the chip hardware circuit structure to further narrow the fault scope and reduce the fault scope to the gate level.

6. The multi-method joint soft defect fault location method for large-scale integrated circuits according to claim 1 is characterized in that: When using the binary method for positioning, the circuit needs to be divided into multiple test points according to the test requirements, and the status of each test point with the input and output ends under various working conditions should be tested in sequence from the whole to the part.

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