TSV (Through Silicon Via) pre-bonding detection circuit based on current charging and discharging

Abstract

The invention discloses a TSV (Through Silicon Via) pre-bonding detection circuit based on current charging and discharging. The TSV pre-bonding detection circuit comprises a charging current source, a discharging current source, a transmission gate switch array and a time detection circuit, the time detection circuit is used for respectively acquiring the time required by the charging stage and the time required by the discharging stage, so that the detection of an open-circuit fault, a leakage fault and an open-circuit leakage double fault is realized, and misjudgment caused by coexistence of different faults is avoided. In a corresponding charging and discharging current source, a current input operational amplifier is used to realize a clamping function of a drain end voltage of a current mirror, the copying accuracy of the current mirror is improved, the shielding effect of a cascode tube is used to realize isolation of the drain end voltage of the current mirror, and the reliability of the current mirror is improved. The current of the charging and discharging current source in the charging stage and the discharging stage in the detection process is kept unchanged, so that the linearity of the detection process is improved.

Description

Technical Field

[0001] The invention belongs to the field of chip detection, and in particular relates to a TSV pre-bonding detection circuit based on current charging and discharging. Background Art

[0002] In recent years, due to physical limitations, it is difficult for traditional two-dimensional integrated circuits based on planar technology to improve chip performance through scaling technology, and Moore's Law is gradually becoming invalid. Three-dimensional integrated circuits are considered to be a promising technology route. This technology integrates more circuits in the same area by vertically connecting multiple chips, increasing chip density, improving signal transmission speed, and reducing power consumption. However, the silicon through vias that connect each chip are prone to defects. Even though three-dimensional integrated circuit manufacturing technology has made great progress, the detection of silicon through via defects is still an important challenge facing the semiconductor industry.

[0003] Through-silicon via inspection can be divided into two categories: pre-bonding inspection and post-bonding inspection. Pre-bonding inspection can solve defects that occur during the through-silicon via manufacturing process, such as voids, open circuits, and leakage; while post-bonding inspection focuses on defects caused by wafer thinning, mold alignment, etc. Pre-bonding inspection can detect defective through-silicon vias before stacking, increasing the possibility of known qualified chips. Since the lack of known qualified chips has been proven to be a serious limitation affecting the yield of three-dimensional integrated circuit stacking, an effective pre-bonding through-silicon via inspection method is the key to achieving the commercialization of three-dimensional integrated circuits. The through-silicon via before bonding is difficult to detect because its tail end is buried in the substrate. Therefore, only the front end of the through-silicon via can be accessed, and there are fewer test resources available, which increases the difficulty of pre-bonding through-silicon via testing.

[0004] An existing pre-bonding through silicon via detection circuit based on the principle of switch capacitor circuit, which equates the switch capacitor circuit to a resistor, the size of which depends on the cycle of the switch alternating conduction and the through silicon via equivalent capacitance, establishes the relationship between the through silicon via equivalent capacitance and the resistor, and obtains the through silicon via equivalent capacitance result by measuring the resistor. An existing pre-bonding through silicon via detection circuit based on the principle of weak current source discharge. The circuit regards the through silicon via as a capacitive load. When there is a defect in the through silicon via, its equivalent capacitance value will change, causing the time required for the detection circuit to discharge to the threshold voltage to change. In summary, most of the existing pre-bonding through silicon via detection is based on a single type of defect for classification discussion, and due to the technical difficulty of pre-bonding through silicon via testing, it is difficult to obtain sufficient fault information for fault diagnosis at this stage. The judgment threshold can only be obtained by giving the expected acceptable fault level, and the through silicon via is generally divided into fault-free through silicon via and faulty through silicon via, and the fault level and fault type of the through silicon via cannot be accurately analyzed. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a TSV pre-bonding detection circuit based on current charging and discharging. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a TSV pre-bonding detection circuit based on current charging and discharging, comprising:

[0007] A charging current source, a discharging current source, a transmission gate switch array and a time detection circuit; wherein,

[0008] The transmission gate switch array is used to control the switching of the transmission gate switches inside the array so that the TSV pre-bonding detection circuit is in the charging stage, the resetting stage, the pre-charging stage or the discharging stage in sequence;

[0009] The charging current source is used to charge the TSV to be detected connected to the TSV pre-bonding detection circuit during the charging phase;

[0010] The discharge current source is used to discharge the TSV to be detected connected to the TSV pre-bonding detection circuit during the discharge phase;

[0011] The time detection circuit is used to detect the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage, and determine whether the TSV to be detected has a fault.

[0012] In one embodiment of the present invention, a transmission gate switch array comprises:

[0013] Transmission gate switch SW1, transmission gate switch SW5 and N combination arrays; wherein,

[0014] The first end of the transmission gate switch SW1 is connected to the output end of the charging current source, and the second end is connected to the first end of the transmission gate switch SW5;

[0015] The second end of the transmission gate switch SW5 is grounded;

[0016] For each combination array, the first end of the combination array is connected to the second end of the transmission gate switch SW1, the second end is connected to the input end of the discharge current source, and the third end is connected to the power supply voltage V DD , the fourth end is connected to the TSV to be detected corresponding to the combination array; N represents the total number of TSVs to be detected.

[0017] In one embodiment of the present invention, the structure of each combination array is the same, wherein the i-th combination array includes:

[0018] Transmission gate switch SW2_i, transmission gate switch SW3_i and transmission gate switch SW4_i; wherein,

[0019] The first end of the transmission gate switch SW2_i serves as the first end of the combination array, and the second end is connected to the first end of the transmission gate switch SW3_i;

[0020] The second end of the transmission gate switch SW3_i serves as the third end of the combination array;

[0021] The first end of the transmission gate switch SW4_i serves as the second end of the combination array, and the second end is connected to the second end of the transmission gate switch SW2_i to serve as the fourth end of the combination array; i represents the serial number of the TSV to be detected currently.

[0022] In one embodiment of the present invention, the transmission gate switch array controls the switching of the transmission gate switches inside itself to put the TSV pre-bonding detection circuit in the charging stage, the resetting stage, the pre-charging stage or the discharging stage, including:

[0023] The transmission gate switch array controls the transmission gate switch SW1 and the transmission gate switch SW2_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW5, the transmission gate switch SW3_i corresponding to the TSV to be detected, and the transmission gate switch SW4_i to be turned off, so that the TSV pre-bonding detection circuit is in a charging stage;

[0024] The transmission gate switch array controls the transmission gate switch SW5 and the transmission gate switch SW2_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW3_i corresponding to the TSV to be detected, and the transmission gate switch SW4_i to be turned off, so that the TSV pre-bonding detection circuit is in a reset stage;

[0025] The transmission gate switch array controls the transmission gate switch SW3_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW5 and the transmission gate switches SW2_i and SW4_i corresponding to the TSV to be detected are turned off, so that the TSV pre-bonding detection circuit is in a pre-charging stage;

[0026] The transmission gate switch array controls the transmission gate switch SW4_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW5, the transmission gate switch SW2_i corresponding to the TSV to be detected, and the transmission gate switch SW3_i to be turned off, so that the TSV pre-bonding detection circuit is in the discharge stage.

[0027] In one embodiment of the present invention, the electrical model of the TSV to be detected includes:

[0028] a non-fault TSV equivalent circuit, an open-fault TSV equivalent circuit, a leakage-fault TSV equivalent circuit, or an open-leakage double-fault TSV equivalent circuit; wherein,

[0029] The fault-free TSV equivalent circuit includes a capacitor C1 connected to ground;

[0030] The open circuit fault TSV equivalent circuit includes: a grounded capacitor C2 and a grounded capacitor C3, the grounded capacitor C2 and the grounded capacitor C3 are connected at a first normalized position, and an open circuit fault exists at the first normalized position x, x∈[0,1], wherein x=0 indicates that the open circuit fault occurs at the top of the TSV, x=0.5 indicates that the open circuit fault occurs at the midpoint of the TSV, and x=1 indicates that the open circuit fault occurs at the bottom of the TSV, the capacitance value of the capacitor C2 is x times the capacitance value of the capacitor C1, and the capacitance value of the capacitor C3 is (1-x) times the capacitance value of the capacitor C1; when an open circuit fault occurs, the capacitor C2 serves as a load capacitor, and the capacitor C3 does not work;

[0031] The leakage fault TSV equivalent circuit includes: a grounded resistor R1 and a grounded capacitor C4, the capacitance value of the capacitor C4 is equal to that of the capacitor C1, and the resistor R1 and the capacitor C4 are connected in parallel;

[0032] The open-circuit leakage double fault TSV equivalent circuit includes: a grounded capacitor C5, a grounded resistor R2 and a grounded capacitor C6, the grounded capacitor C5 and the grounded resistor R2 are connected in parallel, the grounded resistor R2 and the grounded capacitor C6 are connected at a second normalized position, and an open-circuit fault exists at the second normalized position y; y∈[0,1], wherein y=0 indicates that the open-circuit fault occurs at the top of the TSV, y=0.5 indicates that the open-circuit fault occurs at the midpoint of the TSV, and y=1 indicates that the open-circuit fault occurs at the bottom of the TSV, the capacitance value of the capacitor C5 is y times the capacitance value of the capacitor C1, and the capacitance value of the capacitor C6 is (1-y) times the capacitance value of the capacitor C1; when an open-circuit leakage double fault occurs, the capacitor C5 acts as a load capacitor, and the capacitor C6 does not work.

[0033] In one embodiment of the present invention, any one of the charging current source and the discharging current source includes:

[0034] NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, NMOS transistor MN8, NMOS transistor MN9, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PMOS transistor MP6, PMOS transistor MP7, PMOS transistor MP8, PMOS transistor MP9, resistor R, bias voltage source VBIAS1 and bias voltage source VBIAS2; wherein,

[0035] The source of the NMOS tube MN1 is grounded, the gate is connected to the gate of the NMOS tube MN2, and the drain is connected to the drain of the PMOS tube MP1;

[0036] The source of the NMOS tube MN2 is connected to the first end of the resistor R, the gate is connected to the drain of the NMOS tube MN1, and the drain is connected to the drain of the PMOS tube MP2;

[0037] The source of the NMOS tube MN3 is connected to the source of the NMOS tube MN1, the gate is connected to the gate of the NMOS tube MN4, and the drain is connected to the drain of the PMOS tube MP5;

[0038] The source of the NMOS tube MN4 is connected to the source of the NMOS tube MN3, the gate is connected to the gate of the NMOS tube MN1, and the drain is connected to the drain of the PMOS tube MP6;

[0039] The source of the NMOS tube MN5 is connected to the source of the NMOS tube MN4, the gate is connected to the gate of the NMOS tube MN6, and the drain is connected to the source of the NMOS tube MN7;

[0040] The source of the NMOS tube MN6 is connected to the source of the NMOS tube MN5, the gate is connected to the drain of the PMOS tube MP7, and the drain is connected to the source of the NMOS tube MN8;

[0041] The gate of the NMOS tube MN7 is connected to the gate of the NMOS tube MN8, and the drain is connected to the drain of the PMOS tube MP7;

[0042] The source of the NMOS tube MN8 is connected to the source of the NMOS tube MN9, the gate is connected to its own drain, and the drain is connected to the drain of the PMOS tube MP8;

[0043] The gate of the NMOS tube MN9 is connected to the first end of the bias voltage source VBIAS2;

[0044] The source of the PMOS tube MP1 is connected to the source of the PMOS tube MP2, and the gate is connected to the gate of the PMOS tube MP2;

[0045] The gate of the PMOS tube MP2 is connected to its own drain;

[0046] The source of the PMOS tube MP3 is connected to the source of the PMOS tube MP2, the gate is connected to the gate of the PMOS tube MP4, and the drain is connected to the source of the PMOS tube MP5;

[0047] The source of the PMOS tube MP4 is connected to the source of the PMOS tube MP3, the gate is connected to the drain of the PMOS tube MP5, and the drain is connected to the source of the PMOS tube MP6;

[0048] The gate of the PMOS tube MP5 is connected to the gate of the PMOS tube MP6;

[0049] The source of the PMOS tube MP6 is connected to the source of the PMOS tube MP9, and the gate is connected to its own drain;

[0050] The source of the PMOS tube MP7 is connected to the source of the PMOS tube MP4, and the gate is connected to the gate of the PMOS tube MP1;

[0051] The source of the PMOS tube MP8 is connected to the source of the PMOS tube MP7, and the gate is connected to the gate of the PMOS tube MP7;

[0052] The gate of the PMOS tube MP9 is connected to the second end of the bias voltage source VBIAS1;

[0053] The second end of the resistor R is connected to the source of the NMOS transistor MN1;

[0054] A first terminal of the bias voltage source VBIAS1 is connected to the source of the PMOS tube MP8;

[0055] The second end of the bias voltage source VBIAS2 is connected to the source of the NMOS transistor MN6.

[0056] In one embodiment of the present invention, in the charging current source or the discharging current source, the NMOS tube MN1, the NMOS tube MN2, the PMOS tube MP1, the PMOS tube MP2 and the resistor R constitute a self-biased reference current source; the NMOS tube MN3, the NMOS tube MN4, the PMOS tube MP5 and the PMOS tube MP6 constitute a first current input operational amplifier; the NMOS tube MN7, the NMOS tube MN8, the PMOS tube MP7 and the PMOS tube MP8 constitute a second current input operational amplifier.

[0057] In one embodiment of the present invention, the time detection circuit includes:

[0058] Buffer buffer, inverter INV, two-to-one multiplexer MUX, AND gate AND, counter counter and memory RAM; among them,

[0059] The input end of the buffer is connected to the first end of the discharge current source, and the output end is connected to the first input end of the two-to-one multiplexer MUX;

[0060] The input end of the inverter INV is connected to the first end of each combination array, and the output end is connected to the second input end of the two-to-one multiple selector MUX;

[0061] The control end of the two-to-one multiple selector MUX receives the control signal charge, and the output end is connected to the first input end of the AND gate AND;

[0062] The second input terminal of the AND gate AND is connected to the clock signal CLK, and the output terminal is connected to the first input terminal of the counter counter;

[0063] The second input terminal of the counter counter is connected to the control signal CTRL, and the output terminal is connected to the first input terminal of the memory RAM;

[0064] The second input terminal of the memory RAM is connected to the output signal of the two-to-one multiplexer MUX.

[0065] In one embodiment of the present invention, the time detection circuit detects the TSV to be detected according to the time required for the charging stage and the time required for the discharging stage, and determines whether the TSV to be detected has a fault, including:

[0066] The time detection circuit detects the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage, and when the time required in the charging stage and the time required in the discharging stage remain unchanged, it is determined that the TSV to be detected is normal;

[0067] When the time required for the charging stage and the time required for the discharging stage are reduced in the same proportion, it is determined that the TSV to be detected has an open circuit fault;

[0068] When the time required for the charging stage and the time required for the discharging stage are both reduced, but the reduction ratios are different, it is determined that the TSV to be detected has an open-circuit leakage double fault;

[0069] When the time required for the charging stage increases, it is determined that the TSV to be detected has a leakage fault.

[0070] Beneficial effects of the present invention:

[0071] In the solution provided by the present invention, the time required for the charging stage and the time required for the discharging stage are respectively acquired by using a time detection circuit, thereby realizing the detection of open circuit faults, leakage faults and open circuit leakage dual faults, and avoiding the misjudgment caused by the coexistence of different faults. In the corresponding charging and discharging current source, the current input operational amplifier is used to realize the clamping function of the current mirror drain voltage, improve the current mirror replication accuracy, and the shielding effect of the common source and common gate tube is used to realize the isolation of the current mirror drain voltage, so that the current of the charging and discharging current source in the charging stage and the discharging stage during the detection process remains unchanged, so as to improve the linearity of the detection process. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 A schematic diagram of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention;

[0073] Figure 2 A schematic diagram of the structure of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention;

[0074] Figure 3 A schematic diagram of the structure of an electrical model of a TSV to be detected provided in an embodiment of the present invention;

[0075] Figure 4 A schematic diagram of the structure of a charge-discharge current source provided by an embodiment of the present invention;

[0076] Figure 5 A schematic diagram of a charging path of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention in a charging stage;

[0077] Figure 6 A schematic diagram of a reset path of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention in a reset phase;

[0078] Figure 7 A schematic diagram of a pre-charging path of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention in a pre-charging stage;

[0079] Figure 8 A schematic diagram of a discharge path of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention in a discharge stage. DETAILED DESCRIPTION

[0080] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0081] The principle diagram and structural diagram of a TSV pre-bonding detection circuit based on current charging and discharging provided by an embodiment of the present invention are shown in FIG. Figure 1 and Figure 2 The embodiment of the present invention provides a TSV (Through Silicon Via) pre-bonding detection circuit based on current charging and discharging, such as Figure 1 and Figure 2 As shown, this may include:

[0082] A charging current source, a discharging current source, a transmission gate switch array and a time detection circuit; wherein,

[0083] The transmission gate switch array is used to control the switching of the transmission gate switches inside the array so that the TSV pre-bonding detection circuit is in the charging stage, the resetting stage, the pre-charging stage or the discharging stage in sequence;

[0084] The charging current source is used to charge the TSV to be detected connected to the TSV pre-bonding detection circuit during the charging phase;

[0085] The discharge current source is used to discharge the TSV to be detected connected to the TSV pre-bonding detection circuit during the discharge phase;

[0086] The time detection circuit is used to detect the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage, and determine whether the TSV to be detected has a fault.

[0087] The embodiment of the present invention utilizes the capacitance characteristics of through silicon vias and proposes a TSV pre-bonding detection circuit based on current charging and discharging based on the charging and discharging of the capacitor by a current source; by utilizing a time detection circuit to obtain the time required for the charging stage and the time required for the discharging stage respectively, the detection of open circuit faults, leakage faults and open circuit leakage dual faults is realized, thereby avoiding misjudgment caused by the coexistence of different faults.

[0088] Specifically, the electrical model of the TSV to be tested is as follows: Figure 3 As shown, this may include:

[0089] a non-fault TSV equivalent circuit, an open-fault TSV equivalent circuit, a leakage-fault TSV equivalent circuit, or an open-leakage double-fault TSV equivalent circuit; wherein,

[0090] The fault-free TSV equivalent circuit includes capacitor C1 connected to ground;

[0091] The open circuit fault TSV equivalent circuit includes: a grounded capacitor C2 and a grounded capacitor C3, the grounded capacitor C2 and the grounded capacitor C3 are connected at a first normalized position, and an open circuit fault exists at the first normalized position x, x∈[0,1], wherein x=0 indicates that the open circuit fault occurs at the top of the TSV, x=0.5 indicates that the open circuit fault occurs at the midpoint of the TSV, and x=1 indicates that the open circuit fault occurs at the bottom of the TSV, the capacitance value of the capacitor C2 is x times the capacitance value of the capacitor C1, and the capacitance value of the capacitor C3 is (1-x) times the capacitance value of the capacitor C1; when an open circuit fault occurs, the capacitor C2 acts as a load capacitor, and the capacitor C3 does not work;

[0092] The leakage fault TSV equivalent circuit includes: a grounded resistor R1 and a grounded capacitor C4, the capacitance value of the capacitor C4 is equal to that of the capacitor C1, and the resistor R1 and the capacitor C4 are connected in parallel;

[0093] The open-circuit leakage double fault TSV equivalent circuit includes: a grounded capacitor C5, a grounded resistor R2 and a grounded capacitor C6, the grounded capacitor C5 and the grounded resistor R2 are connected in parallel, the grounded resistor R2 and the grounded capacitor C6 are connected at a second normalized position, and an open-circuit fault exists at the second normalized position y; y∈[0,1], wherein y=0 indicates that the open-circuit fault occurs at the top of the TSV, y=0.5 indicates that the open-circuit fault occurs at the midpoint of the TSV, y=1 indicates that the open-circuit fault occurs at the bottom of the TSV, the capacitance value of the capacitor C5 is y times the capacitance value of the capacitor C1, and the capacitance value of the capacitor C6 is (1-y) times the capacitance value of the capacitor C1; when an open-circuit leakage double fault occurs, the capacitor C5 acts as a load capacitor and the capacitor C6 does not work.

[0094] As can be understood, for the fault-free TSV equivalent circuit, since the TSV equivalent resistance is very small, the fault-free TSV is modeled as a single capacitor, see Figure 3 As shown in (a) of FIG. 1 , for the open-circuit fault TSV equivalent circuit, when the open fault completely cuts off the TSV path, an open-circuit fault occurs. Figure 3 (b) in the figure shows an open circuit fault occurring at the normalized position x. The open fault divides the TVS equivalent capacitance into two parts, and the capacitance value of the top capacitor C2 is defined as x times the capacitance value of the capacitor C1, and the capacitance value of the bottom capacitor C3 is defined as (1-x) times the capacitance value of the capacitor C1. By normalizing the position x, the position where the open circuit fault occurs can be clearly obtained, where x=0 means that the open circuit fault occurs at the top of the TSV, x=0.5 means that the open circuit fault occurs at the midpoint of the TSV, and x=1 means that the open circuit fault occurs at the bottom of the TSV. When an open circuit fault occurs, the capacitor C3 is isolated by the open fault, and only the capacitor C2 can work as a load; Figure 3(c) in the figure shows a leakage fault caused by a pinhole or crack. The characteristic of the leakage fault is that there is a leakage path between the TSV and the substrate. The leakage resistance can be represented by the resistor R1. The size of the leakage resistance depends only on the entire leakage area and has nothing to do with the location where the leakage fault occurs. The larger the leakage area, the more serious the leakage fault and the smaller the leakage resistance. Figure 3 (d) in the figure shows the equivalent TSV electrical model when open circuit fault and leakage fault coexist in the actual manufacturing process. It can be understood that since the fault-free TSV is equivalent to a single capacitor C1, the TSV is charged and discharged using a fixed current, and the change of the voltage on the TSV over time is: Wherein, Δ can be + or -, + indicates that it is in the charging state, - indicates that it is in the discharging state, I indicates the magnitude of the charging or discharging current, t indicates the charging and discharging time, C1 indicates the capacitance value of capacitor C1, and due to the open circuit fault, the equivalent TSV capacitance connected to the detection circuit undergoes the following linear change: C5 = xC1, when an open circuit fault occurs, the detection time required for the charging stage and the detection time required for the discharging stage are reduced by the same proportion, when a leakage fault occurs, there is an additional leakage path between the TSV and the ground, which increases the detection time required for the charging stage and reduces the detection time required for the discharging stage, and the open circuit fault and the leakage fault have opposite effects on the detection time required for the charging stage and the same effects on the detection time required for the discharging stage. The test time of the charging and discharging stage is automatically digitized by the counter and recorded in the memory, and the TSV fault condition can be judged according to the charging and discharging time, avoiding the opposite effects of the open circuit fault and the leakage fault on the detection circuit, so that the TSV with the two faults coexisting is mistakenly detected as a fault-free TSV.

[0095] For ease of understanding, various modules of the TSV pre-bonding detection circuit proposed in the embodiment of the present invention are introduced in detail below.

[0096] Charge and discharge current source

[0097] The charging current source charges the TSV to be detected connected to the TSV pre-bonding detection circuit during the charging phase.

[0098] The discharge current source discharges the TSV to be detected connected to the TSV pre-bonding detection circuit during the discharge phase.

[0099] Any of the charging current source and the discharging current source, such as Figure 4 As shown, they can include:

[0100] NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, NMOS transistor MN8, NMOS transistor MN9, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PMOS transistor MP6, PMOS transistor MP7, PMOS transistor MP8, PMOS transistor MP9, resistor R, bias voltage source VBIAS1 and bias voltage source VBIAS2; wherein,

[0101] The source of the NMOS tube MN1 is grounded, the gate is connected to the gate of the NMOS tube MN2, and the drain is connected to the drain of the PMOS tube MP1;

[0102] The source of the NMOS tube MN2 is connected to the first end of the resistor R, the gate is connected to the drain of the NMOS tube MN1, and the drain is connected to the drain of the PMOS tube MP2;

[0103] The source of the NMOS tube MN3 is connected to the source of the NMOS tube MN1, the gate is connected to the gate of the NMOS tube MN4, and the drain is connected to the drain of the PMOS tube MP5;

[0104] The source of the NMOS tube MN4 is connected to the source of the NMOS tube MN3, the gate is connected to the gate of the NMOS tube MN1, and the drain is connected to the drain of the PMOS tube MP6;

[0105] The source of the NMOS tube MN5 is connected to the source of the NMOS tube MN4, the gate is connected to the gate of the NMOS tube MN6, and the drain is connected to the source of the NMOS tube MN7;

[0106] The source of the NMOS tube MN6 is connected to the source of the NMOS tube MN5, the gate is connected to the drain of the PMOS tube MP7, and the drain is connected to the source of the NMOS tube MN8;

[0107] The gate of the NMOS tube MN7 is connected to the gate of the NMOS tube MN8, and the drain is connected to the drain of the PMOS tube MP7;

[0108] The source of the NMOS tube MN8 is connected to the source of the NMOS tube MN9, the gate is connected to its own drain, and the drain is connected to the drain of the PMOS tube MP8;

[0109] The gate of the NMOS tube MN9 is connected to the first end of the bias voltage source VBIAS2;

[0110] The source of the PMOS tube MP1 is connected to the source of the PMOS tube MP2, and the gate is connected to the gate of the PMOS tube MP2;

[0111] The gate of the PMOS tube MP2 is connected to its own drain;

[0112] The source of the PMOS tube MP3 is connected to the source of the PMOS tube MP2, the gate is connected to the gate of the PMOS tube MP4, and the drain is connected to the source of the PMOS tube MP5;

[0113] The source of the PMOS tube MP4 is connected to the source of the PMOS tube MP3, the gate is connected to the drain of the PMOS tube MP5, and the drain is connected to the source of the PMOS tube MP6;

[0114] The gate of the PMOS tube MP5 is connected to the gate of the PMOS tube MP6;

[0115] The source of the PMOS tube MP6 is connected to the source of the PMOS tube MP9, and the gate is connected to its own drain;

[0116] The source of the PMOS tube MP7 is connected to the source of the PMOS tube MP4, and the gate is connected to the gate of the PMOS tube MP1;

[0117] The source of the PMOS tube MP8 is connected to the source of the PMOS tube MP7, and the gate is connected to the gate of the PMOS tube MP7;

[0118] The gate of the PMOS tube MP9 is connected to the second end of the bias voltage source VBIAS1;

[0119] The second end of the resistor R is connected to the source of the NMOS tube MN1;

[0120] A first terminal of the bias voltage source VBIAS1 is connected to the source of the PMOS tube MP8;

[0121] The second terminal of the bias voltage source VBIAS2 is connected to the source of the NMOS transistor MN6.

[0122] Specifically, in the charging current source or the discharging current source, the NMOS tube MN1, the NMOS tube MN2, the PMOS tube MP1, the PMOS tube MP2 and the resistor R constitute a self-biased reference current source; the NMOS tube MN3, the NMOS tube MN4, the PMOS tube MP5 and the PMOS tube MP6 constitute a first current input operational amplifier; the NMOS tube MN7, the NMOS tube MN8, the PMOS tube MP7 and the PMOS tube MP8 constitute a second current input operational amplifier.

[0123] It can be understood that, considering the channel length modulation effect in the actual transistor, the charge and discharge current source uses a current input operational amplifier to realize the clamping function of the current mirror drain voltage, thereby improving the current mirror replication accuracy; wherein, the current mirror includes: a PMOS current mirror composed of a PMOS tube MP3 and a PMOS tube MP4, and an NMOS current mirror composed of an NMOS tube MN5 and an NMOS tube MN6. The shielding effect of the common source and common gate tube is used to isolate the drain voltage of the current mirror, so that the current of the charge and discharge current source remains unchanged during the charging and discharging stages of the detection process, thereby improving the linearity of the detection process, wherein the NMOS tube MN9 and the PMOS tube MP9 are both used as common source and common gate tubes. Specifically, the NMOS tube MN1, the NMOS tube MN2, the PMOS tube MP1, the PMOS tube MP2 and the resistor R constitute a self-biased reference current source, and the current size is changed by adjusting the NMOS tube MN1, the NMOS tube MN2 and the resistor R. NMOS tube MN3, NMOS tube MN4, PMOS tube MP5 and PMOS tube MP6 constitute a first current input operational amplifier, which clamps the drain voltage of PMOS tube MP3 and PMOS tube MP4, reduces the change of charging current Icharge caused by channel length modulation effect, makes Icharge remain unchanged in the charging stage, and improves the accuracy of the change of voltage on TSV with time when charging and discharging TSV. PMOS tube MP9, as a common source and common gate tube, shields the drain voltage of PMOS tube MP4 to reduce the change of drain voltage of PMOS tube MP4 in the charging stage. NMOS tube MN9, as a common source and common gate tube, shields the drain voltage of NMOS tube MN6 to reduce the change of drain voltage of NMOS tube MN6 in the discharge stage.

[0124] Transmission Gate Switch Array

[0125] Transmission gate switch arrays, such as Figure 2 As shown, it may include:

[0126] Transmission gate switch SW1, transmission gate switch SW5 and N combination arrays; wherein,

[0127] A first end of the transmission gate switch SW1 is connected to the output end of the charging current source, and a second end is connected to a first end of the transmission gate switch SW5;

[0128] The second terminal of the transmission gate switch SW5 is grounded;

[0129] For each combination array, the first end of the combination array is connected to the second end of the transmission gate switch SW1, the second end is connected to the input end of the discharge current source, and the third end is connected to the power supply voltage V DD , the fourth end is connected to the TSV to be detected corresponding to the combination array; N represents the total number of TSVs to be detected.

[0130] The structure of each combination array is the same, where the i-th combination array includes:

[0131] Transmission gate switch SW2_i, transmission gate switch SW3_i and transmission gate switch SW4_i; wherein,

[0132] The first end of the transmission gate switch SW2_i serves as the first end of the combination array, and the second end is connected to the first end of the transmission gate switch SW3_i;

[0133] The second end of the transmission gate switch SW3_i serves as the third end of the combination array;

[0134] The first end of the transmission gate switch SW4_i serves as the second end of the combination array, and the second end is connected to the second end of the transmission gate switch SW2_i to serve as the fourth end of the combination array; i represents the serial number of the TSV to be detected currently.

[0135] Specifically, the transmission gate switch array controls the switching of the transmission gate switches inside itself so that the TSV pre-bonding detection circuit is in the charging stage, the resetting stage, the pre-charging stage or the discharging stage in sequence, which may include:

[0136] The transmission gate switch array controls the transmission gate switch SW1 and the transmission gate switch SW2_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW5, the transmission gate switch SW3_i corresponding to the TSV to be detected, and the transmission gate switch SW4_i to be turned off, so that the TSV pre-bonding detection circuit is in the charging stage;

[0137] The transmission gate switch array controls the transmission gate switch SW5 and the transmission gate switch SW2_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW3_i corresponding to the TSV to be detected, and the transmission gate switch SW4_i to be turned off, so that the TSV pre-bonding detection circuit is in a reset stage;

[0138] The transmission gate switch array controls the transmission gate switch SW3_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW5 and the transmission gate switch SW2_i and the transmission gate switch SW4_i corresponding to the TSV to be detected are turned off, so that the TSV pre-bonding detection circuit is in the pre-charging stage;

[0139] The transmission gate switch array controls the transmission gate switch SW4_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW5, the transmission gate switch SW2_i corresponding to the TSV to be detected, and the transmission gate switch SW3_i are turned off, so that the TSV pre-bonding detection circuit is in the discharge stage.

[0140] It can be understood that for the charging stage, the charging path diagram of the TSV pre-bonding detection circuit in the charging stage can be seen in Figure 5 , the transmission gate switch SW1 is turned on to indicate that the charging stage has begun, and the transmission gate switch SW2_i is turned on, indicating that the i-th TSV to be tested is connected to the detection circuit. The control signal charge makes the output of the two-to-one multiplexer MUX the same as the output of the inverter INV. As the charging current source charges the TSV, the voltage of the node B increases with time, causing the inverter INV to output a low level, causing the two-to-one multiplexer to output a low level, causing the AND gate AND to output a constant low level, causing the counter counter to stop counting, and the time required for the charging stage is counted into the memory RAM.

[0141] For the reset phase, see the reset path diagram of the TSV pre-bonding detection circuit in the charging phase. Figure 6 , the transmission gate switch SW1 is turned off, and the transmission gate switch SW5 is turned on, discharging the voltage of node B and the voltage on the i-th TSV to be tested to 0 to avoid affecting the subsequent detection process. The inverter INV outputs a high level, the two-to-one multiplexer MUX outputs a high level, the control signal SW2_i+1 controls the i+1-th TSV to be tested to access the detection circuit, and the counter counter starts counting again.

[0142] For the pre-charging stage, the pre-charging path diagram of the TSV pre-bonding detection circuit in the charging stage is shown in Figure 7 , the transmission gate switch SW3_i is turned on, and the i-th TSV to be tested is precharged to VDD; after the reset stage, the voltage on the TVS has been discharged to 0. In order to detect the discharge stage time later, it is necessary to precharge the TSV before the discharge stage, and charge the voltage of the TSV to VDD to facilitate the subsequent discharge stage test, so as to avoid the situation where there is no power to discharge during the discharge stage.

[0143] For the discharge phase, the discharge path diagram of the TSV pre-bonding detection circuit in the charging phase is shown in Figure 8 , the transmission gate switch SW4_i is turned on. The control signal charge makes the output of the two-to-one multiplexer MUX the same as the output of the buffer buffer. As the discharge current source discharges the TSV, the voltage of the node C decreases over time, causing the buffer buffer to output a low level, causing the two-to-one multiplexer to output a low level, causing the AND gate AND to output a constant low level, causing the counter counter to stop counting, and the time required for the discharge phase is recorded in the memory.

[0144] It should be noted that the transmission gate switch array proposed in the present application controls the switching of its internal transmission gate switches to put the TSV pre-bonding detection circuit in the corresponding working stage, and uses 2+3N transmission gate switches to detect N TSVs to be detected through a combination array with the same number of TSVs to be detected; its connection relationship is not limited to the above situation, for example, the following situation can also exist: only one group of combination arrays is retained to be combined with the original transmission gate switch SW1 and transmission gate switch SW5 to realize the switching of the working stage of the TSV pre-bonding detection circuit; a transmission gate switch is connected in series on each TSV to be tested to form a module to be tested, and each module to be tested is connected in parallel with the combined transmission gate switch to realize the detection of each TSV to be tested. Therefore, the transmission gate switch array proposed in the embodiment of the present invention should have multiple settings.

[0145] Time detection circuit, such as Figure 2 As shown, this may include:

[0146] Buffer buffer, inverter INV, two-to-one multiplexer MUX, AND gate AND, counter counter and memory RAM; among them,

[0147] The input end of the buffer buffer is connected to the first end of the discharge current source, and the output end is connected to the first input end of the two-to-one multiplexer MUX;

[0148] The input end of the inverter INV is connected to the first end of each combination array, and the output end is connected to the second input end of the two-to-one multiplexer MUX;

[0149] The control end of the two-to-one multiplexer MUX is connected to the control signal charge, and the output end is connected to the first input end of the AND gate AND;

[0150] The second input terminal of the AND gate AND is connected to the clock signal CLK, and the output terminal is connected to the first input terminal of the counter counter;

[0151] The second input terminal of the counter counter is connected to the control signal CTRL, and the output terminal is connected to the first input terminal of the memory RAM;

[0152] The second input terminal of the memory RAM is connected to the output signal of the two-to-one multiplexer MUX.

[0153] Specifically, the time detection circuit detects the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage, and determines whether the TSV to be detected has a fault, which may include:

[0154] The time detection circuit detects the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage. When the time required in the charging stage and the time required in the discharging stage remain unchanged, it is determined that the TSV to be detected is normal.

[0155] When the time required for the charging stage and the time required for the discharging stage are reduced in the same proportion, it is determined that the TSV to be detected has an open circuit fault;

[0156] When the time required for the charging stage and the time required for the discharging stage are both reduced, but the reduction ratios are different, it is determined that the TSV to be detected has an open-circuit leakage double fault;

[0157] When the time required for the charging stage increases, it is determined that the TSV to be detected has a leakage fault.

[0158] It can be understood that the time required for the charge and discharge phase remains unchanged means that the time required for the charge and discharge phase of the TSV to be tested is the same as the time required for the charge and discharge phase of the fault-free TSV, and the comparison object of the time required for the charge and discharge phase is the time required for the charge and discharge phase of the fault-free TSV.

[0159] The embodiment of the present invention uses a time detection circuit to obtain the time required for the charging stage and the time required for the discharging stage respectively, thereby realizing the detection of open circuit faults, leakage faults and open circuit leakage dual faults, and avoiding the misjudgment caused by the coexistence of different faults. In the corresponding charging and discharging current source, the current input operational amplifier is used to realize the clamping function of the current mirror drain voltage, improve the current mirror replication accuracy, and the shielding effect of the common source and common gate tube is used to realize the isolation of the current mirror drain voltage, so that the current of the charging and discharging current source in the charging stage and the discharging stage during the detection process remains unchanged, so as to improve the linearity of the detection process.

[0160] It should be noted that in the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0161] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A TSV pre-bonding detection circuit based on current charging and discharging, characterized in that: include: A charging current source, a discharging current source, a transmission gate switch array and a time detection circuit; wherein, The transmission gate switch array is used to control the switching of the transmission gate switches inside the array so that the TSV pre-bonding detection circuit is in the charging stage, the resetting stage, the pre-charging stage or the discharging stage in sequence; The charging current source is used to charge the TSV to be detected connected to the TSV pre-bonding detection circuit during the charging phase; The discharge current source is used to discharge the TSV to be detected connected to the TSV pre-bonding detection circuit during the discharge phase; The time detection circuit is used to detect the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage, and determine whether the TSV to be detected has a fault.

2. A TSV pre-bonding detection circuit based on current charging and discharging according to claim 1, characterized in that: The transmission gate switch array comprises: Transmission gate switch SW1, transmission gate switch SW5 and N combination arrays; wherein, The first end of the transmission gate switch SW1 is connected to the output end of the charging current source, and the second end is connected to the first end of the transmission gate switch SW5; The second end of the transmission gate switch SW5 is grounded; For each combination array, the first end of the combination array is connected to the second end of the transmission gate switch SW1, the second end is connected to the input end of the discharge current source, and the third end is connected to the power supply voltage V DD , the fourth end is connected to the TSV to be detected corresponding to the combination array; N represents the total number of TSVs to be detected.

3. A TSV pre-bonding detection circuit based on current charging and discharging according to claim 2, characterized in that: The structure of each combination array is the same, where the i-th combination array includes: Transmission gate switch SW2_i, transmission gate switch SW3_i and transmission gate switch SW4_i; wherein, The first end of the transmission gate switch SW2_i serves as the first end of the combination array, and the second end is connected to the first end of the transmission gate switch SW3_i; The second end of the transmission gate switch SW3_i serves as the third end of the combination array; The first end of the transmission gate switch SW4_i serves as the second end of the combination array, and the second end is connected to the second end of the transmission gate switch SW2_i to serve as the fourth end of the combination array; i represents the serial number of the TSV to be detected currently.

4. A TSV pre-bonding detection circuit based on current charging and discharging according to claim 3, characterized in that: The transmission gate switch array controls the switching of the transmission gate switches inside the array to put the TSV pre-bonding detection circuit in a charging stage, a reset stage, a pre-charging stage or a discharging stage, including: The transmission gate switch array controls the transmission gate switch SW1 and the transmission gate switch SW2_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW5, the transmission gate switch SW3_i corresponding to the TSV to be detected, and the transmission gate switch SW4_i to be turned off, so that the TSV pre-bonding detection circuit is in a charging stage; The transmission gate switch array controls the transmission gate switch SW5 and the transmission gate switch SW2_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW3_i corresponding to the TSV to be detected, and the transmission gate switch SW4_i to be turned off, so that the TSV pre-bonding detection circuit is in a reset stage; The transmission gate switch array controls the transmission gate switch SW3_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW5 and the transmission gate switches SW2_i and SW4_i corresponding to the TSV to be detected are turned off, so that the TSV pre-bonding detection circuit is in a pre-charging stage; The transmission gate switch array controls the transmission gate switch SW4_i corresponding to the TSV to be detected to be turned on, and the transmission gate switch SW1, the transmission gate switch SW5, the transmission gate switch SW2_i corresponding to the TSV to be detected, and the transmission gate switch SW3_i to be turned off, so that the TSV pre-bonding detection circuit is in the discharge stage.

5. The TSV pre-bonding detection circuit based on current charging and discharging according to claim 1, characterized in that: The electrical model of the TSV to be detected includes: a non-fault TSV equivalent circuit, an open-fault TSV equivalent circuit, a leakage-fault TSV equivalent circuit, or an open-leakage double-fault TSV equivalent circuit; wherein, The fault-free TSV equivalent circuit includes a capacitor C1 connected to ground; The open circuit fault TSV equivalent circuit includes: a grounded capacitor C2 and a grounded capacitor C3, the grounded capacitor C2 and the grounded capacitor C3 are connected at a first normalized position, and an open circuit fault exists at the first normalized position x, x∈[0,1], wherein x=0 indicates that the open circuit fault occurs at the top of the TSV, x=0.5 indicates that the open circuit fault occurs at the midpoint of the TSV, and x=1 indicates that the open circuit fault occurs at the bottom of the TSV, the capacitance value of the capacitor C2 is x times the capacitance value of the capacitor C1, and the capacitance value of the capacitor C3 is (1-x) times the capacitance value of the capacitor C1; when an open circuit fault occurs, the capacitor C2 serves as a load capacitor, and the capacitor C3 does not work; The leakage fault TSV equivalent circuit includes: a grounded resistor R1 and a grounded capacitor C4, the capacitance value of the capacitor C4 is equal to that of the capacitor C1, and the resistor R1 and the capacitor C4 are connected in parallel; The open-circuit leakage double fault TSV equivalent circuit includes: a grounded capacitor C5, a grounded resistor R2 and a grounded capacitor C6, the grounded capacitor C5 and the grounded resistor R2 are connected in parallel, the grounded resistor R2 and the grounded capacitor C6 are connected at a second normalized position, and an open-circuit fault exists at the second normalized position y; y∈[0,1], wherein y=0 indicates that the open-circuit fault occurs at the top of the TSV, y=0.5 indicates that the open-circuit fault occurs at the midpoint of the TSV, and y=1 indicates that the open-circuit fault occurs at the bottom of the TSV, the capacitance value of the capacitor C5 is y times the capacitance value of the capacitor C1, and the capacitance value of the capacitor C6 is (1-y) times the capacitance value of the capacitor C1; when an open-circuit leakage double fault occurs, the capacitor C5 acts as a load capacitor, and the capacitor C6 does not work.

6. The TSV pre-bonding detection circuit based on current charging and discharging according to claim 1, characterized in that: Any of the charging current source and the discharging current source includes: NMOS transistor MN1, NMOS transistor MN2, NMOS transistor MN3, NMOS transistor MN4, NMOS transistor MN5, NMOS transistor MN6, NMOS transistor MN7, NMOS transistor MN8, NMOS transistor MN9, PMOS transistor MP1, PMOS transistor MP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PMOS transistor MP6, PMOS transistor MP7, PMOS transistor MP8, PMOS transistor MP9, resistor R, bias voltage source VBIAS1 and bias voltage source VBIAS2; wherein, The source of the NMOS tube MN1 is grounded, the gate is connected to the gate of the NMOS tube MN2, and the drain is connected to the drain of the PMOS tube MP1; The source of the NMOS tube MN2 is connected to the first end of the resistor R, the gate is connected to the drain of the NMOS tube MN1, and the drain is connected to the drain of the PMOS tube MP2; The source of the NMOS tube MN3 is connected to the source of the NMOS tube MN1, the gate is connected to the gate of the NMOS tube MN4, and the drain is connected to the drain of the PMOS tube MP5; The source of the NMOS tube MN4 is connected to the source of the NMOS tube MN3, the gate is connected to the gate of the NMOS tube MN1, and the drain is connected to the drain of the PMOS tube MP6; The source of the NMOS tube MN5 is connected to the source of the NMOS tube MN4, the gate is connected to the gate of the NMOS tube MN6, and the drain is connected to the source of the NMOS tube MN7; The source of the NMOS tube MN6 is connected to the source of the NMOS tube MN5, the gate is connected to the drain of the PMOS tube MP7, and the drain is connected to the source of the NMOS tube MN8; The gate of the NMOS tube MN7 is connected to the gate of the NMOS tube MN8, and the drain is connected to the drain of the PMOS tube MP7; The source of the NMOS tube MN8 is connected to the source of the NMOS tube MN9, the gate is connected to its own drain, and the drain is connected to the drain of the PMOS tube MP8; The gate of the NMOS tube MN9 is connected to the first end of the bias voltage source VBIAS2; The source of the PMOS tube MP1 is connected to the source of the PMOS tube MP2, and the gate is connected to the gate of the PMOS tube MP2; The gate of the PMOS tube MP2 is connected to its own drain; The source of the PMOS tube MP3 is connected to the source of the PMOS tube MP2, the gate is connected to the gate of the PMOS tube MP4, and the drain is connected to the source of the PMOS tube MP5; The source of the PMOS tube MP4 is connected to the source of the PMOS tube MP3, the gate is connected to the drain of the PMOS tube MP5, and the drain is connected to the source of the PMOS tube MP6; The gate of the PMOS tube MP5 is connected to the gate of the PMOS tube MP6; The source of the PMOS tube MP6 is connected to the source of the PMOS tube MP9, and the gate is connected to its own drain; The source of the PMOS tube MP7 is connected to the source of the PMOS tube MP4, and the gate is connected to the gate of the PMOS tube MP1; The source of the PMOS tube MP8 is connected to the source of the PMOS tube MP7, and the gate is connected to the gate of the PMOS tube MP7; The gate of the PMOS tube MP9 is connected to the second end of the bias voltage source VBIAS1; The second end of the resistor R is connected to the source of the NMOS transistor MN1; A first terminal of the bias voltage source VBIAS1 is connected to the source of the PMOS tube MP8; The second end of the bias voltage source VBIAS2 is connected to the source of the NMOS transistor MN6.

7. The TSV pre-bonding detection circuit based on current charging and discharging according to claim 6, characterized in that: In the charging current source or the discharging current source, the NMOS tube MN1, the NMOS tube MN2, the PMOS tube MP1, the PMOS tube MP2 and the resistor R constitute a self-biased reference current source; the NMOS tube MN3, the NMOS tube MN4, the PMOS tube MP5 and the PMOS tube MP6 constitute a first current input operational amplifier; the NMOS tube MN7, the NMOS tube MN8, the PMOS tube MP7 and the PMOS tube MP8 constitute a second current input operational amplifier.

8. The TSV pre-bonding detection circuit based on current charging and discharging according to claim 2, characterized in that: The time detection circuit comprises: Buffer buffer, inverter INV, two-to-one multiplexer MUX, AND gate AND, counter counter and memory RAM; among them, The input end of the buffer is connected to the first end of the discharge current source, and the output end is connected to the first input end of the two-to-one multiplexer MUX; The input end of the inverter INV is connected to the first end of each combination array, and the output end is connected to the second input end of the two-to-one multiple selector MUX; The control end of the two-to-one multiple selector MUX receives the control signal charge, and the output end is connected to the first input end of the AND gate AND; The second input terminal of the AND gate AND is connected to the clock signal CLK, and the output terminal is connected to the first input terminal of the counter counter; The second input terminal of the counter counter is connected to the control signal CTRL, and the output terminal is connected to the first input terminal of the memory RAM; The second input terminal of the memory RAM is connected to the output signal of the two-to-one multiplexer MUX.

9. The TSV pre-bonding detection circuit based on current charging and discharging according to claim 1, characterized in that: The time detection circuit detects the TSV to be detected according to the time required for the charging stage and the time required for the discharging stage, and determines whether the TSV to be detected has a fault, including: The time detection circuit detects the TSV to be detected according to the time required in the charging stage and the time required in the discharging stage, and when the time required in the charging stage and the time required in the discharging stage remain unchanged, it is determined that the TSV to be detected is normal; When the time required for the charging stage and the time required for the discharging stage are reduced in the same proportion, it is determined that the TSV to be detected has an open circuit fault; When the time required for the charging stage and the time required for the discharging stage are both reduced, but the reduction ratios are different, it is determined that the TSV to be detected has an open-circuit leakage double fault; When the time required for the charging stage increases, it is determined that the TSV to be detected has a leakage fault.

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