A hybrid packaging structure, method and testing method and system of optoelectronic chip

Abstract

The present invention relates to the field of semiconductor packaging technology, and specifically to a hybrid packaging structure, method, and testing method and system of an optoelectronic chip. The packaging structure includes: a first substrate; a strengthening connection layer is arranged on the upper surface of the first substrate; the strengthening connection layer includes: a silicon adapter plate, a first and a second strengthening layer are arranged on the silicon adapter plate, and an electronic chip is arranged on the upper surface of the second strengthening layer; a third strengthening layer, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer, the surface area exposed by the second strengthening layer, and the side of the electronic chip; a photonic chip is arranged on the upper surface of the third strengthening layer at a position corresponding to the first strengthening layer. The hybrid packaging solution based on the strengthening connection layer proposed in the present invention can be applied to wafer-level batch processing, which is conducive to achieving compatibility with advanced packaging processes of electronic chips and large-scale mass production.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a hybrid packaging structure and method of an optoelectronic chip, and a testing method and system thereof. Background Art

[0002] With the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has grown explosively. Lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging.

[0003] In order to meet the demand for Internet traffic, the node bandwidth of the data center needs to reach 10Tb / s. In order to slow down the trend of increasing energy consumption in the data center, we must find ways to reduce the power consumption of systems and devices. Driven by ultra-high data capacity, the traditional electrical chip process is gradually approaching the 10nm size, and the CMOS process is about to encounter physical limits. Since light has the performance of low signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS, the industry generally believes that silicon photonic chips organically combine mature microelectronics and optoelectronics technologies, which can not only reduce chip size, reduce cost and power consumption, but also improve reliability, and are expected to become a high-speed information engine that "goes beyond Moore's Law".

[0004] Therefore, it is necessary to introduce silicon photonics technology. However, most of the traditional hybrid packaging structures of optoelectronic chips are based on 2.5D packaging technology to hybridize multiple small-scale optical chips with multiple electrical chips. Although the computing power can be improved by integrating multiple small-scale optical chips and connecting multiple electrical chips to each optical chip, it is difficult to achieve the application level of computing array scale with the mask template under the conventional wafer area due to the limitation of the structural size of the traditional small-scale optical chip itself. In other words, the processing of conventional hybrid packaging structures is difficult.

[0005] In addition, in order to improve the application level of optical chips, the applicant has proposed a high-dimensional matrix optical chip, such as CN116736933A and CN117234276A, whose photon computing unit size is less than 100μm. However, there is currently no hybrid packaging structure and process for high-dimensional matrix optical chips and electrical chips, and the silicon interposer (or middle layer) is prone to warping due to the dense routing in 2.5D packaging technology. Therefore, when large-scale optical chips and electrical chips are mixed and packaged, they face great challenges in packaging structure design. In this regard, the applicant has also filed a patent application CN117913084A, which discloses a hybrid packaging structure and packaging method for optoelectronic chips based on 2.5D packaging technology. It completes the hybrid packaging of optoelectronic chips by arranging optical chips and electrical chips on the upper surface of the silicon adapter board.

[0006] However, as the functional integration of photonic chips and electronic chips becomes higher and higher, the conductive interfaces on them become more and more dense, and the photonic chips also have external structures such as optical ports, which puts extremely high demands on the packaging process of optical and electronic chips. In other words, the current hybrid packaging of optical and electronic chips is difficult to achieve large-scale batch processing, and the production cost is very high.

[0007] Therefore, there is an urgent need for an optoelectronic hybrid packaging technology that can be suitable for large-scale batch production. Summary of the invention

[0008] The object of the present invention is to provide a hybrid packaging structure, method and testing method and system of an optoelectronic chip, which partially solve or alleviate the above-mentioned deficiencies in the prior art and can apply the packaging structure to wafer-level batch processing technology.

[0009] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0010] The first aspect of the present invention is to provide a hybrid packaging structure of an optoelectronic chip, comprising:

[0011] a first substrate;

[0012] A strengthening connection layer is disposed on the upper surface of the first substrate; wherein the strengthening connection layer comprises:

[0013] A silicon adapter board, wherein a first connection area and a second connection area are provided on the upper surface of the silicon adapter board, and the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column provided on the silicon adapter board; a first strengthening layer is provided on the first connection area, the first strengthening layer is filled with a first strengthening material, and a plurality of first connection positions are provided on the first strengthening layer corresponding to the plurality of the conductive pins; a second strengthening layer is provided on the second connection area, the second strengthening layer is filled with a second strengthening material, and a plurality of second connection positions are provided on the second strengthening layer corresponding to the plurality of the conductive pins;

[0014] At least one first-class electronic chip is disposed on the upper surface of the second strengthening layer, and a conductive interface in the first-class electronic chip is connected to the silicon adapter plate through the second connection position;

[0015] a third strengthening layer, wherein the third strengthening layer can at least cover the surface area exposed by the first strengthening layer, the surface area exposed by the second strengthening layer, and the side surface of the first type of electronic chip, and the third strengthening layer is filled with a third strengthening material; and a plurality of second conductive pillars are arranged on the third strengthening layer corresponding to the first connection position;

[0016] At least one photonic chip is provided with a plurality of conductive interfaces, and the conductive interfaces are correspondingly connected to the second conductive pillars.

[0017] In some embodiments, it also includes: a fourth reinforcement layer arranged between the lower surface of the photonic chip and the upper surface of the third reinforcement layer, the fourth reinforcement layer is filled with a fourth reinforcement material, and a plurality of third connection positions are arranged on the fourth reinforcement layer, and the third connection positions are used to connect the conductive interface of the photonic chip and the second conductive column.

[0018] In some embodiments, the thickness of the first strengthening layer is less than 100 um.

[0019] In some embodiments, the thickness of the second strengthening layer is less than 100 um.

[0020] In some embodiments, the thickness of the third strengthening layer is 300-2000 um.

[0021] In some embodiments, it also includes: a second substrate arranged on the upper surface of the first substrate; at least one type II electronic chip is arranged on the second substrate, and the conductive interface of the type II electronic chip is correspondingly connected to the conductive pins of the second substrate.

[0022] In some embodiments, the type of electronic chip includes one or more of the following types: wDAC chip, xADC chip, xDAC chip, ASCI chip, I / O chip.

[0023] In some embodiments, the second type of electronic chip includes one or more of the following types: wDAC chip, xADC chip, xDAC chip.

[0024] The present invention further provides a packaging method for the hybrid packaging structure of the optoelectronic chip that can be applied to any one of the embodiments of the present invention, comprising the steps of:

[0025] S101, providing a silicon wafer, wherein a plurality of silicon transfer plates are spaced apart from each other on the silicon wafer;

[0026] S102, respectively setting a plurality of first connection positions and a plurality of second connection positions on the plurality of silicon adapter plates;

[0027] S103, filling a first strengthening material around the plurality of first connection sites to form a first strengthening layer, and filling a second strengthening material around the plurality of second connection sites to form a second strengthening layer; and arranging a type of electronic chip on an upper surface of the second strengthening layer;

[0028] S104, disposing a second conductive column on the upper surface of the first strengthening layer;

[0029] S105, filling a third strengthening material around the first strengthening layer, the second strengthening layer and the first type of electronic chip to form a third strengthening layer, wherein the third strengthening layer covers the second conductive pillar, and the top of the second channel is exposed through the upper surface of the third strengthening layer, corresponding to the prepared multiple strengthening connection layers;

[0030] S106, cutting the plurality of strengthening connection layers to obtain a single strengthening connection layer.

[0031] In some embodiments, before S106, the step of:

[0032] At least one photonic chip is arranged on the upper surface of the third strengthening layer, and a conductive interface of the photonic chip is connected to the second conductive column.

[0033] Another aspect of the present invention further provides a testing method for a hybrid packaging structure, comprising the steps of:

[0034] S200, providing a strengthening connection layer, the strengthening connection layer comprising: a silicon adapter board, a first connection area and a second connection area are arranged on the upper surface of the silicon adapter board, and the first connection area and the second connection area are respectively arranged with a plurality of conductive pins, and the conductive pins are led out through a first conductive column arranged on the silicon adapter board; a first strengthening layer is arranged on the first connection area, and a plurality of first connection positions are arranged on the first strengthening layer corresponding to the plurality of conductive pins; a second strengthening layer is arranged on the second connection area, and a plurality of second connection positions are arranged on the second strengthening layer corresponding to the plurality of conductive pins; at least one first-class electronic chip is arranged on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter board through the second connection position; a third strengthening layer, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer, the surface area exposed by the second strengthening layer and the side of the first-class electronic chip, and a plurality of second conductive columns are arranged on the third strengthening layer corresponding to the first connection position;

[0035] S201, obtaining a first target bending line segment L of the strengthening connection layer, where the first target bending line segment L is used to reflect the bending deformation degree of the strengthening connection layer on a plane;

[0036] S202, extracting at least one first line segment L1 and at least one second line segment L2 from the first target curved line segment L;

[0037] S203, determining whether the first target curved line segment L satisfies a first strengthening rule; wherein the first strengthening rule requires that the curvature of the first line segment L1 is less than a set first curvature threshold, and the curvature of the second line segment L2 is less than a set second curvature threshold;

[0038] When the result of S203 is yes, it is considered that the strengthened connection layer meets the first strengthening condition.

[0039] In some embodiments, the steps include:

[0040] S204, disposing a photonic chip on the upper surface of the strengthening connection layer to form a corresponding multi-layer structure;

[0041] S205, obtaining a second target bending line segment L0 of the multi-layer structure;

[0042] S206, extracting at least one third line segment L3 and at least one fourth line segment L4 from the second target curved line segment L0;

[0043] S207, determining whether the second target curved line segment L0 satisfies a second strengthening rule; wherein the second strengthening rule requires that the curvature of the third line segment L3 is less than a set third curvature threshold, and the curvature of the fourth line segment L4 is less than a set fourth curvature threshold;

[0044] When the result of S207 is yes, it is considered that the multilayer structure meets the second strengthening condition.

[0045] The present invention also provides a corresponding test system for a hybrid packaging structure, wherein the packaging structure comprises: a strengthening connection layer, wherein the strengthening connection layer comprises: a silicon adapter, wherein a first connection area and a second connection area are provided on the upper surface of the silicon adapter, and the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column provided on the silicon adapter; a first strengthening layer is provided on the first connection area, and a plurality of first connection positions are provided on the first strengthening layer corresponding to the plurality of conductive pins; a second strengthening layer is provided on the second connection area, and a plurality of second connection positions are provided on the second strengthening layer corresponding to the plurality of conductive pins; at least one first-class electronic chip is provided on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter through the second connection position; a third strengthening layer, wherein the third strengthening layer can at least cover the surface area exposed by the first strengthening layer, the surface area exposed by the second strengthening layer and the side of the first-class electronic chip, and a plurality of second conductive columns are provided on the third strengthening layer corresponding to the first connection position; correspondingly, the system comprises:

[0046] A first acquisition module, used for acquiring a first target bending line segment of the strengthening connection layer, where the first target bending line segment is used for reflecting the bending deformation degree of the strengthening connection layer on a plane;

[0047] A second acquisition module, used to extract at least one first line segment and at least one second line segment from the first target curved line segment;

[0048] A judgment module, used to judge whether the first target curved line segment satisfies a first strengthening rule; wherein the first strengthening rule requires that the curvature of the first line segment is less than a set first curvature threshold, and the curvature of the second line segment is less than a set second curvature threshold;

[0049] When the result of the judgment is yes, it is considered that the strengthened connection layer meets the first strengthening condition.

[0050] Beneficial technical effects:

[0051] The present invention provides a technical solution for hybrid packaging of optical and electrical chips based on a multi-structure layered composite strengthening connection layer. Specifically, the present invention uses multiple layers of strengthening layers to connect to each other, and allows the optical chip and the electrical chip to be installed in staggered layers between different strengthening layers. Therefore, on the one hand, the distribution of multiple strengthening layers and chips reduces or alleviates the problem of uneven stress (or warping problem) that may be caused by the strengthening step, ensuring that the original structure of the silicon wafer or chip will not be damaged while the strength is greatly improved. On the other hand, the layered processing method in this hybrid packaging can also reduce the processing difficulty, and to a certain extent avoid mutual interference between the optical and electrical chips during the packaging process.

[0052] Furthermore, the multi-layer strengthening layers in the present invention cooperate with local reinforcement (such as local setting of the first and second strengthening layers) and overall reinforcement (such as overall wrapping of the third strengthening layer) to further alleviate the deformation problem in the strengthening step (i.e., reduce the deformation speed during the processing, or reduce the deformation amount per unit time), thereby ensuring the effectiveness of strength improvement (i.e., controlling the generation of defects) on the basis of improving the strength of the strengthening connection layer as much as possible.

[0053] Furthermore, for the reinforcing connection layer of the multi-layer staggered design, the present invention also proposes a step-by-step hybrid packaging method. Specifically, the present invention performs collaborative grading treatment on the staggered distribution arrangement of the layers and the step-by-step stacking of the optoelectronic chips, so that the packaging structure can be applied to wafer-level batch processing, and at the same time, the stress unevenness problem caused by the strengthening step can be alleviated through collaborative grading treatment. In other words, the wafer-level processing technology provided by the present invention can achieve a certain balance between the strength improvement and the stress unevenness problem caused by the strength change, so as to enhance the reliability and accuracy of the batch processing flow, thereby reducing the preparation cost.

[0054] Furthermore, corresponding to the above-mentioned multi-layer staggered design of the strengthening connection layer, the present invention also provides a testing method for the packaging structure applied to the wafer-level batch packaging process, which helps to comprehensively evaluate the overall deformation degree of multiple local areas of the strengthening connection layer (especially the core local areas covered by the photonic chip and the electronic chip), as well as the difference in the deformation degree, and thus effectively measure the control effect of the graded strengthening step on the warping problem.

[0055] Furthermore, the testing method of the present invention can also comprehensively strengthen the difference in bending deformation of the connection layer before and after the photonic chip is packaged, so as to further evaluate the control effect of the graded strengthening steps on the warping problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0057] Figure 1 is a schematic structural diagram of a hybrid packaging structure in an exemplary embodiment of the present invention;

[0058] Figure 2 is a structural schematic diagram of a hybrid packaging structure in another exemplary embodiment of the present invention;

[0059] Figure 3 is a schematic structural diagram of a strengthening connection layer in an exemplary embodiment of the present invention;

[0060] Figure 4 is a schematic top view of a hybrid packaging structure in an exemplary embodiment of the present invention;

[0061] Figure 5 is a schematic diagram of a wafer structure in an exemplary embodiment of the present invention;

[0062] Figure 6 is a schematic diagram of the warping of the strengthening connection layer in an exemplary embodiment of the present invention;

[0063] Figure 7 is a schematic diagram of the connection between the strengthening connection layer and the photonic chip in an exemplary embodiment of the present invention;

[0064] Figure 8 A schematic diagram of the process steps of a packaging method in an exemplary embodiment of the present invention;

[0065] Fig. 9 The figure is a schematic diagram of the process steps of a method for testing a packaging structure in an exemplary embodiment of the present invention.

[0066] Summary of reference numerals and symbols: first substrate 10, strengthening connection layer 20, silicon adapter plate 21, first conductive column 211, first strengthening layer 22, first connection position 221, second strengthening layer 23, second connection position 231, third strengthening layer 25, second conductive column 251, fourth strengthening layer 26, third connection position 261, type I electronic chip 30, photonic chip 40, second substrate 50, type II electronic chip 60, wafer 01, first connection area 21a, second connection area 21b. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0068] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0069] In this document, the terms "upper", "lower", "inner", "outer", "front", "rear", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0070] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0071] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0072] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0073] As used in this specification, the term "about" typically means + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0074] In this specification, some embodiments may be disclosed in a format of being in a range. It should be understood that this description of "being in a range" is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent numerical values ​​within this range. For example, the description of the range 1-6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within this range, such as 1, 2, 3, 4, 5 and 6. Regardless of the breadth of the range, the above rules apply.

[0075] As used herein, a "layer" refers to a portion of a material that includes an area having a certain thickness. A layer may extend over the entire upper or lower structure, or may have an extent that is less than the extent of the upper or lower structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, and its thickness may be less than the thickness of the continuous structure. For example, a layer may be located between the upper or lower surface of a continuous structure, or between any pair of horizontal planes therebetween. A layer may have one or more layers horizontally, vertically, and / or above, over, and / or below it. A layer may include multiple layers.

[0076] Herein, "strengthening material" refers to a material that can be bonded to the surface to be packaged and has a certain strength after curing. For example, the first strengthening material refers to a material that can be bonded to the surface of the silicon adapter and can be cured on the surface of the silicon adapter.

[0077] In this article, "wafer" refers to the silicon chip (or silicon wafer) used to make silicon semiconductor circuits. "Chip" can be a small piece cut from a wafer, also called "Die". In some embodiments, a "Die" can form a silicon transfer board.

[0078] See also Figure 1-Figure 9 As shown, the present invention provides a packaging technology for hybrid packaging of optoelectronic chips achieved by a reinforcing connection layer based on a multi-layer staggered design, and the packaging technology can be applied to wafer-level batch processing.

[0079] Embodiment 1

[0080] The present invention proposes a packaging method of a hybrid packaging structure of an optical and electrical chip (also collectively referred to as a chip herein), and to facilitate explanation of the packaging method, a preferred packaging structure of the present invention is first introduced below:

[0081] See also Figure 1 As shown, the hybrid packaging structure of the optoelectronic chip (or referred to as: semiconductor device) includes:

[0082] A first substrate 10;

[0083] A strengthening connection layer 20 is disposed on the upper surface of the first substrate 10; this embodiment adopts a strengthening connection layer formed by a multi-layer structure with a staggered arrangement, wherein the strengthening connection layer 20 includes:

[0084] A silicon adapter board 21, wherein a first connection area and a second connection area are provided on the upper surface of the silicon adapter board 21, and the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column 211 provided on the silicon adapter board 21; a first strengthening layer 22 is provided on the first connection area, the first strengthening layer is filled with a first strengthening material, and a plurality of first connection positions 221 are provided on the first strengthening layer 22 corresponding to the plurality of the conductive pins; a second strengthening layer 23 is provided on the second connection area, the second strengthening layer is filled with a second strengthening material, and a plurality of second connection positions 231 are provided on the second strengthening layer 23 corresponding to the plurality of the conductive pins;

[0085] At least one first-class electronic chip 30 is disposed on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter plate 21 through the second connection position 231;

[0086] A third strengthening layer 25, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer 22, the surface area exposed by the second strengthening layer and the side of the first type of electronic chip, the third strengthening layer is filled with a third strengthening material; and a plurality of second conductive pillars 251 are arranged on the third strengthening layer corresponding to the first connection positions 221;

[0087] At least one photonic chip 40 is provided with a plurality of conductive interfaces, and the conductive interfaces are correspondingly connected to the second conductive pillars. The conductive interfaces, the second conductive pillars 251, the conductive pins, and the first conductive pillars 211 are sequentially connected to form a conductive path to achieve communication connection between the photonic chip and the silicon adapter board.

[0088] In some embodiments, the first conductive pillar is a through silicon via (TSV, also called a through silicon via).

[0089] Correspondingly, see Figure 8 As shown, the hybrid packaging method proposed by the present invention includes the following steps:

[0090] S101, providing a silicon wafer 01 (or wafer), wherein a plurality of silicon transfer plates are spaced apart from each other on the silicon wafer;

[0091] See also Figure 5 As shown, Figure 5 The top view of the wafer 01 is shown. Generally, the wafer 01 can be divided into a plurality of crystal grains, and various circuit processes can be performed on the crystal grains to form semiconductor devices. For example, a conductive circuit (such as a conductive bump) can be prepared on the crystal grains to stack one or more chips thereon, thereby preparing a semiconductor device with complete functions.

[0092] In some embodiments, a separation region with a first interval is formed between each of the crystal grains. For example, the separation region may be a groove structure, and one of the crystal grains may serve as a silicon transfer plate 21 in a semiconductor device.

[0093] S102, respectively setting a plurality of first connection positions and a plurality of second connection positions on the plurality of silicon transfer boards.

[0094] For example, in some embodiments, a first connection area 21a and a second connection area 21b may be defined on the silicon transfer board 21 (see Figure 5For example, the first connection area and the second connection area can be set according to the specifications (such as size) of the selected electronic chip and the photonic chip. Preferably, the area of ​​the connection area is equal to or larger than the overlapping area between the chip and the silicon connection plate.

[0095] Furthermore, a plurality of first connection sites and second connection sites are respectively arranged on the first connection area 21a and the second connection area 21b, wherein the connection sites are conductive structures capable of conducting electricity, such as conductive bumps.

[0096] S103, filling a first strengthening material around the plurality of first connection sites to form a first strengthening layer, and filling a second strengthening material around the plurality of second connection sites to form a second strengthening layer; and arranging a type of electronic chip on an upper surface of the second strengthening layer;

[0097] For example, in some embodiments, a first strengthening material is filled around the first connection site to form a first strengthening layer, and a second strengthening material is filled around the second connection site to form a second strengthening layer. In some embodiments, the first and second strengthening layers can be prepared and formed simultaneously, or, in other embodiments, the first and second strengthening layers can also be prepared in any order.

[0098] Furthermore, a type of electronic chip may be mounted on the second strengthening layer. Herein, the process of providing the strengthening layer is also referred to as a strengthening step.

[0099] S104, disposing a second conductive column 251 on the upper surface of the first strengthening layer 22;

[0100] For example, a plurality of second conductive pillars 251 are respectively arranged on the first strengthening layer corresponding to the plurality of conductive pins; wherein the second conductive pillars 251 are used to be electrically connected to a subsequent photonic chip.

[0101] S105, filling a third strengthening material around the first strengthening layer 22, the second strengthening layer and the first type of electronic chip to form a third strengthening layer 25, and the third strengthening layer covers the second conductive column, and the top of the second conductive column is exposed through the upper surface of the third strengthening layer, corresponding to the prepared multiple strengthening connection layers.

[0102] For example, the process is: filling a third strengthening material on the silicon adapter board; wherein the third strengthening material will cover and fill the exposed surface of the silicon adapter board, and fill the gaps between different layers or structures on the silicon adapter board, so that the third strengthening material can cover and wrap the silicon adapter board to form a third strengthening layer, and the upper surface of the third strengthening layer can expose the top of the second conductive column 251 to reserve an interface for the installation of the photonic chip 40; thereby, multiple strengthening connection layers are formed on the wafer.

[0103] S106, cutting the plurality of strengthening connection layers to obtain a single strengthening connection layer. Specifically, cutting the wafer to obtain a single strengthening connection layer.

[0104] Preferably, in some embodiments, the third reinforcement material may also at least partially fill the groove structure between the grains.

[0105] Preferably, in some embodiments, the third reinforcement material may also simultaneously cover the lower surface of the silicon transition.

[0106] In some embodiments, before S106 , the method further includes the step of disposing at least one photonic chip on the upper surface of the third strengthening layer, wherein the conductive interface of the photonic chip is connected to the second conductive column.

[0107] Preferably, in some embodiments, the photonic chip can be arranged at the wafer level before cutting, such as welding the photonic chip to the surface of the strengthening connection layer through a second conductive column; thus, after the hybrid packaging of optical and electrical chips is completed at the wafer level, the overall cutting is performed.

[0108] Alternatively, in some other embodiments, packaging of a type of electronic chip may be performed only at the wafer level, and packaging of the photonic chip may be performed later.

[0109] Among them, the staggered-layer hybrid packaging technology based on multiple strengthening layers proposed in the present invention helps to realize a specific sequence of packaging processes for electronic chips and photonic chips, thereby reducing the packaging difficulty and further improving the packaging yield on the basis of ensuring the reliability of the packaging structure.

[0110] Specifically, in this embodiment, the electronic chip and the photonic chip are preferably subjected to specific large-scale coverage packaging and small-scale coverage packaging in order. Among them, the large-scale coverage packaging means that the lower surface and the side of the electronic chip are evenly covered by the third strengthening material, and the small-scale coverage packaging means that only part of the lower surface of the photonic chip is covered with the third strengthening material, and the photosensitive area of ​​the photonic chip is set on the part of its lower surface protruding from the third strengthening layer. Therefore, this large-scale and small-scale specific hybrid packaging process can ensure that the final packaged product has sufficient strength while keeping the external area of ​​the core (such as the photosensitive area) from damage / damage / dirt during the multi-step packaging process.

[0111] Moreover, from another perspective, this specific order packaging solution is also conducive to saving the overall packaging cost of the packaged product. Preferably, by packaging the electronic chip and the packaging results (such as evaluating the bending degree of the strengthening connection layer without the photonic chip), the bad package bodies after the electronic chip packaging can be promptly eliminated in the early stage of packaging, so as to reduce the number of bad packages in the overall packaging process. Therefore, this specific order packaging method can improve the utilization rate of the more expensive photonic chips and reduce the cost of use.

[0112] Preferably, see Figure 3 As shown, in some embodiments, before the photonic chip is packaged on the strengthening connection layer 20 , a fourth strengthening layer 26 may be further disposed thereon to indirectly complete the installation of the photonic chip through the fourth strengthening layer 26 .

[0113] In some embodiments, the first strengthening layer and the second strengthening layer may not be connected to each other. That is, in this embodiment, a plurality of small-scale strengthening layers may be preferentially disposed locally on the wafer, whereby such dispersed local strengthening layer arrangement can enhance the strength and rigidity of the wafer during processing, save consumables, and control the problem of uneven stress during the filling process of the strengthening material.

[0114] Of course, in other embodiments, in order to simplify the packaging process, the first strengthening layer and the second strengthening layer may also be in a connected state, for example, they may be integrally formed.

[0115] It should be noted that in existing packaging solutions, in order to ensure the working stability of semiconductor devices formed by packaging, such as reducing problems such as fragmentation and collision cracks, it is often necessary to individually package the semiconductor devices one by one (specifically, the wafer needs to be cut to set up the circuit structure on a separate silicon adapter board). However, this independent packaging will not only increase the difficulty of the packaging process, but also increase the packaging cost.

[0116] In stark contrast to the single flat-layer connection solution in the prior art (such as the hybrid packaging structure disclosed in patent application CN117913084A, in which both the optical chip and the electrical chip are directly connected to the middle layer through an adhesive reinforcement layer), the present invention provides a wafer-level processing technology based on a staggered distribution of a multi-layer structure. Specifically, the present invention performs collaborative grading treatment on the staggered distribution of the layers and the step-by-step stacking of the optoelectronic chips, so that the packaging structure can be applied to wafer-level batch processing, and at the same time, the stress unevenness problem caused by the strengthening step can be alleviated through collaborative grading treatment. In other words, the wafer-level processing technology provided by the present invention can achieve a certain balance between strength improvement and the stress unevenness problem caused by strength changes, so as to enhance the reliability and accuracy of the batch processing flow, thereby reducing the preparation cost.

[0117] Embodiment 2

[0118] See also Figure 1-Figure 4 As shown, the present invention provides a hybrid packaging structure that can be applied to wafer-level batch stacking.

[0119] See also Figure 1 As shown, a hybrid packaging structure of an optoelectronic chip includes: a first substrate 10;

[0120] A strengthening connection layer 20 is disposed on the upper surface of the first substrate 10; wherein the strengthening connection layer 20 comprises:

[0121] A silicon adapter board 21, wherein a first connection area and a second connection area are provided on the upper surface of the silicon adapter board 21, and the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column 211 provided on the silicon adapter board 21; a first strengthening layer 22 is provided on the first connection area, the first strengthening layer is filled with a first strengthening material, and a plurality of first connection positions 221 are provided on the first strengthening layer 22 corresponding to the plurality of the conductive pins; a second strengthening layer 23 is provided on the second connection area, the second strengthening layer is filled with a second strengthening material, and a plurality of second connection positions 231 are provided on the second strengthening layer 23 corresponding to the plurality of the conductive pins;

[0122] At least one first-class electronic chip 30 is disposed on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter plate 21 through the second connection position 231;

[0123] A third strengthening layer 25, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer 22, the surface area exposed by the second strengthening layer and the side of the first type of electronic chip, the third strengthening layer is filled with a third strengthening material; and a plurality of second conductive pillars 251 are arranged on the third strengthening layer corresponding to the first connection positions 221;

[0124] At least one photonic chip 40 is provided with a plurality of conductive interfaces, and the conductive interfaces are correspondingly connected to the second conductive pillars.

[0125] In this embodiment, a strengthening connection layer based on the coordination of multiple strengthening layers is actually proposed, and the strengthening connection layer is obtained based on the cross-staggered arrangement design between multiple structural layers such as multiple strengthening layers, photonic chips and electronic chips. On the one hand, this specially arranged strengthening connection layer can form a stable and reliable connection relationship between the photonic chip and the first substrate to improve the overall strength and stability of the hybrid packaging structure; on the other hand, the distribution setting of multiple strengthening layers can alleviate the stress change problem caused by the strengthening process (such as alleviating the stress change trend caused by each layer and reducing the defect impact that may be caused by a single strengthening layer), especially the cooperation between the second strengthening layer and a type of electronic chip, and the cooperation between the first strengthening layer, the third strengthening layer and the photonic chip can cooperate with each other, so as to facilitate the stable packaging of the electronic chip and the photonic chip at the wafer level.

[0126] Preferably, in some embodiments, the third strengthening material will also cover the lower surface of the silicon adapter plate, and correspondingly the third strengthening layer will wrap and cover the silicon adapter plate, the first strengthening layer, and the second strengthening layer, exposing only the upper surface of a type of electronic chip.

[0127] Alternatively, in some embodiments, the third reinforcement material will fully cover the multi-layer structure, such as the silicon interposer, the first reinforcement layer, the second reinforcement layer, and a type of electronic chip.

[0128] Preferably, in some embodiments, the thickness of the first strengthening layer is less than 100 um.

[0129] Preferably, in some embodiments, the thickness of the second strengthening layer is less than 100 um.

[0130] Preferably, in some embodiments, the thickness of the third strengthening layer is about 300-2000 um.

[0131] In some embodiments, it also includes: a fourth strengthening layer 26 arranged between the lower surface of the photonic chip and the upper surface of the third strengthening layer 25, the fourth strengthening layer 26 is filled with a fourth strengthening material, and a plurality of third connection positions 261 are arranged on the fourth strengthening layer 26, and the third connection positions 261 are used to connect the conductive interface of the photonic chip 40 and the second conductive column 251.

[0132] In this embodiment, the first strengthening layer 22 , the second conductive pillar 251 and the third strengthening material filled therearound form a TMV structure (or referred to as a TMV chip).

[0133] In some embodiments, the connection sites are conductive structures such as conductive bumps fabricated by soldering.

[0134] In some embodiments, it also includes: a second substrate 50 arranged on the upper surface of the first substrate 10; at least one type II electronic chip 60 is arranged on the second substrate 50, and the conductive interface of the type II electronic chip 60 is correspondingly connected to the conductive pins of the second substrate 50.

[0135] In some embodiments, the type of electronic chip includes one or more of the following types: wDAC chip, xADC chip, xDAC chip, ASCI chip, I / O chip.

[0136] Preferably, a type of electronic chip is an electronic chip that can perform functions such as analog-to-digital conversion and digital-to-analog conversion, for example, customized ASIC chips, high-speed communication IP and control I / O chips and other chips required for related calculations.

[0137] In some embodiments, the second type of electronic chips include one or more of the following types: wDAC chip, xADC chip, xDAC chip, data storage chip, control chip.

[0138] Preferably, the chip side surface 401 of the photonic chip 40 extends out of the strengthening connection layer, and correspondingly, the extended portion is suspended relative to the strengthening connection layer.

[0139] Preferably, a photosensitive area is provided on the side of the chip in the photonic chip, and the optical fiber array is horizontally coupled to the photosensitive area (not shown in the figure). Correspondingly, the side of the chip extends out of the middle layer so that the optical fiber array is suspended.

[0140] In some embodiments, the first substrate is an ABF substrate. The full name of the ABF substrate is Ajinomoto Build-up Film substrate, which is a high-performance packaging substrate material mainly used for integrated circuit (IC) packaging. It is composed of multiple layers of interconnection and insulation materials, and can provide electrical connection, mechanical support, protection and thermal conduction channels for the chip.

[0141] In some embodiments, the second substrate is a coreless packaging substrate.

[0142] In some embodiments, see Figure 4 As shown, a plurality of second-class electronic chips may be disposed on the strengthening connection layer, and for example, these second-class electronic chips may all be wDAC chips.

[0143] Embodiment 3

[0144] Corresponding to the above-mentioned multi-layer staggered strengthening connection layer, the present invention also provides a testing method for a packaging structure applied to a wafer-level batch packaging process, the method can test the strengthening quality of the strengthening connection layer, and the strengthening connection layer 20 in this embodiment preferably includes: a silicon adapter plate 21, a first connection area and a second connection area are arranged on the upper surface of the silicon adapter plate 21, and the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column 211 arranged on the silicon adapter plate 21; a first strengthening layer 22 is arranged on the first connection area, and a plurality of conductive pins are arranged on the first strengthening layer 22 corresponding to the plurality of conductive pins. A plurality of first connection positions 221 are arranged; a second strengthening layer 23 is arranged on the second connection area, and a plurality of second connection positions 231 are arranged on the second strengthening layer 23 corresponding to the plurality of the conductive pins; at least one first-class electronic chip 30 is arranged on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter board 21 through the second connection position 231; a third strengthening layer 25, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer 22, the surface area exposed by the second strengthening layer and the side of the first-class electronic chip, and a plurality of second conductive pillars 251 are arranged on the third strengthening layer corresponding to the first connection position 221. Correspondingly, see Fig. 9 As shown, the method comprises the steps of:

[0145] S200, providing a reinforced connection layer;

[0146] S201, obtaining a first target bending line segment L of the strengthening connection layer 20, where the first target bending line segment L is used to reflect the bending deformation degree of the strengthening connection layer 20 on a plane;

[0147] For example, in some embodiments, the first target bending line segment L is a curve segment formed by the cross-section of the upper surface of the strengthening connection layer 20. For example, in some embodiments, the first target bending line segment L can be a curve segment formed by the cross-section of the lower surface of the strengthening connection layer 20.

[0148] S202, extracting at least one first line segment L1 and at least one second line segment L2 from the first target curved line segment L;

[0149] For example, in some embodiments, see Figure 6 As shown, the outer surface (such as the upper surface or the lower surface) of the reinforcing connection layer is divided into a center surface and an edge surface in sequence along the direction from the center to the outside. Correspondingly, the first line segment can be a curved line segment corresponding to the center surface, and the second line segment can be a curved line segment corresponding to the edge surface.

[0150] For another example, in some embodiments, the first line segment can cover the area where a type of electronic chip 30 is located, and the second line segment can cover part of the first strengthening layer and the spacing area between the first strengthening layer and the type of electronic chip 30. That is, the selection of the first line segment and the second line segment can at least partially cover the core processing area.

[0151] S203, determining whether the first target curved line segment L satisfies a first enhancement rule; wherein the first enhancement rule requires that the curvature of the first line segment L1 is less than a set first curvature threshold, and the curvature of the second line segment L2 is less than a set second curvature threshold.

[0152] In this embodiment, curvature refers to the degree to which a layer (such as a reinforcing connection layer) deforms in shape when subjected to force (for example, different points in the layer sense different amounts of stress due to uneven shrinkage / deformation).

[0153] In some embodiments, the strength of the strengthening connection layer can be measured by laser interferometry. The object to be measured (such as the strengthening connection layer) is placed on a laser interferometer measurement platform, and the height change of the surface of the object to be measured is measured using a laser interferometer. The warping (or curvature) of the object to be measured is calculated based on the change in the interference fringes.

[0154] Alternatively, in some other embodiments, an image measuring instrument may be used to measure the warpage of the reinforcing connection layer at at least one section. The image measuring instrument is a high-precision measuring device that can obtain the warpage of the object by photographing and analyzing the surface of the object to be measured.

[0155] When the result of S203 is yes, it is considered that the strengthening connection layer 20 meets the first strengthening condition.

[0156] In some embodiments, if the result of S203 is yes, it is considered that the strengthening step preliminarily meets the strengthening requirements, that is, it is considered that the connection strengthening layer can be applied to the subsequent packaging process. In other words, when the curved line segment L meets the preset strengthening rule, it is considered that the curved line segment meets the strengthening condition, that is, it can be preliminarily considered that the strengthening connection layer meets the subsequent packaging requirements, and the photonic chip can be further installed thereon and the segmentation process can be performed.

[0157] Preferably, in some embodiments, the curvature of the first target curvature line segment L should also be less than a preset curvature threshold (such as the fifth curvature threshold). That is, this embodiment preferably performs a comprehensive analysis on the overall curvature and the curvature of the key local area, so as to ensure that the strengthening connection layer has a relatively limited curvature and a relatively uniform stress distribution, so as to meet the subsequent production, processing and use requirements.

[0158] Furthermore, in some embodiments, the first strengthening rule further requires that the difference between the curvature of the first line segment and the curvature of the second line segment (or referred to as the third curvature difference) is less than a set difference threshold (or referred to as the second difference threshold), that is, the stress uniformity of the strengthened connection layer is further evaluated.

[0159] In some embodiments, the method further comprises the steps of:

[0160] S204, disposing a photonic chip 40 on the upper surface of the strengthening connection layer 20 to form a multi-layer structure;

[0161] S205, obtaining a second target bending line segment L of the multilayer structure 0 ;

[0162] S206, from the second target curved line segment L 0 extracting at least one third line segment L3 and at least one fourth line segment L4;

[0163] For example, in some embodiments, see Figure 7 As shown, the photonic chip 40 and the strengthening connection layer 20 can be regarded as an integral multi-layer structure, and the warping degree of the multi-layer structure on the horizontal plane is obtained to obtain the second target bending line segment.

[0164] S207, determining the second target curved line segment L 0 Whether the second strengthening rule is satisfied; wherein the second strengthening rule requires that the curvature of the third line segment L3 is less than a set third curvature threshold, and the curvature of the fourth line segment L4 is less than a set fourth curvature threshold;

[0165] When the result of S207 is yes, it is considered that the multilayer structure meets the second strengthening condition.

[0166] In some embodiments, if the result of S207 is yes, it is considered that the connection strength between the strengthening connection layer and the photonic chip meets the requirement.

[0167] Preferably, in some embodiments, the first line segment and the third line segment correspond to the same or similar regions on the strengthening connection layer, and the second line segment and the fourth line segment correspond to the same or similar regions on the strengthening connection layer.

[0168] Preferably, in some embodiments, the first line segment at least covers a portion of the region where the photonic chip is connected to the strengthening connection layer.

[0169] In this embodiment, after the photonic chip is installed on the strengthening connection layer to form a multi-layer structure, the curvature of the core local area of ​​the multi-layer structure is preferably further collaboratively evaluated to verify the strengthening effect of the strengthening step.

[0170] Furthermore, in some embodiments, the testing method may further include the steps of:

[0171] calculating a first bending difference between the first line segment and the third line segment, and calculating a second bending difference between the second line segment and the fourth line segment;

[0172] Correspondingly, the second strengthening rule also requires that when the first bending difference and the second bending difference are both less than a set first difference threshold, it is considered that the second strengthening condition is met.

[0173] In this embodiment, the uniformity of the deformation degree of the strengthening connection layer during the packaging process is determined by comparing the overall bending strength and the degree of change of the strengthening connection layer before and after the photonic chip is installed. That is, in this embodiment, when it is determined that the multi-layer structure meets the second strengthening condition, it means that the multiple strengthening layers in the multi-layer structure have shown good uniformity during the manufacturing and subsequent packaging processes, that is, the warping degree is relatively controllable and meets the packaging requirements.

[0174] Preferably, the curve data of the strengthening connection layer is collected at the wafer level, that is, the curvature of one or more curved line segments is collected before cutting the multiple strengthening connection layers in the wafer.

[0175] In particular, in some embodiments, for semiconductor devices with extremely high performance requirements, that is, when the requirements for the enhanced performance of the enhanced connection layer are very high, at least one first line segment and at least one second line segment preferably cover the entire first target bending curve.

[0176] In some embodiments, the first reinforcing material or the second reinforcing material may be underfilled, and in particular, in some embodiments, underfills such as 3730 or 8410 may be selected.

[0177] In some embodiments, the third reinforcing material may be a molding material, specifically, in some embodiments, a molding material such as R4604 / R4212 may be selected.

[0178] Of course, it is understandable that the types of different strengthening materials in the present invention can be adaptively adjusted according to different packaging standards, or the specifications and types of the selected chips, so the present invention is not limited to this.

[0179] Embodiment 4

[0180] The present invention also provides a test system for a hybrid packaging structure, the packaging structure comprising: a strengthening connection layer 20, the strengthening connection layer 20 comprising: a silicon adapter plate 21, a first connection area and a second connection area are arranged on the upper surface of the silicon adapter plate 21, and the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column 211 arranged on the silicon adapter plate 21; a first strengthening layer 22 is arranged on the first connection area, and a plurality of first connection positions 221 are arranged on the first strengthening layer 22 corresponding to the plurality of conductive pins; a second strengthening layer 22 is arranged on the second connection area A strengthening layer 23 is provided, and a plurality of second connection positions 231 are provided on the second strengthening layer 23 corresponding to the plurality of the conductive pins; at least one first-class electronic chip 30 is provided on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter board 21 through the second connection position 231; a third strengthening layer 25, the third strengthening layer can at least cover the surface area exposed by the first strengthening layer 22, the surface area exposed by the second strengthening layer and the side of the first-class electronic chip, and a plurality of second conductive pillars 251 are provided on the third strengthening layer corresponding to the first connection position 221; correspondingly, the system includes:

[0181] A first acquisition module, used for acquiring a first target bending line segment L of the strengthening connection layer 20, wherein the first target bending line segment L is used for reflecting the bending deformation degree of the strengthening connection layer 20 on a plane;

[0182] A second acquisition module, configured to extract at least one first line segment L1 and at least one second line segment L2 from the first target curved line segment L;

[0183] A judgment module, used to judge whether the first target curved line segment L satisfies a first strengthening rule; wherein the first strengthening rule requires that the curvature of the first line segment L1 is less than a set first curvature threshold, and the curvature of the second line segment L2 is less than a set second curvature threshold;

[0184] When the result of the judgment is yes, it is considered that the strengthening connection layer 20 meets the first strengthening condition.

[0185] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0186] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0187] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A packaging method for a hybrid packaging structure of an optoelectronic chip, characterized in that: The hybrid packaging structure of the optoelectronic chip includes: A first substrate (10); A strengthening connection layer (20) is provided on the upper surface of the first substrate (10); wherein the strengthening connection layer (20) comprises a silicon adapter plate (21); a first connection area and a second connection area are provided on the upper surface of the silicon adapter plate (21); the first connection area and the second connection area are respectively provided with a plurality of conductive pins, and the conductive pins are led out through a first conductive column (211) provided on the silicon adapter plate (21); a first strengthening layer (22) is provided on the first connection area, the first strengthening layer (22) is filled with a first strengthening material, and a plurality of first connection positions (221) are provided on the first strengthening layer (22) corresponding to the plurality of conductive pins; a second strengthening layer (23) is provided on the second connection area, the second strengthening layer is filled with a second strengthening material, and a plurality of second connection positions (231) are provided on the second strengthening layer (23) corresponding to the plurality of conductive pins; At least one first-class electronic chip (30) is disposed on the upper surface of the second strengthening layer (23), and a conductive interface in the first-class electronic chip is connected to the silicon adapter plate (21) via the second connection position (231); a third strengthening layer (25), the third strengthening layer (25) being capable of at least covering the surface area exposed by the first strengthening layer (22), the surface area exposed by the second strengthening layer (23), and the side surface of the first type of electronic chip, the third strengthening layer being filled with a third strengthening material; and a plurality of second conductive pillars (251) being arranged on the third strengthening layer corresponding to the first connection position (221); At least one photonic chip (40), wherein a plurality of conductive interfaces are provided on the photonic chip (40), and the conductive interfaces are correspondingly connected to the second conductive pillars (251); The packaging method comprises the steps of: S101, providing a silicon wafer (01), wherein a plurality of silicon transfer plates are spaced apart from each other on the silicon wafer; S102, respectively setting a plurality of first connection positions and a plurality of second connection positions on the plurality of silicon adapter plates; S103, filling a first strengthening material around the plurality of first connection sites to form a first strengthening layer, and filling a second strengthening material around the plurality of second connection sites to form a second strengthening layer; and arranging a type of electronic chip on an upper surface of the second strengthening layer; S104, disposing a second conductive column (251) on the upper surface of the first strengthening layer (22); S105, filling a third strengthening material around the first strengthening layer (22), the second strengthening layer and the first type of electronic chip to form a third strengthening layer (25), wherein the third strengthening layer covers the second conductive column, and the top of the second conductive column is exposed through the upper surface of the third strengthening layer, corresponding to the prepared multiple strengthening connection layers; S106, cutting the plurality of strengthening connection layers to obtain a single strengthening connection layer.

2. The packaging method according to claim 1, characterized in that: Before S106, the step further includes: At least one photonic chip is arranged on the upper surface of the third strengthening layer, and a conductive interface of the photonic chip is connected to the second conductive column.

3. The packaging method according to claim 1, characterized in that: The hybrid packaging structure further comprises: a fourth strengthening layer (26) arranged between the lower surface of the photonic chip (40) and the upper surface of the third strengthening layer (25), the fourth strengthening layer (26) being filled with a fourth strengthening material, and a plurality of third connection positions (261) being arranged on the fourth strengthening layer (26), the third connection positions (261) being used to connect the conductive interface of the photonic chip (40) and the second conductive pillar (251).

4. The packaging method according to claim 1, characterized in that: The thickness of the first strengthening layer is less than 100 um; and / or the thickness of the second strengthening layer is less than 100 um; and / or the thickness of the third strengthening layer is 300-2000 um.

5. The packaging method according to claim 1, characterized in that: The hybrid packaging structure further comprises: a second substrate (50) arranged on the upper surface of the first substrate (10); At least one second-type electronic chip (60) is arranged on the second substrate (50), and the conductive interface of the second-type electronic chip (60) is correspondingly connected to the conductive pins of the second substrate (50).

6. The packaging method according to claim 5, characterized in that: The first type of electronic chips includes one or more of the following types: wDAC chip, xADC chip, xDAC chip, ASCI chip, I / O chip; and / or, the second type of electronic chips includes one or more of the following types: wDAC chip, xADC chip, xDAC chip.

7. A testing method applied to a hybrid packaging structure, characterized in that: Includes steps: S200, providing a strengthening connection layer (20), the strengthening connection layer (20) comprising a silicon adapter plate (21), a first connection area and a second connection area being arranged on an upper surface of the silicon adapter plate (21), the first connection area and the second connection area being respectively provided with a plurality of conductive pins, and the conductive pins being led out through a first conductive column (211) arranged on the silicon adapter plate (21); a first strengthening layer (22) being arranged on the first connection area, and a plurality of first connection positions (221) being arranged on the first strengthening layer (22) corresponding to the plurality of conductive pins; a second strengthening layer (23) being arranged on the second connection area, and the first strengthening layer (23) being provided with a plurality of first connection positions (221) corresponding to the plurality of conductive pins. A plurality of second connection positions (231) are arranged on the second strengthening layer (23) corresponding to the plurality of conductive pins; at least one first-class electronic chip (30) is arranged on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter plate (21) via the second connection position (231); a third strengthening layer (25), the third strengthening layer at least capable of covering the surface area exposed by the first strengthening layer (22), the surface area exposed by the second strengthening layer and the side surface of the first-class electronic chip, and a plurality of second conductive pillars (251) are arranged on the third strengthening layer corresponding to the first connection position (221); S201, obtaining a first target bending line segment L of the strengthening connection layer (20), wherein the first target bending line segment L is used to reflect the degree of bending deformation of the strengthening connection layer (20) on a plane; S202, extracting at least one first line segment L1 and at least one second line segment L2 from the first target curved line segment L; S203, determining whether the first target curved line segment L satisfies a first strengthening rule; wherein the first strengthening rule requires that the curvature of the first line segment L1 is less than a set first curvature threshold, and the curvature of the second line segment L2 is less than a set second curvature threshold; When the result of S203 is yes, it is considered that the strengthened connection layer (20) meets the first strengthening condition.

8. The testing method according to claim 7, characterized in that: Includes steps: S204, arranging a photonic chip (40) on the upper surface of the strengthening connection layer (20) to form a corresponding multi-layer structure; S205, obtaining a second target bending line segment L0 of the multi-layer structure; S206, extracting at least one third line segment L3 and at least one fourth line segment L4 from the second target curved line segment L0; S207, determining whether the second target curved line segment L0 satisfies a second strengthening rule; wherein the second strengthening rule requires that the curvature of the third line segment L3 is less than a set third curvature threshold, and the curvature of the fourth line segment L4 is less than a set fourth curvature threshold; When the result of S207 is yes, it is considered that the multilayer structure meets the second strengthening condition.

9. A test system for a hybrid packaging structure, characterized in that: The packaging structure comprises: a strengthening connection layer (20), the strengthening connection layer (20) comprising a silicon adapter plate (21), a first connection area and a second connection area being arranged on the upper surface of the silicon adapter plate (21), and the first connection area and the second connection area being respectively provided with a plurality of conductive pins, and the conductive pins being led out through a first conductive column (211) arranged on the silicon adapter plate (21); a first strengthening layer (22) being arranged on the first connection area, and a plurality of first connection positions (221) being arranged on the first strengthening layer (22) corresponding to the plurality of conductive pins; a second strengthening layer (23) being arranged on the second connection area, and the second strengthening layer (23) is provided with a plurality of second connection positions (231) corresponding to the plurality of conductive pins; at least one first-class electronic chip (30) is provided on the upper surface of the second strengthening layer, and the conductive interface in the first-class electronic chip is connected to the silicon adapter plate (21) through the second connection position (231); a third strengthening layer (25), the third strengthening layer at least capable of covering the surface area exposed by the first strengthening layer (22), the surface area exposed by the second strengthening layer and the side surface of the first-class electronic chip, and a plurality of second conductive pillars (251) are provided on the third strengthening layer corresponding to the first connection position (221); correspondingly, the system comprises: A first acquisition module, used to acquire a first target bending line segment L of the strengthening connection layer (20), wherein the first target bending line segment L is used to reflect the degree of bending deformation of the strengthening connection layer (20) on a plane; A second acquisition module, configured to extract at least one first line segment L1 and at least one second line segment L2 from the first target curved line segment L; A judgment module, used to judge whether the first target curved line segment L satisfies a first strengthening rule; wherein the first strengthening rule requires that the curvature of the first line segment L1 is less than a set first curvature threshold, and the curvature of the second line segment L2 is less than a set second curvature threshold; When the result of the judgment is yes, it is considered that the strengthened connection layer (20) meets the first strengthening condition.

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