Silicon optical chip, optical fiber array for chip-level test and test method

Abstract

The invention relates to a silicon optical chip which is provided with a first input waveguide, a plurality of first output waveguides and a Loop loop on the same side. The Loop loop has a second input waveguide and a second output waveguide, the second input waveguide dividing 90% of the light into the MPD and dividing 10% of the light into the second output waveguide. An optical fiber array for chip-level testing is provided with a first polarization-maintaining optical fiber, a third polarization-maintaining optical fiber, a multimode optical fiber and four second polarization-maintaining optical fibers, the first polarization-maintaining optical fiber corresponds to a first input waveguide in a silicon optical chip, the third polarization-maintaining optical fiber corresponds to a second input waveguide in the silicon optical chip, and the multimode optical fiber corresponds to a second output waveguide in the silicon optical chip. And the four second polarization maintaining optical fibers are respectively corresponding to four first output waveguides in the silicon optical chip. The method has the advantages that the chip testing speed can be greatly increased, and the chip cost cannot be additionally increased due to the fact that the chip area and the MPD number are not increased.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon photonics chips, and particularly relates to a silicon photonics chip, an optical fiber array for chip-level testing, and a testing method. Background Art

[0002] The structure of a traditional DR4 silicon photonics chip is as follows: It has an input waveguide and four output waveguides on the same side. The input waveguide is coupled to the input of a first 1×2 coupler. The two outputs of the first 1×2 coupler are each coupled to the input of a second 1×2 coupler. The two outputs of each second 1×2 coupler are each coupled to an output waveguide through an MZM modulator. In order to couple the lens, a part of the light from the input waveguide is directed to the MPD to monitor the optical power coupled into the input waveguide, and the other light is divided equally among the four output waveguides. Since the DR4 silicon photonics chip has a large insertion loss, in order to ensure sufficient optical power enters the MZM modulator, usually about 2% of the light is directed to the MPD, and the other about 98% of the light is divided equally among multiple output waveguides. In addition, the waveguide width size on the silicon photonics chip is usually 6μm ± 0.5μm.

[0003] Due to the large insertion loss of the DR4 silicon photonics chip itself and the unstable chip manufacturing process, in order to ensure the production yield of the optical module, it is usually necessary to test 100% of the chips for optical performance parameters such as optical insertion loss. During the testing process, the most commonly used supporting device is the optical fiber array. When the optical fiber array is coupled to the DR4 silicon photonics chip, as Figure 1 shown, each polarization-maintaining fiber in the optical fiber array needs to be aligned with the input waveguide and the output waveguide in the DR4 silicon photonics chip at the same time. The polarization-maintaining fiber commonly used in the optical fiber array is a single-mode fiber, and the mode spot of the single-mode fiber is about 9μm, while the waveguide width size on the silicon photonics chip is usually 6μm ± 0.5μm. Moreover, since only about 2% of the light from the input waveguide enters the MPD, the MPD photocurrent is very small, making it difficult to find the light during coupling, resulting in difficulty in coupling and aligning the polarization-maintaining fiber with the input waveguide and the output waveguide during testing, and causing low testing efficiency. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a silicon photonics chip, an optical fiber array for chip-level testing, and a testing method to overcome the above deficiencies in the prior art.

[0005] The technical solution of the present invention to solve the above technical problems is as follows: A silicon photonics chip has a first input waveguide, multiple first output waveguides, and a Loop loop on the same side. The first input waveguide splits part of the light to the MPD, and the other light is split to the multiple first output waveguides in a geometric progression. The Loop loop has a second input waveguide and a second output waveguide. The second input waveguide splits 90% of the light to the MPD and 10% of the light to the second output waveguide. The widths of the first input waveguide, the first output waveguides, the second input waveguide, and the second output waveguide are all 6μm ± 0.5μm.

[0006] The beneficial effects of the present invention are as follows: A Loop loop is designed in the silicon photonics chip. The Loop loop has a second input waveguide and a second output waveguide. The second input waveguide splits 90% of the light to the MPD. When an external light source provides high optical power to the second input waveguide in the silicon photonics chip through the polarization-maintaining fiber in the fiber array, since the MPD can monitor the photocurrent and the photocurrent is very large, it is easy to find the light through coupling. And since only a single waveguide needs to be aligned, the difficulty is reduced. After aligning the first input waveguide with the polarization-maintaining fiber for incoming light test in the fiber array, it is also easy to align the polarization-maintaining fiber for outgoing light test in the fiber array with the second output waveguide. Thus, the present invention can greatly accelerate the chip test speed, and since the chip area and the number of MPDs are not increased, there is no additional increase in chip cost.

[0007] On the basis of the above technical solution, the present invention can be further improved as follows.

[0008] Furthermore, the first input waveguide, the first output waveguides, the second input waveguide, and the second output waveguide are all inclined and parallel to each other.

[0009] Furthermore, the number of the first output waveguides is four.

[0010] Furthermore, the first input waveguide is coupled to the input of a first 1×2 coupler. The two outputs of the first 1×2 coupler are respectively coupled to the inputs of a second 1×2 coupler. The two outputs of each second 1×2 coupler are respectively coupled to a first output waveguide through an MZM modulator.

[0011] Based on the above technical solution, the present invention further provides an optical fiber array for chip-level testing, which is used to test the above-mentioned silicon optical chip. It includes a first polarization-maintaining fiber, a third polarization-maintaining fiber, a multimode fiber, and four second polarization-maintaining fibers. The size of the third polarization-maintaining fiber is 3μm ± 0.3μm, the size of the multimode fiber is 50μm ± 1μm. The position of the first polarization-maintaining fiber corresponds to the first input waveguide in the silicon optical chip, the position of the third polarization-maintaining fiber corresponds to the second input waveguide in the silicon optical chip, the position of the multimode fiber corresponds to the second output waveguide in the silicon optical chip, and the positions of the four second polarization-maintaining fibers respectively correspond to the four first output waveguides in the silicon optical chip.

[0012] The further beneficial effects of adopting the above are as follows: When an external light source provides a large optical power to the second input waveguide in the silicon optical chip through the third polarization-maintaining fiber in the optical fiber array, since the optical fiber array uses the third polarization-maintaining fiber to couple with the second input waveguide in the silicon optical chip, and 90% of the light in the second input waveguide is directed to the MPD, the MPD photocurrent will be very large, making it easy to find light when the optical fiber array is coupled with the silicon optical chip. The optical fiber array uses a multimode fiber to couple with the second output waveguide in the silicon optical chip. When measuring with an optical power meter connected externally to the multimode fiber, due to the large mode field diameter of the 50μm ± 1μm multimode fiber, even if the optical fiber array and the silicon optical chip are not aligned and the deviation is more than 10μm, the optical power can still be effectively measured. In the existing solution, the mode field diameter of the single-mode fiber is about 9μm. If the deviation is more than 10μm, the optical power cannot be measured. Moreover, when the optical fiber array is coupled with the silicon optical chip, it is very easy for the optical fiber array to have a very small angle with the silicon optical chip. After the angle appears, the distances between the first polarization-maintaining fiber and the second polarization-maintaining fiber and the first input waveguide and the first output waveguide in the silicon optical chip will be relatively small. In this way, the first polarization-maintaining fiber and the second polarization-maintaining fiber cannot be aligned with the first input waveguide and the first output waveguide of the silicon optical chip at the same time. Since the chip performance can only be effectively measured when they are aligned at the same time, the test will fail when they cannot be aligned.

[0013] Furthermore, the inclination angle of the end face of its optical port is the same as the inclination angle of the first input waveguide, the first output waveguide, the second input waveguide, or the second output waveguide.

[0014] Based on the above technical solution, the present invention further provides a method for testing a silicon optical chip, which uses the above-mentioned optical fiber array for chip-level testing to test the silicon optical chip, including the following steps: S1. Connect a light source externally to the third polarization-maintaining fiber, and the light source provides a large optical power, and connect an optical power meter externally to the multimode fiber; S2. Turn on the light source connected to the third polarization-maintaining fiber and the optical power meter connected to the multimode fiber. Align the third polarization-maintaining fiber in the fiber array with the second input waveguide in the silicon photonics chip in an active coupling manner, and align the multimode fiber in the fiber array with the second output waveguide in the silicon photonics chip in an active coupling manner, waiting for the measured photocurrent value by the MPD to be the largest and the measured optical power by the optical power meter to be the largest. S3. Keep the positions of the silicon photonics chip and the fiber array unchanged. Turn off the light source connected to the third polarization-maintaining fiber, and connect a light source to the first polarization-maintaining fiber, and connect an optical power meter to each of the second polarization-maintaining fibers. S4. Turn on the light source connected to the first polarization-maintaining fiber and the optical power meter connected to the second polarization-maintaining fiber. Fine-tune the angle of the fiber array so that the fiber array is parallel to the silicon photonics chip, and in the active coupling mode, align it to the maximum measured optical power by the optical power meter, then the performance of the silicon photonics chip can be tested.

[0015] The further beneficial effects of the above are: the chip performance can be accurately tested, and the test is convenient and fast.

[0016] Further, the high optical power provided by the light source connected to the third polarization-maintaining fiber > 20 dBm. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a coupling test structure diagram of a fiber array and a silicon photonics chip in the prior art; Figure 2 It is a structure diagram of the silicon photonics chip in the present invention; Figure 3 It is a structure diagram of the fiber array in the present invention; Figure 4 It is a coupling test structure diagram of the fiber array and the silicon photonics chip in the present invention.

[0018] In the drawings, the list of components represented by each reference numeral is as follows: 1. Silicon photonics chip, 110. First input waveguide, 120. First output waveguide, 130. Second input waveguide, 140. Second output waveguide, 150. MPD, 160. First 1×2 coupler, 170. Second 1×2 coupler, 180. MZM modulator, 2. Fiber array, 210. First polarization-maintaining fiber, 220. Third polarization-maintaining fiber, 230. Multimode fiber, 240. Second polarization-maintaining fiber. DETAILED DESCRIPTION OF THE INVENTION

[0019] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0020] Example 1 As Figure 2As shown in the figure, a silicon photonics chip has a first input waveguide 110, multiple first output waveguides 120, and a Loop loop on the same side. The first input waveguide 110 splits part of the light towards the MPD 150, and the other light is split towards the multiple first output waveguides 120 in a geometric progression, that is, it still remains consistent with the prior art. For example, if the first input waveguide 110 splits approximately 2% of the light towards the MPD 150, then the other approximately 98% of the light is split towards the multiple first output waveguides 120 in a geometric progression. Of course, this is just an exemplary example, and other ratios are not excluded in actual applications. The Loop loop has a second input waveguide 130 and a second output waveguide 140, that is, a first input waveguide 110, a second input waveguide 130, a second output waveguide 140, and multiple first output waveguides 120 are on the same side. The second input waveguide 130 splits 90% of the light towards the MPD 150 and 10% of the light towards the second output waveguide 140. The width dimension of the first input waveguide 110 is 6μm ± 0.5μm, the width dimension of the first output waveguide 120 is 6μm ± 0.5μm, that is, it still remains consistent with the prior art. The width dimension of the second input waveguide 130 is 6μm ± 0.5μm, and the width dimension of the second output waveguide 140 is 6μm ± 0.5μm.

[0021] A Loop loop is designed in the silicon photonics chip. The Loop loop has a second input waveguide 130 and a second output waveguide 140, and the second input waveguide 130 splits 90% of the light towards the MPD 150. When an external light source provides a large optical power to the second input waveguide 130 in the silicon photonics chip 1 through the polarization-maintaining fiber in the fiber array 2, since the MPD 150 can monitor the photocurrent and the photocurrent is very large, it is easy to find the coupling light, and since only a single waveguide needs to be aligned, the difficulty is reduced. After aligning the first input waveguide 110 with the polarization-maintaining fiber for light input testing in the fiber array 2, it is also easy to align the polarization-maintaining fiber for light output testing in the fiber array 2 with the second output waveguide 140, thereby enabling the present invention to significantly accelerate the chip testing speed, and since the chip area and the number of MPD 150s do not increase, no additional chip cost will be incurred.

[0022] Embodiment 2 As Figure 2 shown, this embodiment is a further improvement based on Embodiment 1, specifically as follows: The first input waveguide 110, the first output waveguide 120, the second input waveguide 130, and the second output waveguide 140 are all inclined and parallel to each other. For example, a common inclination is 8°. Of course, this is just an exemplary example, and other angles are not excluded in actual applications.

[0023] Embodiment 3 AsFigure 2 As shown in the figure, this embodiment is a further improvement based on Embodiment 1 or 2, specifically as follows: The number of the first output waveguides 120 is four. At this time, the silicon photonics chip is a DR4 silicon photonics chip. The first input waveguide 110 is coupled to the input of a first 1×2 coupler 160. The two outputs of the first 1×2 coupler 160 are respectively coupled to the inputs of a second 1×2 coupler 170, that is, there are two second 1×2 couplers 170. The two outputs of each second 1×2 coupler 170 are respectively coupled to a first output waveguide 120 through an MZM modulator 180, that is, there are four MZM modulators 180. The first 1×2 coupler 160 and the second 1×2 coupler 170 both split light in equal proportion, so that after the light output from the first output waveguide 120 is partially split to the MPD 150, the other light can be split to the four first output waveguides 120 in an equal ratio form.

[0024] Embodiment 4 As Figure 3 shown, an optical fiber array for chip-level testing is used to test the silicon photonics chip 1 in any one of Embodiments 1 to 3. It includes: a substrate, a cover plate, and a first polarization-maintaining optical fiber 210, a third polarization-maintaining optical fiber 220, a multimode optical fiber 230, and four second polarization-maintaining optical fibers 240 clamped by the substrate and the cover plate. The size of the third polarization-maintaining optical fiber 220 is 3μm ± 0.3μm, and the size of the multimode optical fiber 230 is 50μm ± 1μm. The position of the first polarization-maintaining optical fiber 210 corresponds to the first input waveguide 110 in the silicon photonics chip 1. The positions of the four second polarization-maintaining optical fibers 240 respectively correspond to the four first output waveguides 120 in the silicon photonics chip 1, that is, this part of the content is still consistent with the prior art; the position of the third polarization-maintaining optical fiber 220 corresponds to the second input waveguide 130 in the silicon photonics chip 1, and the position of the multimode optical fiber 230 corresponds to the second output waveguide 140 in the silicon photonics chip 1. The first polarization-maintaining optical fiber 210, the third polarization-maintaining optical fiber 220, the multimode optical fiber 230, and the four second polarization-maintaining optical fibers 240 are parallel to each other; When an external light source provides high optical power to the second input waveguide 130 in the silicon photonics chip 1 through the third polarization-maintaining optical fiber 220 in the optical fiber array 2, since the optical fiber array 2 uses the third polarization-maintaining optical fiber 220 to couple to the second input waveguide 130 in the silicon photonics chip 1, and 90% of the light in the second input waveguide 130 is split to the MPD 150, the photocurrent of the MPD 150 will be very large, so that it is easy to find light by coupling the optical fiber array 2 and the silicon photonics chip 1; The fiber optic array 2 uses multimode optical fibers 230 to couple with the second output waveguide 140 in the silicon photonics chip 1. When measuring with an optical power meter connected externally to the multimode optical fiber 230, since the mode field of the 50μm ± 1μm multimode optical fiber 230 is large, even if the fiber optic array 2 is not aligned with the silicon photonics chip 1 and the deviation is more than 10μm, the optical power can still be effectively measured. In the existing solution, the mode field of the single-mode optical fiber is about 9μm. If the deviation is more than 10μm, the optical power cannot be measured. Moreover, when the fiber optic array 2 is coupled with the silicon photonics chip 1, it is very easy for the fiber optic array 2 to have a very small angle with the silicon photonics chip 1. After the angle appears, the distances between the first polarization-maintaining optical fiber 210 and the second polarization-maintaining optical fiber 240 relative to the first input waveguide 110 and the first output waveguide 120 in the silicon photonics chip 1 will be smaller (for example, the channel pitch of the fiber optic array 2 is 250μm, with 4 channels, and the total pitch between channel 1 and channel 4 is 750μm. When the fiber optic array 2 is flush-coupled with the silicon photonics chip 1, the pitch between channel 1 and channel 4 is 750μm. When the fiber optic array 2 is not flush with the silicon photonics chip 1, that is, an angle appears, such as an angle of 60° (in actual situations, it is generally less than 6°, and 60° is just taken as an example for calculation). Then, cos60° = 0.5, 0.5×750 = 375μm. At this time, the pitch between channel 1 and channel 4 of the fiber optic array 2 relative to the silicon photonics chip 1 is only 375μm. After channel 1 is aligned with a first output waveguide 120 of the silicon photonics chip 1, channel 4 cannot be aligned with the other first output waveguide 120 of the silicon photonics chip 1). In this way, the first polarization-maintaining optical fiber 210 and the second polarization-maintaining optical fiber 240 cannot be aligned with the first input waveguide 110 and the first output waveguide 120 of the silicon photonics chip 1 at the same time. Since the chip performance can only be effectively measured when they are aligned at the same time, the test will fail when they cannot be aligned.

[0025] Example 5 As Figure 3 shown, this example is a further improvement based on Example 4, specifically as follows: The tilt angle of the end face of the optical port of the fiber optic array is the same as the tilt angle of the first input waveguide 110, the first output waveguide 120, the second input waveguide 130, or the second output waveguide 140 in the silicon photonics chip 1. For example: if the tilt angle of the first input waveguide 110, the first output waveguide 120, the second input waveguide 130, or the second output waveguide 140 is 8°, then the tilt angle of the end face of the optical port of the fiber optic array is also 8°. Of course, this is just an exemplary example here, and other angles are not excluded in the actual application process.

[0026] Example 6 As Figure 4 shown, a method for testing a silicon photonics chip uses the chip-level test fiber optic array described in Example 4 or 5 to test the silicon photonics chip in any one of Examples 1 to 3, including the following steps: S1. Connect the third polarization-maintaining fiber 220 in the fiber array 2 to an external light source, and let the light source provide a large optical power. Also, connect the multimode fiber 230 in the fiber array 2 to an optical power meter. S2. Turn on the light source connected to the third polarization-maintaining fiber 220, and turn on the optical power meter connected to the multimode fiber 230. Align the third polarization-maintaining fiber 220 in the fiber array 2 with the second input waveguide 130 in the silicon photonics chip 1 in an active coupling manner, and align the multimode fiber 230 in the fiber array 2 with the second output waveguide 140 in the silicon photonics chip 1 in an active coupling manner, waiting for the measured photocurrent value by the MPD 150 to be the maximum and the measured optical power by the optical power meter to be the maximum. S3. Keep the positions of the silicon photonics chip 1 and the fiber array 2 unchanged. Turn off the light source connected to the third polarization-maintaining fiber 220, connect a light source to the first polarization-maintaining fiber 210, and connect an optical power meter to each of the second polarization-maintaining fibers 240. S4. Turn on the light source connected to the first polarization-maintaining fiber 210, and turn on the optical power meter connected to the second polarization-maintaining fiber 240. Fine-tune the angle of the fiber array 2 to make the fiber array 2 parallel to the silicon photonics chip 1, and align it in an active coupling manner to make the measured optical power by the optical power meter the maximum, then the performance of the silicon photonics chip 1 can be tested.

[0027] In this test scheme, the large optical power provided by the light source connected to the third polarization-maintaining fiber 220 > 20 dBm.

[0028] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A silicon photonics chip, characterized in that, On the same side, it has a first input waveguide (110), multiple first output waveguides (120), and a Loop loop. The first input waveguide (110) splits part of the light towards the MPD (150), and the other light is split towards the multiple first output waveguides (120) in a geometric progression; the Loop loop has a second input waveguide (130) and a second output waveguide (140). The second input waveguide (130) splits 90% of the light towards the MPD (150) and 10% of the light towards the second output waveguide (140); the widths of the first input waveguide (110), the first output waveguides (120), the second input waveguide (130), and the second output waveguide (140) are all 6μm ± 0.5μm.

2. The silicon photonic chip according to claim 1, wherein The first input waveguide (110), the first output waveguides (120), the second input waveguide (130), and the second output waveguide (140) are all inclined and parallel to each other.

3. A silicon photonics chip according to claim 1, characterized in that The number of the first output waveguides (120) is four.

4. A silicon photonics chip according to claim 3, wherein, The first input waveguide (110) is coupled to the input of a first 1×2 coupler (160). The two outputs of the first 1×2 coupler (160) are respectively coupled to the inputs of a second 1×2 coupler (170). The two outputs of each second 1×2 coupler (170) are respectively coupled to a first output waveguide (120) through an MZM modulator (180).

5. An optical fiber array for chip-level testing, characterized in that, To test the silicon optical chip (1) as described in any one of claims 1 to 4, it includes a first polarization-maintaining fiber (210), a third polarization-maintaining fiber (220), a multimode fiber (230), and four second polarization-maintaining fibers (240). The size of the third polarization-maintaining fiber (220) is 3μm ± 0.3μm, the size of the multimode fiber (230) is 50μm ± 1μm. The position of the first polarization-maintaining fiber (210) corresponds to the first input waveguide (110) in the silicon optical chip (1), the position of the third polarization-maintaining fiber (220) corresponds to the second input waveguide (130) in the silicon optical chip (1), the position of the multimode fiber (230) corresponds to the second output waveguide (140) in the silicon optical chip (1), and the positions of the four second polarization-maintaining fibers (240) respectively correspond to the four first output waveguides (120) in the silicon optical chip (1).

6. The fiber optic array for chip-level testing according to claim 5, wherein The inclination angle of its optical port end face is the same as that of the first input waveguide (110), the first output waveguides (120), the second input waveguide (130), or the second output waveguide (140).

7. A method for testing a silicon photonic chip, characterized in that, Using the chip-level test fiber array as described in claim 5 or 6 to test the silicon optical chip as described in any one of claims 1 to 4, includes the following steps: S1. The third polarization-maintaining fiber (220) is externally connected to a light source, and the light source provides a large optical power, and the multimode fiber (230) is externally connected to an optical power meter; S2. Turn on the light source connected to the third polarization-maintaining fiber (220) and the optical power meter connected to the multimode fiber (230). Actively couple and align the third polarization-maintaining fiber (220) in the fiber array (2) with the second input waveguide (130) in the silicon photonics chip (1), and actively couple and align the multimode fiber (230) in the fiber array (2) with the second output waveguide (140) in the silicon photonics chip (1), waiting for the photocurrent value measured by the MPD (150) to be the largest and the optical power measured by the optical power meter to be the largest. S3. Keep the positions of the silicon photonics chip (1) and the fiber array (2) unchanged. Turn off the light source connected to the third polarization-maintaining fiber (220), connect a light source to the first polarization-maintaining fiber (210), and connect an optical power meter to each of the second polarization-maintaining fibers (240). S4. Turn on the light source connected to the first polarization-maintaining fiber (210) and the optical power meter connected to the second polarization-maintaining fiber (240). Fine-tune the angle of the fiber array (2) so that the fiber array (2) is parallel to the silicon photonics chip (1) and, in the active coupling mode, aligned to the maximum optical power measured by the optical power meter, then the performance of the silicon photonics chip (1) can be tested.

8. A method for testing a silicon photonics chip according to claim 7, characterized in that, The high optical power provided by the light source connected to the third polarization-maintaining fiber (220) > 20 dBm.

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