Method for improving photoetching process window

Abstract

The invention discloses a method for improving a photoetching process window. The method comprises the following steps: providing a layout design comprising a pattern of a functional device and a pattern of a non-functional virtual structure; iteratively optimizing the layout design by adopting the first optical proximity effect correction; wherein the graph of the virtual structure is optimized as the graph of the functional device; carrying out weakness detection on the layout design after the first optical proximity effect correction, and screening out process weakness caused by the graph of the virtual structure; aiming at the process weakness caused by the graph of the virtual structure, performing optimization by adopting secondary optical proximity effect correction; wherein the second optical proximity effect correction is used for operating the graph of the virtual structure; and carrying out weakness detection on the layout design again, and judging whether the process weakness caused by the graph of the virtual structure is optimized or not. According to the technical scheme provided by the invention, the process introduced by the virtual structure is optimized, the process complexity is reduced, and the photoetching process window is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for improving a photolithography process window. Background Art

[0002] Optical Proximity Effect Correction (OPC) is an important part of lithography resolution enhancement technology. It adjusts the topological structure of the light-transmitting area on the lithography mask so that the exposed wafer image can meet the circuit design requirements to the greatest extent. It is crucial to improving the production quality and performance of semiconductor devices.

[0003] In the circuit design layout, there are virtual structures that are unrelated to actual electronic components. This virtual component structure is consistent with the layout graphic size of the main device, and plays a role in filling and stress dispersion in the process. In the OPC process operation, it has the same status as the layout of the main device and is processed as the main graphic. When this virtual structure has process weaknesses or introduces process weaknesses, OPC needs to adjust the auxiliary graphics for optimization, but does not perform special operations on the graphics themselves. Scattering bar modules are often used as auxiliary graphics to balance the imaging differences between dense graphics and sparse graphics areas and improve the common process window. With the increase in the complexity of the layout environment, the rules for adding scattering bars are also extremely complex. It is often necessary to adjust the parameter settings for adding scattering bars as the layout changes, and it is necessary to follow the principle of not being exposed. Under the specified process fluctuation conditions, it is often necessary to invest a high calculation process to obtain the best parameter combination.

[0004] Therefore, it is necessary to propose a new method for improving the photolithography process window to reduce process complexity and improve process efficiency. Summary of the invention

[0005] The object of the present invention is to provide a method for improving the photolithography process window to solve the problem of high process complexity of adjusting auxiliary graphics for optimization when a virtual structure introduces process weaknesses.

[0006] To achieve the above object, the present invention is implemented through the following technical solutions:

[0007] Providing a layout design, the layout design including a graphic of a functional device and a graphic of a non-functional dummy structure;

[0008] Iteratively optimizing the layout design by using a first optical proximity effect correction; wherein the pattern of the virtual structure is optimized as a pattern of a functional device;

[0009] Performing weakness detection on the layout design after the first optical proximity effect correction, and screening out process weaknesses caused by the pattern of the virtual structure;

[0010] Aiming at the process weakness caused by the pattern of the virtual structure, a second optical proximity effect correction is used for optimization; wherein the second optical proximity effect correction operates on the pattern of the virtual structure;

[0011] The layout design is again subjected to weakness detection to determine whether the process weakness caused by the pattern of the virtual structure is optimized.

[0012] Optionally, before providing a layout design, the method further includes:

[0013] In the layout design stage, the graphics of the virtual structure are identified;

[0014] A specific layer is used to identify the graphic of the virtual structure.

[0015] Optionally, the iterative optimization of the layout design by using a first optical proximity effect correction includes:

[0016] Establishing a photolithography model, wherein the photolithography model includes an optical model and a photoresist photochemical reaction model;

[0017] Identifying the graphic edges of the functional device and the graphic edges of the virtual structure in the layout design, and allowing each edge to move freely;

[0018] The edge position is continuously moved, and the corresponding exposed pattern is calculated based on the lithography model, and compared with the layout design to obtain the corresponding edge placement error, until the calculated edge placement error reaches the set value.

[0019] Optionally, the performing weakness detection on the layout design includes:

[0020] Build a rule base based on experience;

[0021] The layout design is subjected to weakness detection based on the established rule base.

[0022] Optionally, the performing weakness detection on the layout design after the optical proximity effect correction and screening out process weaknesses caused by the pattern of the virtual structure includes:

[0023] The layout design is subjected to weakness detection, and the detected process weaknesses are classified; wherein the classified categories include process weaknesses caused by the graphics of the virtual structure.

[0024] Optionally, the parameters based on which the vulnerability detection is performed include:

[0025] Reticle error enhancement factor, normalized pattern log slope, depth of field, critical dimension variation, and critical dimension uniformity.

[0026] Optionally, the optimization of the process weakness caused by the pattern of the virtual structure by using a second optical proximity effect correction includes:

[0027] Establishing a photolithography model, wherein the photolithography model includes an optical model and a photoresist photochemical reaction model;

[0028] Acquiring an adjustment range of the graphic of the virtual structure;

[0029] The pattern of the virtual structure is adjusted within the adjustment range, and a corresponding simulation process profile is acquired based on the photolithography model.

[0030] Optionally, adjusting the graphic of the virtual structure within the adjustment range includes:

[0031] The geometric size, the distance between the virtual structure and the surrounding graphics, the area and the position of the graphic are adjusted.

[0032] The present invention also provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above methods for improving the photolithography process window is implemented.

[0033] The present invention also provides an electronic device, comprising a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any of the above methods for improving the photolithography process window is implemented.

[0034] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0035] The method for improving the photolithography process window provided by the present invention distinguishes between the graphics of functional devices and the graphics of sub-functional virtual structures in the layout design, firstly uses the first optical proximity effect correction to iteratively optimize the layout design, and the first optical proximity effect correction regards the graphics of the virtual structure as the graphics of the functional device for optimization, then screens out the process weaknesses caused by the graphics of the virtual structure, and then performs a second optical proximity effect correction for the process weaknesses caused by the graphics of the virtual structure, and the second optical proximity effect correction only operates on the graphics of the virtual structure, and finally performs weakness detection on the optimized layout design to determine whether the process weaknesses caused by the graphics of the virtual structure are optimized. The technical solution of the present invention is aimed at the process weaknesses caused by the graphics of the virtual structure, and no longer uses the method of adding auxiliary graphics (such as scattering strips) for optimization, but directly operates on the graphics of the virtual structure, thereby reducing the process complexity and improving the photolithography process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A schematic diagram of a process for improving a photolithography process window provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a flow chart of a second optical proximity effect correction process according to an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the structure of a layout design provided by an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a structure after the layout design is optimized according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following is a further detailed description of a method for improving the lithography process window proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0041] See also Figure 1 , Figure 1 A schematic diagram of a process flow for improving a photolithography process window is provided in accordance with an embodiment of the present invention. The method comprises:

[0042] Step S1: Provide a layout design, which is a design file of a mask, including graphics of functional devices and graphics of non-functional dummy structures. The dummy structure (Dummy) is a semiconductor element or structure without function, which is usually used to fill unused areas in the chip to ensure that the structure and performance of other parts can be maintained. These fillers are usually made of the same material as the chip, but they will not be used for any circuit or logic function.

[0043] Step S2: Iteratively optimizing the layout design by using the first optical proximity effect correction; wherein the pattern of the virtual structure is optimized as the pattern of the functional device.

[0044] The optical proximity effect refers to the situation that during the exposure process, due to the interference and diffraction effects between adjacent patterns on the mask, the pattern projected onto the wafer is different from the pattern on the mask. As the size of the pattern on the mask decreases, the interference and diffraction effects between adjacent patterns become more obvious, and the deviation of the pattern after exposure becomes larger. The shape of the pattern on the mask is changed to compensate for the deformation of the lithography pattern produced in the photolithography process, so that the pattern obtained by lithography on the wafer is basically consistent with the expected pattern. This compensation mechanism of the mask pattern is called optical proximity effect correction.

[0045] Step S3: performing weakness detection on the layout design after the first optical proximity effect correction, and screening out process weaknesses caused by the pattern of the virtual structure;

[0046] Step S4: optimizing the process weakness caused by the pattern of the virtual structure by using a second optical proximity effect correction; wherein the second optical proximity effect correction operates on the pattern of the virtual structure.

[0047] Step S5: performing weakness detection on the layout design again to determine whether the process weakness caused by the pattern of the virtual structure has been optimized.

[0048] In the above embodiment, by distinguishing the graphics of functional devices and the graphics of sub-functional virtual structures in the layout design, the layout design is first iteratively optimized using the first optical proximity effect correction, and the first optical proximity effect correction optimizes the graphics of the virtual structure as the graphics of the functional device, and then the process weaknesses caused by the graphics of the virtual structure are screened out, and then the second optical proximity effect correction is performed for the process weaknesses caused by the graphics of the virtual structure, and the second optical proximity effect correction only operates on the graphics of the virtual structure, and finally the optimized layout design is tested for weaknesses to determine whether the process weaknesses caused by the graphics of the virtual structure are optimized. The technical solution of the present invention is aimed at the process weaknesses caused by the graphics of the virtual structure, and no longer uses the method of adding auxiliary graphics (such as scattering strips) for optimization, but directly operates on the graphics of the virtual structure, thereby reducing the process complexity and improving the lithography process window.

[0049] In some embodiments, before providing a layout design, the method further includes:

[0050] In the layout design stage, the graphics of the virtual structure are identified;

[0051] A specific layer is used to identify the graphic of the virtual structure.

[0052] In the above embodiment, the graphics of the virtual structure are identified in the layout design stage and marked with a specific layer, so that the graphics of the virtual structure can be operated in a targeted manner in step S4.

[0053] In some embodiments, the iterative optimization of the layout design using the first optical proximity effect correction includes:

[0054] Establishing a photolithography model, wherein the photolithography model includes an optical model and a photoresist photochemical reaction model;

[0055] Identifying the graphic edges of the functional device and the graphic edges of the virtual structure in the layout design, and allowing each edge to move freely;

[0056] The edge position is continuously moved, and the corresponding exposed pattern is calculated based on the lithography model, and compared with the layout design to obtain the corresponding edge placement error (Edge Placement Error, EPE), until the calculated edge placement error reaches the set value.

[0057] In the above embodiment, the optical proximity effect correction software uses the lithography model to predict the pattern after the mask exposure corresponding to the current layout design, and compares it with the target pattern to calculate the difference between the two. The difference between the current result and the target pattern is called edge placement error (EPE). The smaller the edge placement error value, the closer it is to the target, and this process is continuously iterated until the calculated edge placement error reaches the set specification range.

[0058] It should be noted that the first optical proximity effect correction regards the pattern of the virtual structure as the pattern of the functional device for iterative optimization.

[0059] In some embodiments, the performing weakness detection on the layout design includes:

[0060] Build a rule base based on experience;

[0061] The layout design is subjected to weakness detection based on the established rule base.

[0062] In the above embodiment, specifically, the post-exposure pattern corresponding to the layout design calculated last time can be corrected according to the first optical proximity effect, and the process weaknesses that exist can be determined based on the post-exposure pattern, and further it can be determined which process weaknesses are caused by the pattern of the virtual structure.

[0063] It should be noted that the establishment of the rule base is based on experience, and different rules are needed to detect weaknesses according to different process nodes. The rules can be classified according to the reasons for their formation. For example, a certain type of rule can be written to specifically detect process weaknesses caused by the virtual structure.

[0064] In some embodiments, the step of performing weakness detection on the layout design after the optical proximity effect correction and screening out process weaknesses caused by the pattern of the virtual structure includes:

[0065] The layout design is subjected to weakness detection, and the detected process weaknesses are classified; wherein the classified categories include process weaknesses caused by the graphics of the virtual structure.

[0066] In the above embodiment, the process weaknesses caused by the pattern of the virtual structure are screened out by classification.

[0067] In some embodiments, the parameters based on which the vulnerability detection is performed include:

[0068] Reticle error enhancement factor, normalized pattern log slope, depth of focus, critical dimension variation, and critical dimension uniformity.

[0069] Specifically, the Mask Error Enhancement Factor (MEEF) is the slope of the photoresist line width on the wafer as the mask pattern line width changes; the Normalized Image Log Slope (NILS) is an important parameter for measuring the spatial image quality in the lithography process. The larger the NILS value, the higher the spatial imaging contrast and the better the imaging quality; the Depth of Focus (DOF) refers to the maximum variable range of the focal length within the allowable range of variation of the line width; the Critical Dimension Variation (CDV) refers to the variation of the critical dimension (i.e., the minimum feature size on the chip, Critical Dimension, CD) between different locations or different wafers due to various factors in the semiconductor manufacturing process; the Critical Dimension Uniformity (CDU) is a key parameter for measuring the control performance of the lithography process, and is used to describe the consistency of the critical dimension on the entire wafer during the lithography process.

[0070] In the above embodiment, it can be determined based on one parameter or a combination of multiple parameters whether a process weakness exists and the type of the process weakness.

[0071] In some embodiments, see Figure 2 , the optimization using a second optical proximity effect correction for the process weakness caused by the pattern of the virtual structure includes:

[0072] Step S41: establishing a photolithography model, wherein the photolithography model includes an optical model and a photoresist photochemical reaction model;

[0073] Step S42: obtaining the adjustment range of the graphic of the virtual structure;

[0074] Step S43: adjusting the pattern of the virtual structure within the adjustment range, and acquiring a corresponding simulation process profile based on the photolithography model.

[0075] It should be noted that, in the above embodiment, the second optical proximity effect correction is only performed on the graphic of the virtual structure.

[0076] Specifically, adjusting the graphic of the virtual structure within the adjustment range includes:

[0077] The geometric size, the distance between the virtual structure and the surrounding graphics, the area and the position of the graphic are adjusted.

[0078] See also Figure 3 , Figure 3 A schematic diagram of a layout design provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown in the figure, the dotted box is the virtual structure. Figure 3 After the first optical proximity effect correction is performed on the mask corresponding to the layout design shown, in the calculated exposed pattern (not shown), the virtual structure is close to the patterns of the functional devices on both sides, which may easily cause risks. Therefore, during the second optical proximity effect correction, the pattern of the virtual structure may be optimized, for example, by adjusting the area of ​​the virtual structure. Figure 4 , interrupt the graphic of the virtual structure in the design layout (refer to Figure 4 In other embodiments, the graphics of the virtual structure can be optimized by adjusting the position of the virtual structure, the spacing between the virtual structure and the surrounding graphics, etc., which is not specifically limited here.

[0079] The present invention also provides a readable storage medium, wherein the readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above methods for improving the photolithography process window is implemented.

[0080] The present invention also provides an electronic device, comprising a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any of the above methods for improving the photolithography process window is implemented.

[0081] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0082] It should be noted that the devices and methods disclosed in the embodiments of this article can also be implemented in other ways. The device implementation described above is only schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of this article. In this regard, each box in the flowchart or block diagram can represent a part of a module, program or code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system for performing a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0083] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0084] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for improving a photolithography process window, characterized in that: include: Providing a layout design, the layout design including a graphic of a functional device and a graphic of a non-functional dummy structure; Iteratively optimizing the layout design by using a first optical proximity effect correction; wherein the pattern of the virtual structure is optimized as a pattern of a functional device; Performing weakness detection on the layout design after the first optical proximity effect correction, and screening out process weaknesses caused by the pattern of the virtual structure; Aiming at the process weakness caused by the pattern of the virtual structure, a second optical proximity effect correction is used for optimization; wherein the second optical proximity effect correction operates on the pattern of the virtual structure; The layout design is again subjected to weakness detection to determine whether the process weakness caused by the pattern of the virtual structure is optimized.

2. The method for improving the photolithography process window according to claim 1, characterized in that: Before providing a layout design, the method further includes: In the layout design stage, the graphics of the virtual structure are identified; A specific layer is used to identify the graphic of the virtual structure.

3. The method for improving the photolithography process window according to claim 1, characterized in that: The iterative optimization of the layout design by using the first optical proximity effect correction includes: Establishing a photolithography model, wherein the photolithography model includes an optical model and a photoresist photochemical reaction model; Identifying the graphic edges of the functional device and the graphic edges of the virtual structure in the layout design, and allowing each edge to move freely; The edge position is continuously moved, and the corresponding exposed pattern is calculated based on the lithography model, and compared with the layout design to obtain the corresponding edge placement error, until the calculated edge placement error reaches the set value.

4. The method for improving the photolithography process window according to claim 1, characterized in that: The performing weakness detection on the layout design comprises: Build a rule base based on experience; The layout design is subjected to weakness detection based on the established rule base.

5. The method for improving the photolithography process window according to claim 1, characterized in that: The step of performing weakness detection on the layout design after the optical proximity effect correction and screening out process weaknesses caused by the pattern of the virtual structure includes: The layout design is subjected to weakness detection, and the detected process weaknesses are classified; wherein the classified categories include process weaknesses caused by the graphics of the virtual structure.

6. The method for improving the photolithography process window according to claim 1, characterized in that: The parameters based on which the weakness detection is performed include: Reticle error enhancement factor, normalized pattern log slope, depth of field, critical dimension variation, and critical dimension uniformity.

7. The method for improving the photolithography process window according to claim 1, characterized in that: The optimization of the process weakness caused by the pattern of the virtual structure by using a second optical proximity effect correction includes: Establishing a photolithography model, wherein the photolithography model includes an optical model and a photoresist photochemical reaction model; Acquiring an adjustment range of the graphic of the virtual structure; The pattern of the virtual structure is adjusted within the adjustment range, and a corresponding simulation process profile is acquired based on the photolithography model.

8. The method for improving the photolithography process window according to claim 7, characterized in that: The adjusting the graphic of the virtual structure within the adjustment range includes: The geometric size, the distance between the virtual structure and the surrounding graphics, the area and the position of the graphic are adjusted.

9. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for improving the photolithography process window according to any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for improving the photolithography process window according to any one of claims 1 to 8 is implemented.

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