Variable-length instruction storage controller, control method, terminal and storage medium

Abstract

The invention discloses a variable-length instruction storage controller, a control method, a terminal and a storage medium, and relates to the technical field of integrated circuit design. The variable-length instruction storage controller comprises an address judgment module, a dual-port array, a one-adding summator, an instruction fetching shifting module and an instruction caching module. And the address judgment module outputs an instruction address to be fetched, the low L bit of the address is a control signal, and the rest high H bits are instruction reading addresses. A first reading port of the dual-port array outputs a first port instruction of a high H-bit address, and a second reading port outputs a second port instruction of an address obtained by adding 1 to the high H-bit address; based on the control signal, selecting a first instruction from the first port instructions, selecting a second instruction from the second port instructions, and combining the first instruction and the second instruction into a cache instruction; a displacement switch array included in the fetch shift module transmits a cache instruction to the instruction cache module, and the instruction with any length can be fetched from the instruction cache module, so that storage control of the instruction with the variable length is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a variable-length instruction storage controller, a control method, a terminal and a storage medium. Background Art

[0002] In traditional CPU architectures, instruction storage controllers usually store instructions with a fixed bit width (e.g., 32 bits). This design simplifies the hardware logic for instruction reading and execution, but it also leads to some efficiency issues. Some instructions may only require a shorter encoding length, and the traditional 32-bit instruction storage method wastes storage space. In some operations, the CPU will frequently use certain instructions. If a variable-length instruction storage controller is used, a shorter encoding length can be selected for frequently used instructions, which will significantly reduce the space requirements for instruction storage, thereby saving valuable instruction storage space, helping to reduce the size and cost of the entire instruction memory and improve the utilization efficiency of storage resources.

[0003] The prior art provides a method and device for caching variable-length instructions, which uses an auxiliary memory to store redundant copies of instruction data at cache boundary locations. The main purpose of the method is to solve the access efficiency problem when variable-length instructions cross cache line boundaries, but it cannot reduce the volume and cost of the entire instruction memory. The prior art also provides an instruction cache with a fixed number of variable-length instructions. This method requires the storage number of instructions to be known, and requires the use of a pre-decoder to pre-process the instructions. It is not suitable for scenarios where the storage number is unknown, and the pre-decoding operation increases the computational burden.

[0004] In summary, existing instruction memories have the disadvantages of being large in size and cost, having low resource utilization, and being unsuitable for scenarios where the storage quantity is unknown. Summary of the invention

[0005] The present invention provides a variable-length instruction storage controller, a control method, a terminal and a storage medium. A dual-port array is used to obtain instructions of adjacent addresses. The fetching of variable-length instructions can be controlled by using a known instruction length. The present invention has low volume and cost, high resource utilization, can realize automatic fetching of instructions, and can be applicable to scenarios where the storage quantity is unknown.

[0006] In a first aspect, the present invention provides a variable-length instruction storage controller, comprising: an address determination module, a dual-port array, an adder, an instruction fetch shift module and an instruction cache module;

[0007] The dual-port array includes a first read port, a second read port, a first write port, a second write port, a first enable port and a second enable port; the first enable port is used to control the first write port to write data or the first read port to read data; the second enable port is used to control the second write port to write data or the second read port to read data;

[0008] When used, multiple instructions of different lengths are pre-stored into the dual-port array;

[0009] The address judgment module outputs the address of the instruction to be fetched, the low L bit of the address of the instruction to be fetched is the control signal, L is equal to 1 or 2; the remaining high H bit address is transmitted to the first read port and the adder at the same time, the first read port outputs the first port instruction of the address based on the high H bit address; the adder adds 1 to the high H bit address and transmits it to the second read port; the second read port outputs the second port instruction of the address after adding 1; the first port instruction and the second port instruction are transmitted to the instruction fetch shift module;

[0010] Selecting a first instruction from the first port instructions based on the control signal, and selecting a second instruction from the second port instructions; combining the first instruction and the second instruction into a cache instruction;

[0011] The shift switch array included in the instruction fetch shift module transmits the cached instructions to the instruction cache module, and instructions of any length can be taken out from the instruction cache module to realize the storage control of variable-length instructions.

[0012] As a possible implementation, the variable-length instruction storage controller has an automatic mode and a manual mode; when in the automatic mode, the instruction length is input to the address determination module, and the variable-length instruction storage controller reads each instruction in sequence according to the order in which the instruction length is stored;

[0013] When in manual mode, a specified address is input to the address judgment module, and the variable-length instruction storage controller reads the variable-length instruction in the specified address.

[0014] As a possible implementation, the address determination module includes a first multiplexer, a trigger, and an adder, and the variable-length instruction storage controller is switched to an automatic mode or a manual mode by a switch signal, and the first multiplexer is used to output the address of the instruction to be fetched;

[0015] In the automatic mode, the trigger caches the current instruction address, the adder adds the current instruction address and the instruction length and transmits the result to the first multiplexer, and the first multiplexer outputs the address obtained after the addition as the address of the instruction to be fetched;

[0016] In manual mode, the first multiplexer outputs the specified address as the address of the instruction to be fetched.

[0017] As a possible implementation, the instruction fetch and shift module further includes a second multiplexer, and the second multiplexer controls the shift switch array to output instructions at positions corresponding to the first port instruction and the second port instruction based on a control signal.

[0018] As a possible implementation, the instruction length is N bits, 1≤N≤5; the specified address length is S bits, 8≤S≤16; the dual-port array capacity is R bits, 256≤R≤64K; and the instruction cache module capacity is P bits, 16≤P≤40.

[0019] In a second aspect, the present invention provides a variable-length instruction storage control method, using the variable-length instruction storage controller provided in the first aspect, comprising the following steps:

[0020] S1. Pre-store multiple instructions into the dual-port array to generate the address of the instruction to be fetched;

[0021] S2. Divide the address of the instruction to be fetched into a low L bit and a high H bit, where L is equal to 1 or 2;

[0022] S3. Read the instruction based on the high H bit and generate a control signal based on the low L bit;

[0023] S4. The control signal controls the displacement switch array to output the instruction of the corresponding position to the instruction cache module;

[0024] S5. Take out variable-length instructions from the instruction cache module.

[0025] As a possible implementation method, in automatic mode, the instruction length is input, and each instruction is read in sequence according to the order in which it is stored based on the instruction length; in manual mode, a specified address is input, and variable-length instructions in the specified address are read.

[0026] As a possible implementation manner, in automatic mode, the address of the instruction to be fetched is the address obtained by adding the current instruction address and the instruction length; in manual mode, the address of the instruction to be fetched is the specified address.

[0027] In a third aspect, the present invention provides a terminal, comprising a processor and a communication interface coupled to the processor, wherein the processor is used to run a computer program or instruction to implement the variable-length instruction storage control method provided in the first aspect.

[0028] In a fourth aspect, the present invention provides a computer-readable storage medium, comprising a processor and a communication interface coupled to the processor, wherein the processor is used to run a computer program or instruction to implement the variable-length instruction storage control method provided in the first aspect.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] 1. By using the variable-length instruction storage controller provided by the present invention, users can store instructions according to their actual length, rather than uniformly using a longer fixed length, thereby saving storage space, improving the utilization efficiency of storage resources, and helping to reduce the cost and volume of the overall hardware.

[0031] 2. The variable-length instruction storage controller provided by the present invention can be applied to scenarios where the storage quantity is unknown, and can cope with more flexible instruction usage and requirements.

[0032] 3. The variable-length instruction storage controller provided by the present invention reduces pre-decoding operations, thereby reducing the computational burden.

[0033] 4. The variable-length instruction storage controller provided by the present invention has good compatibility and can adapt to instruction sets of different lengths and types. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0035] Figure 1 Schematic diagram of a variable length instruction storage controller in an embodiment of the present invention;

[0036] Figure 2 A control logic diagram of a variable-length instruction storage controller in automatic mode according to an embodiment of the present invention;

[0037] Figure 3 A control logic diagram of a variable-length instruction storage controller in a manual mode according to an embodiment of the present invention;

[0038] Figure 4 Flowchart of a variable length instruction storage control method in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0040] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0041] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. The following at least one item (items) or similar expressions thereof refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one item (items) of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0042] In the traditional CPU instruction fetching process, the instruction length of each instruction fetch is fixed at 32 bits. Since some instructions are used frequently, if 8 bits, 16 bits or 24 bits are used to encode these instructions, more instruction storage space can be saved. The present invention provides a variable-length instruction storage controller, a control method, a terminal and a storage medium, which use a dual-port array to obtain instructions of adjacent addresses, and use a known instruction length to control the fetching of variable-length instructions.

[0043] In a first aspect, the present invention provides a variable length instruction storage controller, see Figure 1 , including: address judgment module, dual-port array, add-1 adder, instruction fetch shift module and instruction cache module;

[0044] When in use, multiple instructions of different lengths are stored in the dual-port array in advance; the variable-length instruction storage controller provided by the present invention can be applicable to scenarios where the storage quantity is unknown, and can cope with more flexible instruction usage and requirements.

[0045] The dual-port array includes a first read port, a second read port, a first write port, a second write port, a first enable port and a second enable port; the first enable port is used to control the first write port to write data or the first read port to read data; the second enable port is used to control the second write port to write data or the second read port to read data;

[0046] As a possible implementation, the variable-length instruction storage controller has an automatic mode and a manual mode; when in the automatic mode, the instruction length is input to the address determination module, and the variable-length instruction storage controller reads each instruction in sequence according to the order in which the instruction length is stored;

[0047] When in manual mode, a specified address is input to the address judgment module, and the variable-length instruction storage controller reads the variable-length instruction in the specified address.

[0048] Address judgment module, outputs the address of the instruction to be fetched;

[0049] As a possible implementation, the address judgment module includes a first multiplexer, a trigger, and an adder. The variable-length instruction storage controller is controlled by a switch signal to switch to an automatic mode or a manual mode. When the switch signal is 0, it switches to the automatic mode, and when the switch signal is 1, it switches to the manual mode. The first multiplexer is used to output the address of the instruction to be fetched;

[0050] In the automatic mode, the trigger caches the current instruction address, the adder adds the current instruction address and the instruction length and transmits the result to the first multiplexer, and the first multiplexer outputs the address obtained after the addition as the address of the instruction to be fetched;

[0051] In manual mode, the first multiplexer outputs the specified address as the address of the instruction to be fetched.

[0052] As an example of automatic mode, if the instruction length input to the address judgment module is 3 bits, the instruction length can be 001, 010, 011, 100, 101, corresponding to instruction lengths of 8 bits, 16 bits, 24 bits, 32 bits, and 40 bits, respectively. Assuming the value is 001, that is, the instruction length is 8 bits, and assuming that the current instruction address of the trigger cache is 11001100110, the adder performs binary addition on the current instruction address 11001100110 and the instruction length 001 to obtain 11001100111, and the first multiplexer outputs 11001100111 as the instruction address to be fetched.

[0053] As an example of a manual mode, a designated address 11001100110 is input to the address determination module, and the first multiplexer directly outputs 11001100110 as the address of the instruction to be fetched.

[0054] The low L bit of the address of the instruction to be fetched is a control signal, where L is equal to 1 or 2; the remaining high H bit addresses are simultaneously transmitted to the first read port and the adder, and the first read port outputs the first port instruction of the address based on the high H bit address; the adder adds 1 to the high H bit address and transmits it to the second read port; the second read port outputs the second port instruction of the address after adding 1; the first port instruction and the second port instruction are transmitted to the instruction fetch shift module;

[0055] As an example, assuming that the address of the instruction to be fetched is 11001100110, 11001100110 is divided into the upper 9 bits 110011001 and the lower 2 bits 10, and the first read port outputs the first port instruction of the address 110011001; the adder adds 1 to 110011001 to obtain 110011010, and the second port outputs the second port instruction of the address 110011010.

[0056] Selecting a first instruction from the first port instructions based on the control signal, and selecting a second instruction from the second port instructions; combining the first instruction and the second instruction into a cache instruction;

[0057] As an example, the instruction cache module is set to 40 bits. When the lower 2 bits of the address of the instruction to be fetched are 00, the 32 bits of port one and the 8 bits of port two are combined into a 40-bit cache instruction; when the lower 2 bits of the address of the instruction to be fetched are 01, the 24 bits of port one and the 16 bits of port two are combined into a 40-bit cache instruction; when the lower 2 bits of the address of the instruction to be fetched are 10, the 16 bits of port one and the 32 bits of port two are combined into a 40-bit cache instruction; when the lower 2 bits of the address of the instruction to be fetched are 11, the 8 bits of port one and the 32 bits of port two are combined into a 40-bit cache instruction.

[0058] Exemplarily, the control signal is 10 in the lower 2 bits, and the upper 16 bits in the first port instruction and the lower 32 bits in the second port instruction are combined into a 40-bit cache instruction. The shift switch array included in the instruction fetch shift module transmits the cache instruction to the instruction cache module, and instructions of any length can be taken out from the instruction cache module to realize the storage control of variable-length instructions.

[0059] As an example, the shift switch array transmits a 40-bit cache instruction to the instruction cache module, and can take out 8 bits, 16 bits, 24 bits, 32 bits or 40 bits from the instruction cache module to implement storage control of variable-length instructions.

[0060] The variable-length instruction storage controller provided by the present invention reduces pre-decoding operations, thereby reducing the calculation burden.

[0061] As a possible implementation, the instruction fetch and shift module further includes a second multiplexer, and the second multiplexer controls the shift switch array to output instructions at positions corresponding to the first port instruction and the second port instruction based on a control signal.

[0062] As a possible implementation, the instruction length is N bits, 1≤N≤5, for example: N=1, N=2, N=3, N=4, N=5; the specified address length is S bits, 8≤S≤16, for example: S=8, S=9, S=10, S=11, S=12, S=13, S=14S=15, S=16; the dual-port array capacity is R bits, 256≤R≤64K; the instruction cache module capacity is P bits, 16≤P≤40; for example: P=16, P=24, P=32, P=40.

[0063] The variable-length instruction storage controller provided by the present invention has good compatibility and can adapt to instruction sets of different lengths and types.

[0064] To facilitate understanding of the technical solution of the present application, further description is given below in conjunction with specific embodiments.

[0065] See also Figure 2 , which is a control logic diagram of the variable length instruction storage controller provided by the present invention in automatic mode. Input the instruction length 001 to the address judgment module, that is, the instruction length is 8 bits. Assuming that the current instruction address of the trigger cache is 11001100110, the adder performs binary addition on the current instruction address 11001100110 and the instruction length 001 to obtain 11001100111, and the first multiplexer outputs 11001100111 as the instruction address to be fetched.

[0066] The instruction address 11001100111 to be fetched is divided into the upper 9 bits 110011001 and the lower 2 bits 11, and the upper 9 bits 110011001 are transmitted to the first read port; the adder adds 1 to 110011001 to obtain 110011010, and transmits 110011010 to the second read port. The instruction fetch displacement module receives the first port instruction of the address 110011001 and the second port instruction of the address 110011010.

[0067] The lower 2 bits 11 are used as control signal input, see Figure 2 At this time, 8 bits of the first port instruction and 32 bits of the second port instruction are selected to form a 40-bit cache instruction. The shift switch array transmits the 40-bit cache instruction to the instruction cache module. Users can take out 8 bits, 16 bits, 24 bits, 32 bits or 40 bits from the instruction cache module according to their own needs to realize storage control of variable-length instructions.

[0068] See also Figure 3, which is a control logic diagram of the variable length instruction storage controller provided by the present invention in manual mode. The specified address 11001100110 is input to the address judgment module, and the first multiplexer directly outputs 11001100110 as the address of the instruction to be fetched.

[0069] The instruction address 11001100110 to be fetched is divided into the upper 9 bits 110011001 and the lower 2 bits 10, and the upper 9 bits 110011001 are transmitted to the first read port; the adder adds 1 to 110011001 to obtain 110011010, and transmits 110011010 to the second read port. The instruction fetch displacement module receives the first port instruction of the address 110011001 and the second port instruction of the address 110011010.

[0070] The lower 2 bits 10 are used as control signal input, see Figure 3 At this time, 16 bits of the first port instruction and 24 bits of the second port instruction are selected to form a 40-bit cache instruction. The shift switch array transmits the 40-bit cache instruction to the instruction cache module. Users can take out 8 bits, 16 bits, 24 bits, 32 bits or 40 bits from the instruction cache module according to their own needs to realize the storage control of variable-length instructions.

[0071] By using the variable-length instruction storage controller provided by the present invention, users can store instructions according to their actual length, rather than uniformly using a longer fixed length, thereby saving storage space, improving the utilization efficiency of storage resources, and helping to reduce the cost and volume of the overall hardware.

[0072] In a second aspect, the present invention provides a variable length instruction storage control method, using the variable length instruction storage controller provided in the first aspect, see Figure 4 , including the following steps:

[0073] S1. Pre-store multiple instructions into the dual-port array to generate the address of the instruction to be fetched;

[0074] S2. Divide the address of the instruction to be fetched into a low L bit and a high H bit, where L is equal to 1 or 2;

[0075] S3. Read the instruction based on the high H bit and generate a control signal based on the low L bit;

[0076] S4. The control signal controls the displacement switch array to output the instruction of the corresponding position to the instruction cache module;

[0077] S5. Take out variable-length instructions from the instruction cache module.

[0078] As a possible implementation method, in automatic mode, the instruction length is input, and each instruction is read in sequence according to the order in which it is stored based on the instruction length; in manual mode, a specified address is input, and variable-length instructions in the specified address are read.

[0079] As a possible implementation manner, in automatic mode, the address of the instruction to be fetched is the address obtained by adding the current instruction address and the instruction length; in manual mode, the address of the instruction to be fetched is the specified address.

[0080] In a third aspect, the present invention provides a terminal, comprising a processor and a communication interface coupled to the processor, wherein the processor is used to run a computer program or instruction to implement the variable-length instruction storage control method provided in the first aspect.

[0081] In a fourth aspect, the present invention provides a computer-readable storage medium, comprising a processor and a communication interface coupled to the processor, wherein the processor is used to run a computer program or instruction to implement the variable-length instruction storage control method provided in the first aspect.

[0082] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the drawings, etc. In the specification, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the specification. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0083] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the present invention and its equivalents.

Claims

1. A variable length instruction storage controller, characterized in that: The variable length instruction storage controller comprises: an address determination module, a dual port array, an adder, an instruction fetch shift module and an instruction cache module; The dual-port array includes a first read port, a second read port, a first write port, a second write port, a first enable port and a second enable port; the first enable port is used to control the first write port to write data or the first read port to read data; the second enable port is used to control the second write port to write data or the second read port to read data; When in use, a plurality of instructions of different lengths are stored in advance in the dual-port array; The address judgment module outputs the address of the instruction to be fetched, the low L bit of the address of the instruction to be fetched is a control signal, and L is equal to 1 or 2; the remaining high H bit addresses are simultaneously transmitted to the first read port and the adder, and the first read port outputs the first port instruction of the address based on the high H bit address; the adder adds 1 to the high H bit address and transmits it to the second read port; the second read port outputs the second port instruction of the address after adding 1; the first port instruction and the second port instruction are transmitted to the instruction fetch shift module; Selecting a first instruction from the first port instructions and a second instruction from the second port instructions based on the control signal; combining the first instruction and the second instruction into a cache instruction; The shift switch array included in the instruction fetch and shift module transmits the cache instruction to the instruction cache module, and instructions of any length can be taken out from the instruction cache module to realize storage control of variable-length instructions.

2. The variable length instruction storage controller according to claim 1, characterized in that: The variable-length instruction storage controller has an automatic mode and a manual mode; when in the automatic mode, the instruction length is input to the address determination module, and the variable-length instruction storage controller reads each instruction in sequence according to the order in which the instruction length is stored; When in manual mode, a designated address is input to the address determination module, and the variable-length instruction storage controller reads the variable-length instruction in the designated address.

3. The variable length instruction storage controller according to claim 2, characterized in that: The address determination module includes a first multiplexer, a trigger, and an adder. The variable-length instruction storage controller is controlled by a switch signal to switch to an automatic mode or a manual mode. The first multiplexer is used to output the address of the instruction to be fetched; In the automatic mode, the trigger caches the current instruction address, the adder adds the current instruction address and the instruction length and transmits the result to the first multiplexer, and the first multiplexer outputs the address obtained after the addition as the address of the instruction to be fetched; In manual mode, the first multiplexer outputs the specified address as the address of the instruction to be fetched.

4. The variable length instruction storage controller according to claim 1, characterized in that: The instruction fetch and shift module further includes a second multiplexer, and the second multiplexer controls the shift switch array to output instructions at positions corresponding to the first port instruction and the second port instruction based on the control signal.

5. The variable length instruction storage controller according to claim 2, characterized in that: The instruction length is N bits, 1≤N≤5; the designated address length is S bits, 8≤S≤16; the dual-port array capacity is R bits, 256≤R≤64K; the instruction cache module capacity is P bits, 16≤P≤40.

6. A variable length instruction storage control method, using the variable length instruction storage controller according to any one of claims 1 to 5, characterized in that: The steps include: S1. Pre-store multiple instructions into the dual-port array to generate the address of the instruction to be fetched; S2. Divide the instruction address to be fetched into a low L bit and a high H bit, where L is equal to 1 or 2; S3. Based on the high H-bit read instruction, a control signal is generated based on the low L-bit; S4. The control signal controls the displacement switch array to output the instruction of the corresponding position to the instruction cache module; S5. Take out variable-length instructions from the instruction cache module.

7. The variable length instruction storage control method according to claim 6, characterized in that: In automatic mode, the instruction length is input, and each instruction is read in sequence according to the order in which it is stored based on the instruction length; in manual mode, a specified address is input, and the variable-length instruction in the specified address is read.

8. The variable length instruction storage control method according to claim 7, characterized in that: In automatic mode, the address of the instruction to be fetched is the address obtained by adding the current instruction address and the instruction length; in manual mode, the address of the instruction to be fetched is the specified address.

9. A terminal, characterized in that: It comprises a processor and a communication interface coupled to the processor, wherein the processor is used to run a computer program or instruction to implement the variable-length instruction storage control method as described in any one of claims 6 to 8.

10. A computer-readable storage medium, comprising a processor and a communication interface coupled to the processor, wherein the processor is configured to execute a computer program or instruction to implement the variable-length instruction storage control method according to any one of claims 6 to 8.

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