Controller of a storage device and instruction scheduling method

Abstract

Disclose a controller and an instruction scheduling method for a storage device. A plurality of CA buses and CA control units corresponding to the plurality of CA buses one by one are arranged in each channel of the controller of the storage device. By increasing the number of CA buses in each channel, only a small amount of physical resources need to be added to improve the bandwidth utilization rate of the DQ bus. Moreover, the number of CA buses in each channel can be flexibly configured, and corresponding bandwidth matching designs can be made for different performance scenarios to balance chip area and performance.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a controller and an instruction scheduling method for a storage device. Background Art

[0002] Currently, many storage devices, such as USB flash drives, SD cards, CF cards, SSDs, eMMC embedded memory cards, UFS devices, etc., use flash memory storage media (especially NAND-type storage media) as the main storage media and are gradually becoming the mainstream form. Compared with traditional magnetic medium memories, their performance has made a qualitative leap. For the traditional flash memory interface protocols (ONFi or Toggle) applied to such storage devices, commands / addresses and data are transmitted using the same bus. As the data transmission rate of the flash memory interface increases, while the command / address transmission rate remains unchanged, the proportion of the command / address transmission time increases, resulting in a bottleneck in the improvement of the data transmission bandwidth of the flash memory interface.

[0003] To solve the problem of the improvement of the traditional flash memory interface, a new flash memory interface protocol (for example, Separate CommandAddress, abbreviated as SCA) separates the command / address and data transmissions and places them on two different transmission buses for transmission, that is, the CA instruction is transmitted on the Command and Address (abbreviated as CA) bus, and the DQ instruction (i.e., the data to be written to or read from the flash memory storage medium) is transmitted on the DATA (also called DQ) bus.

[0004] As the transmission rate of the DQ bus becomes higher and higher, the time consumed by the storage device to read a unit of data becomes shorter and shorter. However, since the CA bus is a low-speed signal and its operating frequency has a maximum limit, the time required for the CA instruction on the CA bus can no longer be shortened by increasing the frequency. When the time required for transmission on the DQ bus is less than the time required for the CA instruction on the CA bus, the data transmission on the DQ bus will be idle because it needs to wait for the execution of the CA instruction on the CA bus. As Figure 1 shown, the data transmission G needs to wait for the commands A / B / C / D / G to be executed before it can start; during the execution of the command G, the DQ bus is idle, resulting in waste of the DQ bus bandwidth. In this case, the data transmission bandwidth of the bus of the flash memory storage medium is limited and no longer increases with the increase in the input / output transmission rate of the flash memory storage medium. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide an instruction scheduling method and apparatus to solve the above problems.

[0006] According to the first aspect of the embodiments of the present disclosure, a controller for a storage device is provided. The controller includes at least one channel. The first channel in the at least one channel is coupled to a plurality of flash memory particles through a plurality of CA buses and a DQ bus. The first channel includes:

[0007] An instruction cache unit that caches various instructions adapted to the plurality of flash memory particles through a plurality of instruction queues respectively;

[0008] A plurality of CA control units, corresponding to the plurality of CA buses one by one. Each CA control unit is responsible for writing a corresponding CA instruction to its corresponding CA bus;

[0009] A DQ control unit, corresponding to the DQ bus, for writing data from a data path to a corresponding flash memory particle or reading data from the corresponding flash memory particle to the data path via the DQ bus according to a received DQ instruction;

[0010] An arbitration scheduling unit for monitoring the working states of the plurality of CA control units and the DQ control unit, selecting a CA instruction or a DQ instruction from the plurality of instruction queues for a CA control unit or a DQ control unit in an idle state, and sending the selected CA instruction or DQ instruction to the CA control unit or DQ control unit in the idle state.

[0011] In some embodiments, for the storage device, the transmission times of the DQ bus and the CA bus in a plurality of scenarios of random read, random write, sequential read, and sequential write for a single DQ bus and a single CA bus are obtained, and the transmission times of the DQ bus and the CA bus are compared and summarized to obtain the preferred number of CA buses in the first channel.

[0012] In some embodiments, the preferred number of CA buses in the first channel is equal to the ceiling of the data transmission time of a single CA bus divided by the data transmission time of a single CA bus.

[0013] In some embodiments, the selected CA instruction is a CA instruction that can be executed in parallel with the DQ instruction being executed by the DQ control unit and the CA instructions being executed by the plurality of CA control units, and the selected DQ instruction is a DQ command that can be executed in parallel with the CA instructions being executed by the plurality of CA control units.

[0014] In some embodiments, the selected CA instruction is the first CA instruction in the corresponding instruction queue, and the selected DQ instruction is the first DQ instruction in the corresponding instruction queue.

[0015] In some embodiments, the selected CA instruction is the CA instruction with the highest priority among multiple CA instructions that meet the requirements, and the selected DQ instruction is the DQ instruction with the highest priority among multiple DQ instructions that meet the requirements.

[0016] In some embodiments, the controller further includes:

[0017] A command parser, configured to parse the received host command, convert it into an instruction adapted to the flash memory particles, and store the instruction in the instruction cache unit.

[0018] According to a second aspect of the embodiments of the present disclosure, there is provided an instruction scheduling method for a controller of a storage device. The controller includes at least one channel. The first channel in the at least one channel is coupled to a plurality of flash memory particles through a plurality of CA buses and a DQ bus. The first channel further includes a plurality of CA control units that control the plurality of CA buses one-to-one, and the first channel further includes a DQ control unit responsible for controlling the DQ bus. The instruction scheduling method includes:

[0019] Monitoring the status of the plurality of CA control units and the DQ control unit;

[0020] When the first CA control unit among the plurality of CA control units is in an idle state, take out a CA instruction that can be executed in parallel with the currently executing CA instruction and DQ instruction from a plurality of instruction queues, and send it to the first CA control unit for execution. The plurality of instruction queues respectively cache various instructions adapted to the plurality of flash memory particles;

[0021] When the DQ control unit is in an idle state, take out a DQ instruction that can be executed in parallel with the currently executing CA instruction from a plurality of instruction queues, and send it to the DQ control unit for execution.

[0022] In some embodiments, it further includes: if there are multiple CA instructions that meet the conditions, select the CA instruction with the highest priority and send it to the first CA control unit for execution; and

[0023] if there are multiple DQ instructions that meet the conditions, select the DQ instruction with the highest priority and send it to the DQ control unit for execution.

[0024] According to a third aspect of the embodiments of the present disclosure, there is provided a storage device, including: a controller and a flash memory storage medium that are coupled, and the controller is the controller described above.

[0025] According to the controller of the storage device provided by the embodiments of the present disclosure, a plurality of CA control units are designed in each channel corresponding to a plurality of CA buses. By increasing the number of CA buses in the channel, only a small amount of physical resources need to be added to improve the bandwidth utilization rate of the DQ bus. Moreover, the number of CA buses in each channel can be flexibly configured, and corresponding bandwidth matching designs can be made for different performance scenarios to balance the chip area and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0027] Figure 1 is an example diagram of the parallel execution of the CA bus and the DQ bus;

[0028] Figure 2 is a schematic block diagram of an exemplary host system;

[0029] Figure 3 is a schematic structural diagram of the instruction scheduling device provided by the embodiments of the present disclosure;

[0030] Figure 4 is applied to the Figure 3 control flowchart of the arbitration scheduling unit in;

[0031] Figure 5 is another example diagram of the parallel execution on the CA bus and the DQ bus. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0033] The following describes the present invention based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details. In order to avoid obscuring the essence of the present invention, well-known methods, processes, procedures, elements, and circuits are not described in detail.

[0034] Unless the context clearly requires otherwise, the words "comprising", "including" and similar words in the entire specification and claims shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0035] Figure 2 FIG. is a schematic block diagram of an exemplary host system 100. The host system 100 is, for example, a personal computer, a laptop computer, or a server.

[0036] The host system 100 includes a host device 110 (for example, a computer system including a main processor and a memory) and a storage device. The host device 110 can issue host commands to the storage device, so that the storage device manages the data stored in the storage device according to the commands. For example, the host device 110 can be communicatively connected to the storage device (for example, through a host interface) and issue various commands (for example, READ, WRITE, UNMAP, REASSIGN BLOCK, TRIM, etc.) to the storage device. The storage device can store, update, read, and / or otherwise manage host data according to the address range prompted by the commands. Once the command is executed, the storage device can transmit a response to the host device 110, thereby indicating that the command has been successfully completed.

[0037] The storage device consists of a controller 120 and a storage medium 130. The controller 120 parses the host commands, converts the host commands into instructions adapted to the storage medium 130, then executes the instructions and feeds back the instruction results to the host device 110. The controller 120 consists of various software and hardware. The hardware is, for example, a (micro)processor, cache units such as SRAM and DRAM, and interface circuits. The software is, for example, a series of software programs for completing management functions, including but not limited to data reading and writing, bad block management, wear leveling, garbage collection, power-off recovery, and write balancing techniques.

[0038] The storage medium 130 is used to store data. There are multiple channels (for example, CH0 and CH1) between the controller 120 and the storage medium 130, and the controller 120 and the storage medium 130 perform data interaction through each channel.

[0039] Currently, the mainstream storage medium 130 is a flash storage medium (especially NAND-type storage medium). Generally, each channel (such as CH0 or CH1 in the figure) is coupled to N (N is 2, 4, 8, etc.) flash memory particles, and the controller 120 needs to operate the corresponding flash memory particles through each channel. When the SCA protocol is used as the flash interface protocol, each channel includes two buses: the DQ bus and the CA bus. The controller 120 executes DQ instructions through the DQ bus to write data to or read data from the flash memory particles, and executes CA instructions through the CA bus to perform command / address operations on the flash memory particles.

[0040] As an alternative solution, the data transfer bandwidth of the flash interface can be increased and the performance of the processor can be improved by adding more channels between the controller 120 and the storage medium 130, thereby solving the problems raised in the background art. However, this solution requires the controller 120 to increase a lot of IO resources and logic control resources, which will cause a sharp increase in the chip area and product cost of the controller 120. For this reason, the embodiments of the present disclosure propose another solution. Figure 3 The schematic structural diagram of the controller 120 of the storage device proposed by the embodiments of the present disclosure is shown.

[0041] As Figure 3 shown, the controller 120 includes a host interface 301, a command parser 302, a channel 303, and a physical layer module 304. The channel 303 includes an instruction cache unit 3031, an arbitration scheduling unit 3032, n CA control units from 0 to n-1, 1 DQ control unit, and a data path 3033. The channel 303 is coupled to n CA buses and 1 DQ bus via the physical layer module 304, and further coupled to m flash memory particles, so that the controller 120 can access the m flash memory particles through the channel 303 and the above buses. Here, both m and n are positive integers greater than or equal to 2. It should be understood that the controller 120 usually has multiple channels, but for simplicity, only a single channel 303 is described as an example here.

[0042] The host interface 301 is used to receive host commands from the host device 110 and perform data transmission with the host device 110. The host commands are, for example, a write command for writing data to the flash storage medium 130, a read command for reading data from the flash storage medium, a query command for checking the execution status of the write command or the read command, and so on. The interface protocol adopted by the host interface 301 determines various command types and formats. For example, when using UPIU (UFS Protocol Information Units) as the interface protocol, the transmitted UPIU packet consists of multiple parts such as a header and a payload. The header provides information such as the interaction type, length, and attributes, and the payload provides the specific content of the command or data.

[0043] The command parser 302 parses the received host commands, converts them into instructions adapted to the flash memory particles, and stores the instructions in the instruction cache unit 3031. Flash memory particles of different products support different instruction sets. For example, for a "write operation", different flash memory particle products have different instruction formats. Therefore, the command parser 302 needs to convert the received host commands into corresponding instruction formats. The command parser 302 can convert one host command into multiple instructions adapted to the flash memory particles, or convert multiple host commands into multiple instructions adapted to the flash memory particles. The embodiments of the present disclosure do not specifically limit the correspondence between the number of host commands and the number of instructions adapted to the flash memory particles.

[0044] Based on the SCA protocol, the command parser 302 classifies the instructions adapted to the flash memory particles into CA instructions and DQ instructions. CA instructions are generally operation instructions related to the configuration of the flash memory particles, such as instructions for reading the status of the flash memory particles and instructions for modifying the status of registers on the flash memory particles. DQ instructions are generally instructions related to the data stored on the flash memory particles, such as instructions for reading or writing data to the flash memory particles. The command parser 302 can also obtain the priority of each CA instruction and store the priority corresponding to the respective CA instruction in the instruction cache unit.

[0045] In some embodiments, the command parser 302 maintains multiple first-in, first-out instruction queues in the instruction cache unit 3031 for multiple flash memory particles respectively, for storing CA instructions and DQ instructions adapted to each flash memory particle respectively. The figure shows (m + 1) instruction queues corresponding to flash memory particles DIE 0 to DIE m respectively.

[0046] CA control units 0 to n - 1 correspond one-to-one with CA buses 0 to CA bus n - 1 respectively. Each CA control unit is responsible for writing the corresponding CA instruction to the corresponding CA bus via the physical layer module 304 to execute the CA instruction through the CA bus.

[0047] The DQ control unit 3034, corresponding to the DQ bus 0, is used to write data from the data path 3033 to the corresponding flash memory particle via the DQ bus 0 according to the received DQ instruction, or read data from the corresponding flash memory particle to the data path 3033. The data path 3033 is, for example, a cache. The data to be written to the flash memory particle is first placed in the data path 3033 and then taken away by the DQ control unit 3034. The data read from the flash memory particle is first placed in the data path 3033 by the DQ control unit 3034 and then transmitted to the host device 110.

[0048] The physical layer module 304 refers to the hardware and software components in the physical layer of the controller 120, which are responsible for managing the transmission and storage of data on the physical medium, including converting the internal digital control signal into a high-speed analog signal for input and output, and converting the high-speed analog signal into an internal digital control signal.

[0049] The arbitration scheduling unit 3032 is responsible for monitoring the working states of multiple CA control units and DQ control units. When one of the control units is in an idle state, it takes out a CA instruction or a DQ instruction from a certain instruction queue and sends the taken-out CA instruction or DQ instruction to the idle CA control unit or DQ control unit. Due to the SCA protocol limitation, some DQ instructions and / or CA instructions cannot be executed in parallel. Therefore, the arbitration scheduling unit 3032 needs to detect and exclude some instructions that conflict with the currently executing CA instructions and / or DQ instructions during the above process, and ensure that the CA instructions or DQ instructions sent to the idle CA control unit or DQ control unit can be executed in parallel with the currently executing CA instructions and / or DQ instructions. For example, if the CA instruction is a DQ-relate instruction, it conflicts with the DQ data transfer command of the same LUN (Logical Unit Number), and these two commands cannot be executed simultaneously.

[0050] Figure 4 It is the control flow chart provided by the embodiment of the present disclosure for the arbitration scheduling unit 3032, which specifically includes the following steps.

[0051] In step S401, monitor the states of the CA and DQ control units.

[0052] In step S402, if there is an idle DQ control unit, execute step S404.

[0053] In step S403, if there is an idle CA control unit, execute step S405.

[0054] In step S404, select the queue whose first instruction is a DQ instruction.

[0055] In step S405, select the queue whose first instruction is a CA instruction.

[0056] In step S406, select DQ instructions that do not conflict with all the currently executing CA instructions.

[0057] In step S407, select CA instructions that do not conflict with the currently executing DQ instruction.

[0058] In step S408, select the DQ instruction with the highest priority.

[0059] In step S409, select the CA instruction with the highest priority.

[0060] In step S410, send the corresponding DQ instruction to the idle DQ control unit.

[0061] In step S411, send the corresponding CA instruction to the idle CA control unit.

[0062] According to this embodiment, continuously monitor the status of all CA control units and DQ control units. When a DQ control unit is in an idle state, it is necessary to obtain a DQ instruction from multiple instruction queues. This DQ instruction can be executed in parallel with the currently executing CA instruction, so that the DQ instruction can be sent to the idle DQ control unit. To this end, first find a queue whose first instruction is a DQ instruction and take out the first instruction from it, and determine whether this instruction can be executed in parallel with the currently executing CA instruction. If so, send this instruction to the idle DQ control unit for execution. If there are multiple queues whose first instruction is a DQ instruction, take out these first instructions from them and determine which of these instructions can be executed in parallel with the currently executing CA instruction. If there are multiple instructions that can be executed in parallel with the currently executing CA instruction, send the instruction with the highest priority among them to the idle DQ control unit for execution.

[0063] When a certain CA control unit is in an idle state, it is necessary to obtain a CA instruction from multiple instruction queues. This CA instruction can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions, so that the CA instruction can be sent to the idle CA control unit. To this end, a queue whose first instruction is a CA instruction can be found first and the first instruction can be taken out, and it is determined whether the instruction can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions. If so, the instruction is sent to the idle CA control unit. If there are multiple queues whose first instruction is a CA instruction, these first instructions are taken out, and it is determined which of these instructions can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions. If there are multiple instructions that can be executed in parallel with the currently executing DQ instruction and the remaining CA instructions, the instruction with the highest priority is sent to the idle CA control unit for execution

[0064] Figure 5 It is another example diagram of parallel execution on the CA bus and the DQ bus.

[0065] Reference Figure 5 As shown, when data transfer X is executed, the arbitration scheduling unit distributes CA instructions B / C / G to be executed on CA bus 0 of CA control unit 0; distributes CA instructions A / D to be executed on CA bus 1 of CA control unit 1. Since the two CA buses are executed in parallel, the CA instructions obtain twice the bandwidth. Before data transfer X is completed, data transfer G starts to be executed. The prerequisite is that commands A / B / C / D / G have been executed. Then, after data transfer X is executed, data transfer G can start to be executed immediately. In this way, data transfers are tightly connected on the DQ bus, making full use of the bandwidth of the DQ bus.

[0066] According to the above embodiments, a pair of N (N is an integer greater than or equal to 2) DQ buses and CA buses are respectively set in each channel of the controller of the memory, which can, to a certain extent, avoid the idle state of the DQ bus caused by waiting for the execution of CA instructions on the CA bus. As long as the DQ bus is busy most of the time, the data transfer bandwidth of the DQ bus and the data transfer bandwidth of the flash memory interface can be improved. However, the larger N is, the more the chip area and product cost of the controller increase. Therefore, an appropriate value of N needs to be selected. Generally, for a certain storage device, the transmission time of a single DQ bus and a single CA bus in multiple scenarios can be obtained through experiments, and the preferred value of N of the storage device can be estimated by comparing and summarizing the data transfer times of the single DQ bus and the single CA bus. The multiple scenarios include but are not limited to: random read, random write, sequential read, and sequential write. These reads and writes are generally carried out in units of storage pages (4K units).

[0067] For a certain storage device, if the data transfer time of a single CA bus is N times that of a single DQ bus, then N is preferably equal to the ceiling of the division of the data transfer time of a single CA bus by the data transfer time of a single DQ bus. More specifically, for example, m samples in multiple scenarios are obtained through experiments. The i-th sample is represented as {}, representing the data transfer time of the CA bus in the i-th sample, and representing the data transfer time of the DQ bus in the i-th sample. Then, the following formula (1) is used to obtain N:

[0068] N >= Max(ceil( / )) i = 1, …, m (1),

[0069] where ceil() represents ceiling, Max represents selecting the maximum value, and the preferred value of N is the selected maximum value.

[0070] According to the controller of the storage device provided by the embodiments of the present disclosure, a plurality of CA buses and CA control units corresponding to the plurality of CA buses one by one are provided in each channel. By increasing the number of CA buses in the channel, only a small amount of physical resources need to be added to improve the bandwidth utilization rate of the DQ bus. Moreover, the number of CA buses in each channel can be flexibly configured, and corresponding bandwidth matching designs can be made for different performance scenarios to balance the chip area and performance.

[0071] As described above in the embodiments of the present invention, these embodiments do not elaborate on all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A controller of a storage device, the controller comprising at least one channel, a first channel of the at least one channel being coupled to a plurality of flash memory particles through a plurality of CA buses and a DQ bus, the first channel comprising: An instruction cache unit, which caches various instructions adapted to the plurality of flash memory particles respectively through a plurality of instruction queues; A plurality of CA control units, corresponding one to one with the plurality of CA buses, each CA control unit being responsible for writing a corresponding CA instruction into its corresponding CA bus; A DQ control unit, corresponding to the DQ bus, for writing data from a data path to a corresponding flash memory particle via the DQ bus according to a received DQ instruction, or reading data from a corresponding flash memory particle to the data path; The arbitration scheduling unit is used to monitor the working status of the multiple CA control units and the DQ control unit, select a CA instruction or a DQ instruction from the multiple instruction queues for a CA control unit or a DQ control unit in an idle state, and send the selected CA instruction or the DQ instruction to the CA control unit or the DQ control unit in an idle state.

2. The controller according to claim 1, wherein: For the storage device, transmission times of a single DQ bus and a single CA bus in multiple scenarios of random reading, random writing, continuous reading, and continuous writing are obtained, and the transmission times of the DQ bus and the CA bus are compared and summarized to obtain a preferred number of CA buses in the first channel.

3. The controller according to claim 2, wherein: The preferred number of CA buses in the first channel is equal to the data transmission time of a single CA bus divided by the data transmission time of a single CA bus, and the result is rounded up.

4. The controller according to claim 1, wherein: The selected CA instruction is a CA instruction that can be executed in parallel with the DQ instruction being executed by the DQ control unit and the CA instruction being executed by the CA control unit. The selected DQ instruction is a DQ command that can be executed in parallel with the CA instruction being executed by the CA control unit.

5. The controller according to claim 4, wherein: The selected CA instruction is the first CA instruction in the corresponding instruction queue, and the selected DQ instruction is the first DQ instruction in the corresponding instruction queue.

6. The controller according to claim 4, wherein: The selected CA instruction is the CA instruction with the highest priority among multiple CA instructions that meet the requirements, and the selected DQ instruction is the DQ instruction with the highest priority among multiple DQ instructions that meet the requirements.

7. The controller according to any one of claims 1 to 6, wherein: The controller further comprises: The command parser is used to parse the received host command, convert it into an instruction adapted to the flash memory particle, and store the instruction in the instruction cache unit.

8. A method for scheduling instructions, for use in a controller of a storage device, the controller comprising at least one channel, a first channel of the at least one channel being coupled to a plurality of flash memory particles through a plurality of CA buses and a DQ bus, the first channel further comprising a plurality of CA control units for controlling the plurality of CA buses one-to-one, the first channel further comprising a DQ control unit responsible for controlling the DQ bus, the method for scheduling instructions comprising: monitoring states of the plurality of CA control units and the DQ control unit; When a first CA control unit among the multiple CA control units is in an idle state, taking out a CA instruction that can be executed in parallel with the currently executed CA instruction and DQ instruction from the multiple instruction queues, and sending the CA instruction to the first CA control unit for execution, wherein the multiple instruction queues respectively cache various instructions adapted to the multiple flash memory particles; When the DQ control unit is in an idle state, a DQ instruction that can be executed in parallel with the currently executing CA instruction is taken out from multiple instruction queues and sent to the DQ control unit for execution.

9. The instruction scheduling method according to claim 8, further comprising: If there are multiple CA instructions that meet the conditions, select the CA instruction with the highest priority and send it to the first CA control unit for execution; as well as If there are multiple DQ instructions that meet the conditions, the DQ instruction with the highest priority is selected and sent to the DQ control unit for execution.

10. A storage device comprising: A coupled controller and a flash memory storage medium, wherein the controller is a controller as described in any one of claims 1 to 7.

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