PCIE peripheral secondary scanning link establishment method based on Loongson 3A5000 and 7A1000 chipsets

Abstract

The invention provides a PCIE peripheral secondary scanning link establishment method based on Loongson 3A5000 and 7A1000 chipsets, and belongs to the technical field of electronic information. The PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets mainly comprises the steps of designing a mainboard PCIE golden finger interface hardware circuit, reading and configuring a PCIE register of the Loongson 3A5000, loading an FPGA and performing a secondary scanning mode on PCIE equipment; and the secondary scanning and the re-link establishment of the Loongson 3A5000 and the PCIE peripheral are realized. Dynamic switching of PCIE peripheral functions is achieved in the environment of Loongson 3A5000 and 7A1000 chip sets, it is ensured that the switching process is transparent to a user, normal use is not affected, the flexibility and expansibility of equipment can be further improved, and very high practical value and commercial value are achieved; by adopting a 3A5000 domestic processor, secondary scanning and link establishment of the PCIE peripheral can be realized, and the same function as that of an imported x86 processor is realized.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a PCIE peripheral secondary scanning and link building method based on Loongson 3A5000 and 7A1000 chipsets. Background Art

[0002] The PCIE interface is a high-speed interface for communication between the processor and peripherals. PCIE peripherals with dedicated customized functions are usually implemented using FPGA chips with integrated PCIE hard cores. When the functions of PCIE peripherals with customized functions need to switch between multiple functional modes, the FPGA chip resources and power consumption are limited, and all functions cannot be implemented at the same time. In order to effectively reduce the size, power consumption and cost of PCIE peripherals, the functions of PCIE peripherals can be dynamically replaced on demand, thereby improving the versatility and flexibility of the equipment.

[0003] More and more devices are using domestic alternatives. In the past, when PCIE peripherals were used with x86 architecture processors and north and south bridge chipsets, after the FPGA logic of the PCIE peripherals was reloaded, it was only necessary to uninstall the driver, uninstall the device, and then scan the device to directly complete the secondary scanning and linking method. However, when the Loongson 3A5000 domestic processor and 7A1000 chipset are used to replace the traditional x86 architecture processor and north and south bridge chipset, the x86 technical method cannot be used to achieve the secondary scanning and linking of PCIE peripherals. Summary of the invention

[0004] The present invention provides a method for secondary scanning and link building of PCIE peripherals based on Loongson 3A5000 and 7A1000 chipsets. When the function mode of a PCIE device needs to be replaced, a function loading module of the PCIE peripheral is used to secondary load the logic of the FPGA, and then the content of the present invention is used to implement secondary scanning and link building of the PCIE device, thereby realizing the function change of the PCIE peripheral.

[0005] The invention provides a PCIE peripheral secondary scanning link building method based on Loongson 3A5000 and 7A1000 chipset, comprising: establishing a link between Loongson 3A5000 and a PCIE peripheral, loading a PCIE driver of the PCIE peripheral, and acquiring a PCIE node number of the PCIE peripheral and a value of a related configuration register; wherein the Loongson 3A5000 is connected to the PCIE peripheral via the 7A1000 chipset; when it is necessary to switch the function of the PCIE peripheral, the PCIE peripheral is notified to prepare to switch to a new function, and the current PCIE driver is unloaded; the FPGA chip of the PCIE peripheral loads a logic file of the new function in an active or passive manner; disconnecting the link between the Loongson 3A5000 and the PCIE peripheral, using the previously read PCIE node number and the value of the related configuration register, writing back the related configuration register of the PCIE peripheral, and enabling the PCIE peripheral; firstly unloading the PCIE peripheral, and then performing a secondary scanning on the PCIE peripheral to complete the re-link building between the Loongson 3A5000 and the PCIE peripheral.

[0006] According to the present invention, a PCIE peripheral secondary scanning and link establishment method based on the Loongson 3A5000 and 7A1000 chipsets also includes: loading a driver for a new functional mode of the PCIE peripheral to complete the call of a new function of the PCIE peripheral.

[0007] According to a PCIE peripheral secondary scanning link establishment method based on Loongson 3A5000 and 7A1000 chipsets provided by the present invention, the hardware design of the gold finger link between the 7A1000 chipset and the PCIE peripheral includes: shielding the reset signal of the PCIE interface of the 7A1000 chipset and using the global reset signal on the PCB.

[0008] According to a PCIE peripheral secondary scanning and link building method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention, the value of the relevant configuration register of the PCIE peripheral is read using the busybox tool of the Loongson 3A5000 operating system.

[0009] According to a PCIE peripheral secondary scanning and linking method based on the Loongson 3A5000 and 7A1000 chipset provided by the present invention, the PCIE peripheral is first uninstalled, and then the PCIE peripheral is scanned for a second time, including: using a first instruction and a PCIE node number of the PCIE peripheral to uninstall the PCIE peripheral; and using a second instruction to implement a secondary scanning of the PCIE peripheral of the Loongson 3A5000, and completing the re-linking of the Loongson 3A5000 and the PCIE peripheral.

[0010] According to a PCIE peripheral secondary scanning and link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention, PCIE peripherals are enabled, including: enabling the PCIE peripherals by configuring the status and command registers of the PCIE peripherals.

[0011] According to a PCIE peripheral secondary scanning and link building method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention, the FPGA chip actively loads the logic file of the new function, including: the FPGA chip actively downloads and loads the new function logic file through the network or local storage device.

[0012] According to a PCIE peripheral secondary scanning and link building method based on the Loongson 3A5000 and 7A1000 chipset provided by the present invention, the FPGA chip loads the logic file of the new function in a passive manner, including: the FPGA chip receives the logic file of the new function transmitted by the Loongson 3A5000 through a specific communication protocol.

[0013] The PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention has the following beneficial effects:

[0014] (1) The PCIE peripheral secondary scanning and link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention realizes dynamic switching of PCIE peripheral functions in the environment of the Loongson 3A5000 and 7A1000 chipsets, ensuring that the switching process is transparent to the user and does not affect normal use, and can further increase the flexibility and scalability of the device, and has very high practical value and commercial value.

[0015] (2) The PCIE peripheral secondary scanning and link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention can also realize the secondary scanning and link establishment of PCIE peripherals by using the 3A5000 domestic processor, and realize the same function as the imported x86 processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a flow chart of a PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention;

[0018] Figure 2 It is a schematic diagram of the connection between the Loongson 3A5000 and the PCIE peripherals provided by the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that, in the description of the embodiments of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0021] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0022] Combine the following Figure 1-Figure 2 The present invention describes a method for secondary scanning and link establishment of PCIE peripherals based on the Loongson 3A5000 and 7A1000 chipsets provided in an embodiment of the present invention.

[0023] Figure 1 : is a flow chart of the PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention, such as Figure 1 As shown, including but not limited to the following steps:

[0024] Step 101: Establish a link between Loongson 3A5000 and PCIE peripherals, load the PCIE driver of the PCIE peripherals, and obtain the PCIE node number of the PCIE peripherals and the values ​​of related configuration registers; wherein, Loongson 3A5000 is connected to the PCIE peripherals through the 7A1000 chipset.

[0025] Ensure that the Loongson 3A5000 processor and PCIE devices are powered on at the same time; when the system starts, enumerate all devices and load the default PCIE driver.

[0026] While waiting for the PCIE peripheral to be powered on and the first link establishment to be completed, determine the PCIE node number of the PCIE peripheral, and read the values ​​of the relevant configuration registers BAR10, BAR54, BAR58, BAR18, BAR1C, BAR20, BAR24 and BAR30 in sequence through the busybox tool of the Loongson 3A5000 operating system, and cache them locally as intermediate values.

[0027] Figure 2 Schematic diagram of the connection between the Loongson 3A5000 and PCIE peripherals provided by the present invention, such as Figure 2 As shown in the figure, the Loongson 3A5000 processor is connected to the Loongson 7A1000 bridge chip through the HyperTransport X16 interface. This bridge chip is responsible for transferring the CPU data to the PCIE bus. The PCIE hard core is integrated in an FPGA chip, which implements the standard specification of PCIE 2.0, allowing the FPGA to work as a PCIE peripheral. Finally, inside the FPGA, the functional logic of the PCIE peripheral can be loaded in an active or passive manner to achieve different functions.

[0028] It should be noted that the hardware design of the gold finger of the Loongson 3A5000 and 7A1000 chipsets and PCIE peripherals should pay attention to the design of the reset signal: when designing, it is necessary to shield the reset signal of the PCIE interface of the 7A1000 chipset, and use the global reset signal on the PCB to ensure that when the registers of the Loongson 3A5000 are operated, the reset signal is not sent to the FPGA chip of the PCIE peripheral.

[0029] Step 102: When the function of the PCIE peripheral needs to be switched, the PCIE peripheral is notified to prepare to switch to a new function, and the current PCIE driver is uninstalled.

[0030] When the Loongson 3A5000 processor needs to change the function of the PCIE peripheral, it notifies the PCIE peripheral to change the specified function and uninstalls the driver of the PCIE peripheral to prevent the program from communicating with the PCIE peripheral and blocking the PCIE channel.

[0031] Step 103: The FPGA chip of the PCIE peripheral loads the logic file of the new function in an active or passive manner.

[0032] Among them, active loading includes: the FPGA chip actively downloads and loads new functional logic files through the network or local storage device;

[0033] Passive loading includes: the FPGA chip receives the logic file of the new function transmitted by the host system (Loongson 3A5000) through a specific communication protocol.

[0034] Optionally, the specific communication protocols include the following two:

[0035] JTAG is a standard test protocol, commonly used for boundary scan testing and programming of chips. FPGA chips usually have a JTAG interface, which can be used for programming.

[0036] SPI is a synchronous serial communication interface, commonly used for short-distance communication. FPGA chips can load new functional logic from external memory (such as SPI Flash) through the SPI interface.

[0037] Step 104: Disconnect the link between Loongson 3A5000 and the PCIE peripheral, use the previously read PCIE node number and the value of the related configuration register to write back the related configuration register of the PCIE peripheral, and enable the PCIE peripheral.

[0038] After the present invention waits for the FPGA to load the logic file, the Loongson 3A5000 writes back the values ​​of the relevant configuration registers in sequence. Finally, the state and command registers of the PCIE peripherals are written back to enable the PCIE peripherals.

[0039] Step 105: Uninstall the PCIE peripherals first, and then scan the PCIE peripherals for a second time to complete the re-establishment of the link between the Loongson 3A5000 and the PCIE peripherals.

[0040] Optionally, the present invention can use the first instruction and the PCIE node number of the PCIE peripheral to uninstall the PCIE peripheral; and, the present invention can use the second instruction to implement a secondary scan of the PCIE peripherals of the Loongson 3A5000 to complete the re-linking of the Loongson 3A5000 and the PCIE peripherals.

[0041] Optionally, the PCIE peripheral secondary scanning and link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention also includes: loading a driver for a new functional mode of the PCIE peripheral to complete the call of a new function of the PCIE peripheral.

[0042] Based on the content of the above embodiment, as an optional embodiment, the present invention provides a PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets, comprising the following steps:

[0043] Step 1: The hardware design of the PCIE signal of the 7A1000 domestic bridge chip needs to shield the reset signal of the PCIE interface of the 7A1000 bridge chip and use the global reset signal on the PCB.

[0044] Step 2: Wait for the Loongson 3A5000 and PCIE peripherals to be powered on at the same time, and load the initial functions of the PCIE peripherals by default. At this time, record the PCIE node number and the values ​​of related configuration registers. After the operating system is started, load the default driver to call the PCIE peripherals.

[0045] Step 3: When the function of the PCIE peripheral needs to be switched, first notify the PCIE peripheral to switch to the specified function, then uninstall the PCIE peripheral driver, and wait for the new function of the FPGA chip of the PCIE peripheral to be loaded.

[0046] Step 4: According to the hardware design of the PCIE peripheral FPGA chip, you can choose to actively or passively load the logic file of the specified function to the PCIE peripheral FPGA chip.

[0047] Step 5: After waiting for the global loading of the FPGA resources of the PCIE peripheral to be completed, 3A5000 will disconnect from the PCIE peripheral. It is necessary to use the previously read PCIE register value to write back the register, and finally configure the PCIE command and status register to re-enable the device.

[0048] Step 6: Remove the PCIE peripheral first, then execute the rescan function of the PCIE peripheral to complete the secondary link between 3A5000 and the PCIE peripheral.

[0049] Step 7: Load the driver of the new function of the PCIE peripheral to complete the call of the new function of the PCIE peripheral.

[0050] Based on the content of the above embodiment, as an optional embodiment, the present invention provides a PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets, comprising the following steps:

[0051] A. The PCIE peripheral is powered on together with the Loongson 3A5000 processor, the slot node number of the PCIE peripheral is queried, and the relevant configuration register information of the node is read;

[0052] B. When the PCIE peripheral function needs to be switched, the Loongson 3A5000 processor first notifies the PCIE peripheral to switch to the specified function, then uninstalls the PCIE peripheral driver, and the FPGA of the PCIE peripheral actively or passively loads the logic file of the specified function;

[0053] C. After waiting for the new logic function of the FPGA of the PCIE peripheral to be loaded, the Loongson 3A5000 will lose the link with the PCIE peripheral;

[0054] D. The Loongson 3A5000 processor sequentially writes back the configuration registers of the PCIE peripheral that were previously read, and enables the command and status registers of the PCIE peripheral to enable the PCIE peripheral.

[0055] E. The Loongson 3A5000 processor first removes the PCIE device through instructions, and then scans the PCIE device for the second time through instructions to complete the re-establishment of the link between the Loongson 3A5000 processor and the PCIE peripheral.

[0056] F. The Loongson 3A5000 processor reloads the PCIE peripheral driver to call the new functions of the PCIE peripheral.

[0057] In summary, the PCIE peripheral secondary scanning link establishment method based on the Loongson 3A5000 and 7A1000 chipsets provided by the present invention has the following beneficial effects:

[0058] (1) The function of the PCIE peripheral can be switched at will, realizing seamless switching of the PCIE peripheral function;

[0059] (2) The use of 3A5000 domestic processors can also realize secondary scanning and link building of PCIE peripherals, achieving the same functions as imported x86 processors.

[0060] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0061] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A PCIE peripheral secondary scanning link building method based on Loongson 3A5000 and 7A1000 chipsets, characterized in that: include: Establish a link between Loongson 3A5000 and PCIE peripherals, load the PCIE driver of the PCIE peripherals, and obtain the PCIE node number and the value of the relevant configuration register of the PCIE peripherals; wherein, Loongson 3A5000 is connected to the PCIE peripherals through the 7A1000 chipset; When the function of the PCIE peripheral needs to be switched, the PCIE peripheral is notified to switch to a new function and the current PCIE driver is uninstalled; The FPGA chip of the PCIE peripheral uses active or passive methods to load the logic file of the new function; Disconnect the link between Loongson 3A5000 and PCIE peripherals, use the previously read PCIE node number and the value of the relevant configuration register to write back the relevant configuration registers of the PCIE peripherals, and enable the PCIE peripherals; Uninstall the PCIE peripherals first, and then scan the PCIE peripherals for a second time to complete the re-establishment of the link between Loongson 3A5000 and the PCIE peripherals.

2. According to claim 1, the PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets is characterized in that: Also includes: The driver of the new functional mode of the PCIE peripheral is loaded to complete the call of the new function of the PCIE peripheral.

3. The PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets according to claim 1 is characterized in that: The hardware design of the gold finger link between the 7A1000 chipset and PCIE peripherals includes: shielding the reset signal of the PCIE interface of the 7A1000 chipset and using the global reset signal on the PCB.

4. The PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets according to claim 1 is characterized in that: The values ​​of the relevant configuration registers of the PCIE peripherals are read using the busybox tool of the Loongson 3A5000 operating system.

5. The PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets according to claim 1 is characterized in that: Uninstall the PCIE peripherals first, and then perform a second scan on the PCIE peripherals, including: Uninstalling the PCIE peripheral using the first instruction and the PCIE node number of the PCIE peripheral; and, The second instruction is used to perform a second scan on the PCIE peripherals of Loongson 3A5000 to complete the re-link between Loongson 3A5000 and the PCIE peripherals.

6. The PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets according to claim 1 is characterized in that: Enable PCIE peripherals, including: Enable the PCIE peripherals by configuring the status and command registers of the PCIE peripherals.

7. The PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets according to claim 1 is characterized in that: The FPGA chip uses an active method to load the logic files of new functions, including: The FPGA chip actively downloads and loads new functional logic files through the network or local storage device.

8. The PCIE peripheral secondary scanning link building method based on the Loongson 3A5000 and 7A1000 chipsets according to claim 1 is characterized in that: The FPGA chip uses a passive method to load the logic file of the new function, including: The FPGA chip receives the logic file of the new function transmitted by the Loongson 3A5000 through a specific communication protocol.

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