Waveform data capturing method, device and equipment for multiple FPGAs (Field Programmable Gate Array) and storage medium
Through the signal configuration management of multi-chip FPGAs and the logic-side data interaction, the problem of low waveform data grabbing efficiency in the prior art is solved, and efficient grabbing and flexible adjustment of multi-bit data is achieved.
Patent Information
- Application Number
- CN202411489147.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-02-18
AI Technical Summary
The existing multi-chip waveform data grabbing methods can only sample register signals and can only perform data grabbing according to single bit bits, resulting in low data grabbing efficiency and long time.
Through multiple FPGAs, the signal configuration file is read to generate a signal configuration set, the target signal configuration is found and sent to the logical side, the waveform data returned by the logical side is read and the waveform data set is generated, and the standard viewable format file is decoded.
It realizes sampling of signals outside the register, supports reading of multi-bit data, and significantly improves the efficiency and flexibility of waveform data capture.
Smart Images
Figure CN119474801A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of software-hardware collaborative simulation, and in particular to a waveform data capture method, device, equipment and storage medium for multiple FPGAs. Background Art
[0002] FPGA, the full name of which is Field Programmable Gate Array, is an integrated chip mainly based on digital circuits and a type of programmable logic device (PLD). Waveform data capture refers to the process of capturing and recording waveform data from the circuit or system under test using an oscilloscope or other test equipment.
[0003] As the scale of integrated circuits continues to expand, the time spent on chip verification is increasing. In addition to traditional simulators, the use of emulators based on software-hardware collaboration is becoming more and more popular, improving the efficiency of verification through software-hardware collaborative simulation verification.
[0004] The existing waveform data capture method that supports multiple chips has limited signals that can be sampled and can only sample register signals. At the same time, waveform data can only be captured by single bit, that is, it is limited to capturing waveform data with the lowest data accuracy (i.e. single bit). Therefore, the efficiency of data capture is low and time-consuming. Summary of the invention
[0005] In order to improve the efficiency of waveform data capture, the present application provides a waveform data capture method, device, equipment and storage medium for multiple FPGAs.
[0006] In a first aspect, the present application provides a waveform data capture method for multiple FPGAs, which adopts the following technical solution: the method comprises:
[0007] Reading a signal configuration file containing a signal configuration, extracting the signal configuration and generating a signal configuration set;
[0008] When a query instruction of a sampling signal set is received, the sampling signal set includes a sampling signal, and a target signal configuration corresponding to the sampling signal is searched in the signal configuration set according to the sampling signal;
[0009] Sending all the target signal configurations found to the logic side;
[0010] All the target signal configurations found are stored locally as a sampling signal set configuration file;
[0011] By performing data interaction with the FPGA corresponding to the sampling signal, the waveform data returned by the logic side is read and a waveform data set is generated;
[0012] The waveform data set is written to a disk as a waveform data file, the waveform data file is decoded into a standard viewable format file according to the sampling signal set configuration file, and the standard viewable format file is exported.
[0013] Through the above technical solution, the FPGA chip can read other signals besides the register and generate a signal configuration set in advance, making it more convenient to capture the data of multiple signals and reducing the time spent on repeated captures. At the same time, reading the waveform data returned by the logic side can read multiple bits of data at a time, greatly improving the efficiency of waveform data capture.
[0014] In a specific implementation scheme, the signal configuration includes:
[0015] Signal name, signal ID, FPGA chip ID, signal bit information, the signal name and signal ID are unique identifiers of the signal, the FPGA chip ID is the unique identifier of the FPGA chip, and the signal bit information includes the bits contained in the signal.
[0016] Through the above technical solution, the signal-related information is recorded in the signal configuration and can be called at any time when needed, avoiding repeated searching and improving the overall operation efficiency.
[0017] In a specific implementation scheme, the sampling signal includes a sampling signal ID or a sampling signal name, and searching the signal configuration set for a target signal corresponding to the sampling signal according to the sampling signal includes:
[0018] According to the sampling signal ID or the sampling signal name, the target signal configuration corresponding to the sampling signal is searched in the signal configuration set.
[0019] Through the above technical solution, because the signal name and signal ID are unique identifiers of the signal, the target signal configuration can be accurately and quickly found in the configuration set according to the signal name or signal ID.
[0020] In a specific possible implementation scheme, the target signal configuration includes a target FPGA chip ID corresponding to the sampled signal;
[0021] The step of performing data interaction with the FPGA corresponding to the sampling signal, reading the waveform data returned by the logic side and generating a waveform data set includes:
[0022] Find the corresponding target FPGA chip according to the target FPGA chip ID, and create a target Control instance according to the target FPGA chip;
[0023] The target Control instance exchanges data with the target FPGA chip, reads the waveform data returned by the logic side and generates a waveform data set.
[0024] Through the above technical solution, with the help of the Control instance, data interaction is carried out with the FPGA slice area where the sampling signal bit is located to read the waveform data. By reading the area, multiple bits can be read at a time, which is more efficient.
[0025] In a specific implementation scheme, creating a target Control instance according to the target FPGA chip includes:
[0026] The target Control instance is created and managed according to the target FPGA chip through the Manager module.
[0027] Through the above technical solution, multiple Control instances are generated according to the number of FPGA chips, and each Control instance corresponds to the FPGA chip ID. Multiple Control instances are created and managed through the Manager module, so that the data of each Control instance is relatively independent and not easy to be contaminated by each other.
[0028] In a specific possible implementation scheme, after the waveform data set is written to a disk as a waveform data file, the method further includes:
[0029] querying whether a sampling signal modification instruction is received, wherein the sampling signal modification instruction includes modification information for the sampling signal;
[0030] If the sampling signal modification instruction is received, modifying the sampling signal set according to the modification information to obtain a new sampling signal set;
[0031] Generate a new waveform data set and a new sampling signal set configuration file according to the new sampling signal set, and save the new waveform data set to a disk as a new waveform data file;
[0032] If the sampling signal modification instruction is not received, the original sampling signal set configuration file and the waveform data file are used.
[0033] Through the above technical solution, the sampling signal set can be paused and modified at any time during the process of capturing waveform data, and sampling signals can be added or reduced. The sampling signal set can be dynamically adjusted during operation, which greatly improves flexibility and efficiency.
[0034] In a specific implementation scheme, decoding the waveform data file into a standard viewable format file and exporting it according to the sampled signal set configuration file includes:
[0035] At the end of the simulation, all the waveform data files are decoded one by one according to the corresponding sampling signal configuration set files, and the waveforms are merged to generate a standard viewable format file.
[0036] Through the above technical solution, when the simulation ends, if there are multiple waveform data files, they are merged into a standard viewable format file during the decoding process, and exported as a standard viewable format file to make it easier for users to understand and analyze the data.
[0037] In a second aspect, the present application provides a waveform data capture device for multiple FPGAs, which adopts the following technical solution: the device comprises:
[0038] A configuration set generation module, used to read a signal configuration file containing a signal configuration, extract the signal configuration and generate a signal configuration set;
[0039] A sampling signal query module, configured to, upon receiving a query instruction for a sampling signal set, wherein the sampling signal set includes a sampling signal, search the signal configuration set for a target signal configuration corresponding to the sampling signal according to the sampling signal;
[0040] A signal configuration sending module, used to send all the target signal configurations found to the logic side;
[0041] A configuration file storage module, used for locally storing all the target signal configurations found as a sampling signal set configuration file;
[0042] A waveform data reading module, used to perform data interaction with the FPGA corresponding to the sampling signal, read the waveform data returned by the logic side and generate a waveform data set;
[0043] The decoding file export module is used to store the waveform data set into a disk as a waveform data file, decode the waveform data file into a standard browseable format file according to the sampling signal set configuration file, and export the standard browseable format file.
[0044] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and executes the waveform data capture method of the above-mentioned multiple FPGAs.
[0045] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute the waveform data capture method of the above-mentioned multiple FPGAs.
[0046] In summary, this application has the following beneficial technical effects:
[0047] When capturing waveform data from multiple FPGAs, the FPGA can accept multiple types of signals, so that the sampling signals are no longer limited to register signals; at the same time, the waveform data returned by the logic side can read multiple bits of data at a time, greatly improving the efficiency of data capture; at the same time, when capturing waveform data, the operation can be paused and the sampling signal can be modified according to the actual situation to reduce the time wasted by running again, thereby achieving the purpose of dynamic adjustment during runtime and greatly improving the flexibility of waveform data capture. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 It is a flow chart of waveform data capture of multiple FPGAs in an embodiment of the present application.
[0049] Figure 2 It is a structural block diagram of waveform data capture of multiple FPGAs in an embodiment of the present application.
[0050] Reference numerals: 201, configuration set generation module; 202, sampling signal query module; 203, signal configuration sending module; 204, configuration file storage module; 205, waveform data reading module; 206, decoding file export module. DETAILED DESCRIPTION
[0051] The following is combined with Figure 1-2 This application is described in further detail.
[0052] The embodiment of the present application discloses a waveform data capture method for multiple FPGAs, which is used to capture waveform data.
[0053] FPGA, the full name of which is Field Programmable Gate Array, is an integrated chip mainly based on digital circuits and a type of programmable logic device (PLD). Waveform data capture refers to the process of capturing and recording waveform data from the circuit or system under test using an oscilloscope or other test equipment.
[0054] Under the relevant technology, the waveform data capture scheme that supports multiple chips is limited in the signals that can be sampled. Only register signals can be sampled, and other signals cannot be sampled. The source of the captured waveform data is single. At the same time, when capturing waveform data, it can only be captured according to the single bit of the sampled signal. The signal is composed of bits. When the signal is composed of multiple bits or multiple signals need to be sampled, the waveform data capture time is long and the efficiency is low.
[0055] Therefore, the present application proposes a waveform data capture method of multiple FPGAs, which uses multiple FPGAs to capture waveform data.
[0056] like Figure 1As shown, the method specifically comprises the following steps:
[0057] S10, reading a signal configuration file containing a signal configuration, extracting the signal configuration and generating a signal configuration set.
[0058] Specifically, signal configuration files refer to files used to define and control signal behavior. These files contain various signal configuration information of the signal, such as signal name, signal parameters, etc. Read the signal configuration file, extract the signal configuration information of each signal from the file, and aggregate all signal configuration information into a signal configuration set.
[0059] S20, when a query instruction of a sampling signal set is received, the sampling signal set includes a sampling signal, and a target signal configuration corresponding to the sampling signal is searched in a signal configuration set according to the sampling signal.
[0060] Specifically, the user summarizes the sampling signals to be queried into a sampling signal set according to the actual situation and sends it to the system. When the system receives the query instruction of the sampling signal set, the sampling signals to be queried may be one or more. According to the characteristic information of the sampling signal, the target signal configuration corresponding to the sampling signal is searched in the signal configuration set, and the signal configurations of all sampling signals are queried and corresponded to the sampling signals one by one.
[0061] S30, sending all the found target signal configurations to the logic side.
[0062] Specifically, after all target signal configurations corresponding to the sampling signal set are queried, the target signal configurations are packaged and sent to the logic side, and the logic side returns the waveform data corresponding to the sampling signal set.
[0063] S40: All the found target signal configurations are stored locally as a sampling signal set configuration file.
[0064] Specifically, all target signal configurations corresponding to the sampling signal set are stored locally as a sampling signal set configuration file, and the sampling signal set configuration file corresponding to the sampling signal set is obtained.
[0065] S50, performing data interaction with the FPGA corresponding to the sampling signal, reading the waveform data returned by the logic side and generating a waveform data set.
[0066] Specifically, the configuration information of the sampling signal includes the FPGA information corresponding to the sampling signal, such as the location information of the sampling signal on the FPGA. The waveform data returned by the logic side is read according to the FPGA information. After reading the waveform data of all sampling signals, a waveform data set is generated.
[0067] S60, writing the waveform data set to a disk as a waveform data file, decoding the waveform data file into a standard viewable format file according to the sampling signal set configuration file, and exporting the standard viewable format file.
[0068] Specifically, the sampled signal data is stored on the local disk and converted into a waveform data file. According to the sampled signal set configuration file, the waveform data file is decoded into a standard viewable format file through a conversion tool. During the decoding process, each signal in the sampled signal set will be mapped to an identifier in the standard viewable format file, and its changes will be recorded in the numerical change area. After decoding, the standard viewable format file will be exported.
[0069] This application uses multiple FPGAs to capture waveform data. FPGA can read other signals besides registers and generate configuration sets in advance, making it more convenient to capture multiple data and reducing the time spent on repeated captures. At the same time, according to the waveform data returned by the FPGA reading logic side corresponding to the sampling signal, multiple bits of data can be read at a time, greatly improving the efficiency of data capture.
[0070] In one embodiment, if the signal configuration required is not fully extracted when extracting the signal configuration, when it comes to capturing waveform data, when relevant information is needed, the problem of re-extraction leading to reduced efficiency may occur. For example, when it is necessary to read the waveform data returned by the logic side according to the FPGA corresponding to the sampled signal, if the FPGA information corresponding to the signal is not extracted, the waveform data reading may encounter difficulties and the efficiency becomes low.
[0071] In order to improve the efficiency of waveform data capture, the extracted signal configuration must at least include the signal name, signal ID, FPGA chip ID, and signal bit information. The signal name and signal ID are the unique identifiers of the signal, the FPGA chip ID is the unique identifier of the FPGA chip, and the signal bit information includes the bits contained in the signal and the position information of the bits in the corresponding FPGA chip. Regarding how to obtain the position information of the bits in the corresponding FPGA chip, specifically, an FPGA will be divided into multiple macros according to the number of signals, each macro contains multiple bits, and the signal configuration also contains the position information of the macro to which the signal belongs. The signal bit information includes the bits contained in the signal and the position information of the bits in the macro. According to the above information, the position information of the bits in the corresponding FPGA chip can be obtained. When extracting the signal configuration, the signal-related information is recorded in the signal configuration, which can be called at any time when needed to avoid searching again and improve the overall operation efficiency.
[0072] In one embodiment, the known information of the sampling signal to be queried includes the sampling signal ID, the sampling signal name, the sampling signal source, etc. In order to accurately query the target signal configuration corresponding to the sampling signal in the signal configuration set, the step of searching the target signal configuration corresponding to the sampling signal in the signal configuration set according to the sampling signal can be specifically performed as follows:
[0073] Search the target signal configuration corresponding to the sampling signal in the signal configuration set according to the sampling signal ID or sampling signal name. Specifically, first, determine the sampling signal ID or sampling signal name of the sampling signal as the query medium, for example, determine the sampling signal ID as the query medium; then, search the sampling signal ID in the signal configuration set. There is only one sampling signal ID in the signal configuration set. After the sampling signal ID is found, the signal configuration corresponding to the sampling signal ID in the signal configuration set is the target signal configuration of the sampling signal. The signal name and signal ID are the unique identifiers of the signal. The target signal configuration can be found in the configuration set accurately and quickly according to the signal name or signal ID.
[0074] In one embodiment, considering that the efficiency of waveform data capture by single bit is low, in order to improve the efficiency of waveform data capture, the steps of reading the waveform data returned by the logic side through the FPGA corresponding to the sampling signal and generating a waveform data set can be specifically performed as follows:
[0075] First, find the corresponding target FPGA chip according to the target FPGA chip ID. Specifically, the FPGA chip ID is the unique identifier of the FPGA chip. If the FPGA chip ID of FPGA chip A is a, then the target FPGA chip A where the sampling signal is located can be accurately found through the target FPGA chip ID: a. Then, create a target Control instance according to the target FPGA. Specifically, the Control instance needs to correspond to the FPGA chip ID one by one, and create Control instance A according to the target FPGA chip A. Next, the target Control instance interacts with the target FPGA chip, reads the waveform data returned by the logic side and generates a waveform data set. Specifically, Control instance A interacts with the target FPGA chip A, reads the waveform data and generates waveform data set a. With the help of the Control instance, multiple bits of data in a certain area on the FPGA chip can be read at one time, which is more efficient.
[0076] In one embodiment, in order to better manage data, the step of creating a target Control instance according to the target FPGA chip can be specifically performed as follows:
[0077] The target Control instance is created and managed according to the target FPGA chip through the Manager module. Specifically, Control instance A of target FPGA chip A needs to be created through the Manager module. When Control instance A needs to be modified, it also needs to be modified through the Manager module. Multiple Control instances are created and managed through the Manager module, so that the data of each Control instance is relatively independent and not easily contaminated by each other.
[0078] In one embodiment, considering that the sampled signal set may be modified, in order to further improve the flexibility of waveform data capture, after the waveform data set is written to the disk as a waveform data file, the following steps may be performed:
[0079] Query whether a sampling signal modification instruction is received. The sampling signal modification instruction includes modification information for the sampling signal. Specifically, the user may need to increase or decrease the sampling signals in the sampling signal set during operation according to actual conditions. In this case, the user will issue a sampling signal modification instruction. The sampling signal modification instruction includes adding or decreasing the sampling signals in the sampling signal set.
[0080] If a modification instruction of the sampling signal is received, the sampling signal set is modified according to the modification information to obtain a new sampling signal set. Specifically, the sampling signal in the sampling signal set is added or reduced according to the modification instruction to obtain the new sampling signal set. Next, a new waveform data set and a new sampling signal set configuration file are generated according to the new sampling signal set, and the new waveform data set is written to the disk as a new waveform data file. Specifically, the new sampling signal set is input into the system, and steps S20-S50 are repeated to obtain a new waveform data set and a new sampling signal set configuration file, and the step of "writing the sampling signal data set to the disk as a waveform data file" is repeated to generate a new waveform data file.
[0081] If no instruction to modify the sampling signal is received, the original sampling signal set configuration file and waveform data file are used. Specifically, the sampling signal set does not need to be modified, the waveform data file remains unchanged, and the next step of decoding can be performed directly.
[0082] It should also be noted that the waveform data file is decoded according to the sampling signal set configuration file, and the position information of the bits contained in the sampling signal set configuration file in the corresponding FPGA chip is used.
[0083] When capturing waveform data, you can pause and modify the sampling signal set at any time, add or reduce sampling signals, and dynamically adjust the sampling signal set during runtime, which greatly improves flexibility and efficiency.
[0084] In one embodiment, in order to facilitate the user to understand the analysis data, the step of decoding the waveform data file into a standard viewable format file according to the sampling signal set configuration file and exporting it can be specifically performed as follows:
[0085] At the end of the simulation, all waveform data files are decoded one by one according to the corresponding sampling signal configuration set file, and the waveforms are merged to generate a standard viewable format file. Specifically, if a modification sampling signal instruction is received, multiple waveform data files need to be decoded, the waveforms are synthesized, and a standard viewable format file is generated; if no modification sampling signal instruction is received, only one waveform data needs to be decoded to generate a standard viewable format file. The standard viewable format file is usually in the form of a VCD format file.
[0086] After the simulation is completed, if there are multiple waveform data files, all waveform data files will be decoded one by one according to the corresponding sampling signal configuration set file. During decoding, the waveforms will be merged to generate a standard viewable format file, which will make it more convenient for users to view the simulation results.
[0087] Based on the above method, the present application also discloses a waveform data capture device for multiple FPGAs. Figure 2 , the device includes the following modules:
[0088] A configuration set generating module 201 is used to read a signal configuration file containing a signal configuration, extract the signal configuration and generate a signal configuration set;
[0089] The sampling signal query module 202 is used for, upon receiving a query instruction of a sampling signal set, the sampling signal set includes a sampling signal, and searching for a target signal configuration corresponding to the sampling signal in a signal configuration set according to the sampling signal;
[0090] The signal configuration sending module 203 is used to send all the found target signal configurations to the logic side;
[0091] The configuration file storage module 204 is used to locally store all the target signal configurations found as a sampling signal set configuration file;
[0092] The waveform data reading module 205 is used to perform data interaction with the FPGA corresponding to the sampling signal, read the waveform data returned by the logic side and generate a waveform data set;
[0093] The decoded file export module 206 is used to store the waveform data set into a disk as a waveform data file, decode the waveform data file into a standard viewable format file according to the sampling signal set configuration file, and export the standard viewable format file.
[0094] In one embodiment, the configuration set generation module 202, the signal configuration specifically includes the signal name, signal ID, FPGA chip ID, and signal bit information. The signal name and signal ID are unique identifiers of the signal, the FPGA chip ID is the unique identifier of the FPGA chip, and the signal bit information includes the bits contained in the signal.
[0095] In one embodiment, the sampled signal query module 202 is specifically configured to search for a target signal configuration corresponding to the sampled signal in the signal configuration set according to the sampled signal ID or the sampled signal name.
[0096] In one embodiment, the waveform data reading module 205 is specifically used to find the corresponding target FPGA chip according to the target FPGA chip ID, and create a target Control instance according to the target FPGA chip; the target Control instance interacts with the target FPGA chip, reads the waveform data returned by the logic side and generates a waveform data set.
[0097] In one embodiment, the waveform data reading module 205 is specifically configured to create and manage a target Control instance according to a target FPGA chip through a Manager module.
[0098] In one embodiment, the decoded file export module 206 is further used to copy the entire encrypted storage table to obtain an encrypted storage copy table; and export the encrypted storage copy table, which contains the decrypted data.
[0099] In one embodiment, the decoding file export module 206 is also used to query whether an instruction to modify the sampling signal is received, and the instruction to modify the sampling signal includes modification information for the sampling signal; if the instruction to modify the sampling signal is received, the sampling signal set is modified according to the modification information to obtain a new sampling signal set; a new waveform data set and a new sampling signal set configuration file are generated according to the new sampling signal set, and the new waveform data set is written to the disk as a new waveform data file; if the instruction to modify the sampling signal is not received, the original sampling signal set configuration file and waveform data file are used.
[0100] In one embodiment, the decoded file export module 206 is also used to decode all waveform data files one by one according to the corresponding sampling signal configuration set files when the simulation is finished, and merge the waveforms to generate a standard viewable format file.
[0101] The embodiment of the present application also discloses a computer device.
[0102] Specifically, the computer device includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute the waveform data capture method of the above-mentioned multiple FPGAs.
[0103] The embodiment of the present application also discloses a computer-readable storage medium.
[0104] Specifically, the computer-readable storage medium stores a computer program that can be loaded by a processor and executes the above-mentioned database static desensitization method. The computer-readable storage medium includes, for example: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.
Claims
1. A waveform data capture method for multiple FPGAs, characterized in that: The method comprises: Reading a signal configuration file containing a signal configuration, extracting the signal configuration and generating a signal configuration set; When a query instruction of a sampling signal set is received, the sampling signal set includes a sampling signal, and a target signal configuration corresponding to the sampling signal is searched in the signal configuration set according to the sampling signal; Sending all the target signal configurations found to the logic side; All the target signal configurations found are stored locally as a sampling signal set configuration file; By performing data interaction with the FPGA corresponding to the sampling signal, the waveform data returned by the logic side is read and a waveform data set is generated; The waveform data set is saved to a disk as a waveform data file, and the waveform data file is decoded into a standard viewable format file according to the sampling signal set configuration file and exported.
2. The method according to claim 1, characterized in that: The signal configuration includes: Signal name, signal ID, FPGA chip ID, signal bit information, the signal name and signal ID are unique identifiers of the signal, the FPGA chip ID is the unique identifier of the FPGA chip, and the signal bit information includes the bits contained in the signal.
3. The method according to claim 1, characterized in that: The sampling signal includes a sampling signal ID or a sampling signal name; The step of searching the signal configuration set for a target signal configuration corresponding to the sampled signal according to the sampled signal comprises: According to the sampling signal ID or the sampling signal name, the target signal configuration corresponding to the sampling signal is searched in the signal configuration set.
4. The method according to claim 1, characterized in that: The target signal configuration includes the target FPGA chip ID corresponding to the sampling signal; The step of performing data interaction with the FPGA corresponding to the sampling signal, reading the waveform data returned by the logic side and generating a waveform data set includes: Find the corresponding target FPGA chip according to the target FPGA chip ID, and create a target Control instance according to the target FPGA chip; The target Control instance exchanges data with the target FPGA chip, reads the waveform data returned by the logic side and generates a waveform data set.
5. The method according to claim 4, characterized in that: The creating a target Control instance according to the target FPGA chip includes: The target Control instance is created and managed according to the target FPGA chip through the Manager module.
6. The method according to claim 1, characterized in that: After the waveform data is stored in a disk as a waveform data file, the method further includes: querying whether a sampling signal modification instruction is received, wherein the sampling signal modification instruction includes modification information for the sampling signal; If the sampling signal modification instruction is received, modifying the sampling signal set according to the modification information to obtain a new sampling signal set; Generate a new waveform data set and a new sampling signal set configuration file according to the new sampling signal set, and save the new waveform data set to a disk as a new waveform data file; If the sampling signal modification instruction is not received, the original sampling signal set configuration file and the waveform data file are used.
7. The method according to claim 6, characterized in that: Decoding the waveform data file into a standard viewable format file and exporting it according to the sampling signal set configuration file comprises: At the end of the simulation, all the waveform data files are decoded one by one according to the corresponding sampling signal configuration set files, and the waveforms are merged to generate a standard viewable format file.
8. A waveform data capture device for multiple FPGAs, characterized in that: The device comprises: A configuration set generation module (201), used for reading a signal configuration file containing a signal configuration, extracting the signal configuration and generating a signal configuration set; A sampling signal query module (202) is used for, upon receiving a query instruction for a sampling signal set, the sampling signal set comprising a sampling signal, searching the signal configuration set for a target signal configuration corresponding to the sampling signal according to the sampling signal; A signal configuration sending module (203), used for sending all the target signal configurations found to the logic side; A configuration file storage module (204), configured to locally store all the target signal configurations found as a sampled signal set configuration file; A waveform data reading module (205), configured to perform data interaction via an FPGA corresponding to the sampling signal, read the waveform data returned by the logic side and generate a waveform data set; The decoded file export module (206) is used to store the waveform data set into a disk as a waveform data file, decode the waveform data file into a standard viewable format file according to the sampling signal set configuration file, and export the standard viewable format file.
9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.