Method for realizing real-time simulation on FPGA (Field Programmable Gate Array) by using fixed-point operation

Abstract

The invention discloses a method for realizing real-time simulation on an FPGA (Field Programmable Gate Array) by using fixed-point operation. The method comprises the following steps: carrying out per-unit processing on a differential equation of a simulated system to obtain a per-unit differential equation; performing discretization processing on the per unit differential equation to obtain a per unit differential equation; converting the per-unit difference equation into corresponding hardware description based on fixed-point operation; and integrating the hardware description, and deploying the hardware description on an FPGA for operation. Therefore, simulated systems with different numerical scales can be converted into a unified numerical scale through per unit, and simulation calculation is realized on the FPGA based on fixed-point operation, so that the cost of real-time simulation is greatly reduced, and the simulation frequency and the simulation precision are improved.

Description

Technical Field

[0001] The present application relates to the field of real-time simulation technology, and in particular to a method for implementing real-time simulation on FPGA using fixed-point operations. Background Art

[0002] In modern real-time simulation systems, FPGA, as a flexible and programmable hardware platform, is widely used in fields that require high-performance, low-latency processing, especially in situations where high-speed real-time simulation is required. FPGA can provide a step size of less than 1 microsecond, making high-speed real-time simulation possible.

[0003] Real-time simulation systems usually require numerical solutions to differential equations to simulate the dynamic behavior of the system. However, traditionally, in order to maintain the versatility of simulations at different numerical scales, existing solutions usually use floating-point operations for numerical solutions. However, implementing floating-point operations on FPGAs consumes a lot of hardware resources, which greatly increases system costs and slows down calculation speed, limiting system performance and cost-effectiveness.

[0004] Fixed-point arithmetic is a more efficient method of numerical representation and calculation. By representing numerical values ​​with integers of fixed bit width, hardware resources can be saved and calculation speed can be increased. Therefore, if fixed-point arithmetic is used for numerical solution, hardware resources can be greatly saved and calculation speed can be increased. However, the numerical range of fixed-point numbers is limited, which makes it difficult to meet the simulation requirements of different numerical scales.

[0005] Therefore, an optimized solution for implementing real-time simulation on FPGA using fixed-point arithmetic is desired.

[0006] Application Contents

[0007] This application content section is provided to introduce the concepts in a brief form, which will be described in detail in the detailed implementation section below. This application content section is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to be used to limit the scope of the technical solution claimed for protection.

[0008] The embodiment of the present application also provides a method for implementing real-time simulation on an FPGA using fixed-point operations, which includes:

[0009] Performing per-unit processing on the differential equation of the simulated system to obtain a per-unit differential equation;

[0010] Discretizing the normalized differential equation to obtain a normalized difference equation;

[0011] Converting the normalized difference equation into a corresponding hardware description based on fixed-point operations; and

[0012] The hardware description is synthesized and deployed to run on FPGA.

[0013] In the above-mentioned method of implementing real-time simulation on FPGA using fixed-point operations, the differential equation of the simulated system is normalized to obtain a normalized differential equation, including: selecting a base value for the variables and constants in the differential equation; dividing the variables and constants by the corresponding base values ​​to obtain corresponding normalized values; and replacing the variables and constants in the differential equation with the corresponding normalized values ​​to obtain the normalized differential equation.

[0014] In the above method for implementing real-time simulation on FPGA using fixed-point operations, the discretization process is any one of the Euler method, the trapezoidal method, the explicit and implicit Runge-Kutta method and the Symplectic algorithm.

[0015] In the above-mentioned method of implementing real-time simulation on FPGA using fixed-point operations, the per-unit differential equation is converted into a corresponding hardware description based on fixed-point operations, including: uploading the per-unit differential equation to a cloud server; on the cloud server, performing equation description segmentation based on variable granularity on the per-unit differential equation to obtain a sequence of equation variables; passing the sequence of equation variables through a variable embedding encoder to obtain a sequence of equation variable embedding coding vectors; semantically encoding the sequence of equation variable embedding coding vectors to obtain equation semantic coding features; generating the hardware description based on the equation semantic coding features, and returning the hardware description to the FPGA.

[0016] In the above-mentioned method of implementing real-time simulation on FPGA using fixed-point operations, the sequence of equation variable embedded coding vectors is semantically encoded to obtain equation semantic coding features, including: passing the sequence of equation variable embedded coding vectors through a semantic encoder based on a converter structure to obtain an equation semantic coding feature vector as the equation semantic coding feature.

[0017] In the above-mentioned method of implementing real-time simulation on FPGA using fixed-point operations, it is characterized in that the sequence of equation variable embedded coding vectors is passed through a semantic encoder based on a converter structure to obtain an equation semantic coding feature vector as the equation semantic coding feature, including: passing the sequence of equation variable embedded coding vectors through the semantic encoder based on a converter structure to obtain multiple equation variable feature vectors; and cascading the multiple equation variable feature vectors to obtain the equation semantic coding feature vector.

[0018] In the above-mentioned method of implementing real-time simulation on FPGA using fixed-point operations, the hardware description is generated based on the equation semantic encoding features, and the hardware description is returned to the FPGA, including: passing the equation semantic encoding feature vector through a hardware description generator based on a generative adversarial network to obtain the hardware description; returning the hardware description to the FPGA.

[0019] In the above-mentioned method of implementing real-time simulation on FPGA using fixed-point operations, the equation semantic encoding feature vector is passed through a hardware description generator based on a generative adversarial network to obtain the hardware description, including: optimizing the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector; passing the optimized equation semantic encoding feature vector through the hardware description generator based on a generative adversarial network to obtain the hardware description.

[0020] The embodiment of the present application provides a method for implementing real-time simulation on FPGA using fixed-point operations, which performs per-unit processing on the differential equation of the simulated system to obtain a per-unit differential equation; discretizes the per-unit differential equation to obtain a per-unit differential equation; converts the per-unit differential equation into a corresponding hardware description based on fixed-point operations; and, after the hardware description is integrated, it is deployed on the FPGA to run. In this way, the simulated system with different numerical scales can be converted to a unified numerical scale through per-unit processing, and then the simulation calculation can be implemented on the FPGA based on fixed-point operations, so as to greatly reduce the cost of real-time simulation and improve the simulation frequency and simulation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0022] Figure 1 A flowchart of a method for implementing real-time simulation on an FPGA using fixed-point operations provided in one embodiment of the present application.

[0023] Figure 2 A flowchart of a method for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application.

[0024] Figure 3 This is a flowchart of the sub-steps of step 130 in the method for implementing real-time simulation on FPGA using fixed-point operations provided in another embodiment of the present application.

[0025] Figure 4 A block diagram of a system for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application.

[0026] Figure 5 The present invention is a block diagram of an electronic device according to an exemplary embodiment of the present application.

[0027] Figure 6 This is an application scenario diagram of a method for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present application more clear, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but are not intended to limit the present application.

[0029] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0030] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. Meanwhile, other operations may also be added to these processes, or a certain step or several steps of operations may be removed from these processes.

[0031] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0033] It should be understood that in real-time simulation systems, high-speed (step length less than 1us) real-time simulation is usually implemented on a Field Programmable Gate Array (FPGA). In order to maintain the versatility of simulations of different numerical scales, existing solutions usually use floating-point operations for numerical solutions, but implementing floating-point operations on FPGAs consumes a lot of hardware resources, resulting in a significant increase in system costs and slow calculation speeds. On the other hand, if fixed-point operations are used for numerical solutions, hardware resources can be greatly saved and the calculation speed can be accelerated, but the range of values ​​that can be represented by fixed-point operations is limited, and it is difficult to apply simulation requirements of different numerical scales.

[0034] In order to solve the above problems, a method for implementing real-time simulation on FPGA using fixed-point operations is provided in the present application, which performs per-unit processing on the differential equation of the simulated system to obtain a per-unit differential equation; discretizes the per-unit differential equation to obtain a per-unit differential equation; converts the per-unit differential equation into a corresponding hardware description based on fixed-point operations; and deploys the hardware description after synthesis on the FPGA for operation. In this way, the simulated system of different numerical scales can be converted to a unified numerical scale through per-unit processing, and then the simulation calculation can be implemented on the FPGA based on fixed-point operations, so as to greatly reduce the cost of real-time simulation and improve the simulation frequency and simulation accuracy.

[0035] In one embodiment of the present application, a method for implementing real-time simulation on an FPGA using fixed-point operations is provided, which includes: normalizing the differential equations of the simulated system; discretizing the normalized differential equations to form normalized difference equations; converting the normalized difference equations into corresponding hardware descriptions based on fixed-point operations; and synthesizing the hardware descriptions and deploying them on the FPGA for execution.

[0036] according to Figure 1 As shown in (a), in the design stage, the differential equation of the simulated system is first established. In the synchronous rotating dq coordinate system, the differential equation of the non-salient pole permanent magnet synchronous motor is:

[0037]

[0038] Among them, i d and i q is the stator current in the dq coordinate system, μ d and μ q is the stator voltage in the dq coordinate system, ω is the rotor electromagnetic angular velocity, is the permanent magnet flux, R and L are the stator resistance and stator inductance respectively, and t is the time.

[0039] Then, the differential equation is normalized. The normalization of the differential equation can be achieved by the following steps: selecting a base value for the quantity (including variables and constants) in the differential equation, dividing the quantity by the corresponding base value to obtain the corresponding normalized value, and writing the normalized differential equation in the form of the quantity in normalized value form.

[0040] Specifically, a base value as defined in Table 1 is selected, and the amount is divided by the corresponding base value to obtain the per-unit value, wherein the base value is denoted by the subscript base and the per-unit value is denoted by the subscript pu.

[0041] Table 1: Base and per unit values ​​of variables and parameters of differential equations for non-salient pole permanent magnet synchronous motors

[0042]

[0043]

[0044] Based on the per-unit values ​​defined in the table above, write the per-unit differential equation to complete the per-unit differential equation:

[0045]

[0046] Then, the normalized differential equation is discretized to form a normalized difference equation, wherein the discretization can adopt numerical calculation methods including Euler method, trapezoidal method, explicit and implicit Runge-Kutta method and Symplectic algorithm.

[0047] In a specific embodiment of the present application, the forward Euler method is used to select h pu Discretize (2) with step size, and obtain the normalized difference equation as follows:

[0048]

[0049] in,

[0050]

[0051] Then, the normalized differential equation is converted into a corresponding hardware description based on fixed-point operations, wherein the hardware description can be implemented by different hardware description languages ​​and high-level languages, including but not limited to VHDL, Verilog and High-Level Synthesis (HLS).

[0052] In a specific embodiment of the present application, fixed-point numbers are used to represent the quantities in (3), and fixed-point operations are used to represent the operations between the quantities in (3), and the quantities and operations are described using a hardware description language.

[0053] Finally, the hardware description is synthesized and deployed on the FPGA to complete the (a) design step.

[0054] In the operation phase (b), u d and u q is the input signal, with ω, R and L are parameters, i d and i q is the output signal. d ,u q ,ω, R and L are divided by the corresponding base values ​​in Table 1 to achieve per-unit conversion. After obtaining the corresponding per-unit values, they are passed to the FPGA to complete the calculation corresponding to (3) using fixed-point operations to obtain the per-unit value i of the output signal. dpu and i qpu . will i dpu i dpu and i qpu Multiply by the corresponding base value in Table 1 to achieve de-normalization and obtain the output signal i d and i q When it is deployed and run on FPGA, the input signal and parameters are normalized and then passed to FPGA for calculation, and the calculation result is denormalized to generate output signal.

[0055] In a specific embodiment of the present application, the normalization of the input signal and the parameter can be achieved by dividing the input signal and the parameter by the corresponding base value, and the de-normalization of the output signal can be achieved by multiplying the corresponding base value. In another specific embodiment of the present application, the normalization of the input signal and the parameter can also be achieved by multiplying the input signal and the parameter by the reciprocal of the corresponding base value. In another embodiment of the present application, the normalization of the input signal and the parameter, and the de-normalization of the output signal can be implemented on an FPGA, or on other computing units (such as a CPU) outside the FPGA.

[0056] It should be understood that the above-mentioned method of using fixed-point operations to implement real-time simulation on FPGA can be applied in electronic systems, electrical systems, mechanical systems, hydraulic systems, pneumatic systems and control systems.

[0057] The solution disclosed in this application converts the simulated systems of different numerical scales into a unified numerical scale through normalization, and then implements simulation calculation on FPGA based on fixed-point operation. Compared with the traditional floating-point operation solution, this solution can greatly reduce the cost of real-time simulation and improve the simulation frequency and simulation accuracy.

[0058] Furthermore, in another embodiment of the present application, a method for implementing real-time simulation on FPGA using fixed-point operations is provided. Figure 2 This is a flow chart of a method for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application. Figure 2As shown, the method for implementing real-time simulation on FPGA using fixed-point operations according to an embodiment of the present application includes: 110, normalizing the differential equation of the simulated system to obtain a normalized differential equation; 120, discretizing the normalized differential equation to obtain a normalized difference equation; 130, converting the normalized difference equation into a corresponding hardware description based on fixed-point operations; and, 140, synthesizing the hardware description and deploying it on FPGA for operation. The discretization process is any one of the Euler method, the trapezoidal method, the explicit and implicit Runge-Kutta method, and the Symplectic algorithm.

[0059] This real-time simulation method can convert the simulated systems of different numerical scales into a unified numerical scale through normalization, and then realize the simulation calculation on FPGA based on fixed-point operation. Compared with the traditional calculation scheme, this scheme can greatly reduce the cost of real-time simulation and improve the simulation frequency and simulation accuracy.

[0060] It should be understood that FPGA is a programmable logic device. By converting the algorithm or logic function description into a hardware description, a specific function can be implemented on the FPGA. Therefore, it is necessary to convert the normalized differential equation into a hardware description so as to implement the simulation algorithm as a hardware circuit, thereby performing real-time simulation on the FPGA. However, implementing floating-point operations on FPGA requires a large amount of hardware resources, including multipliers, adders, etc., while fixed-point operations can be implemented through simple shift and addition operations, which greatly saves hardware resources. Based on this, it is very important to convert the normalized differential equation into a corresponding hardware description based on fixed-point operations, which can improve the hardware resource utilization and calculation speed of the system, realize high-speed real-time simulation, and reduce the cost of the system.

[0061] Figure 3 This is a flowchart of the sub-steps of step 130 in the method for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application. Figure 3 As shown, 130, based on fixed-point operations, the normalized differential equation is converted into a corresponding hardware description, including: 131, uploading the normalized differential equation to a cloud server; 132, on the cloud server, performing equation description segmentation based on variable granularity on the normalized differential equation to obtain a sequence of equation variables; 133, passing the sequence of equation variables through a variable embedding encoder to obtain a sequence of equation variable embedding coding vectors; 134, performing semantic coding on the sequence of equation variable embedding coding vectors to obtain equation semantic coding features; 135, based on the equation semantic coding features, generating the hardware description, and returning the hardware description to the FPGA.

[0062] Specifically, in the technical solution of the present application, in the process of converting the normalized differential equation into the corresponding hardware description, first, the normalized differential equation is uploaded to the cloud server. Next, considering that there are many variables in the normalized differential equation, the different granularities and correlations of these variables determine the implementation and operation of the hardware. Therefore, in order to be able to convert the equation into a hardware description, so as to implement the hardware function on the FPGA, in the technical solution of the present application, it is necessary to perform the equation description segmentation based on the variable granularity on the cloud server to obtain a sequence of equation variables. It should be understood that the equation segmentation method can decompose the normalized differential equation into multiple variables to realize the parallel processing of different variables in the equation, and capture the semantic association relationship between the variables at the same time, so as to generate a more accurate hardware description based on the semantic association between the equation variables, and improve the calculation efficiency and speed up the processing speed.

[0063] Then, considering that there is a mutual correlation between each equation variable in the sequence of equation variables, therefore, in order to be able to extract important features and correlations between variables, in the technical solution of the present application, the sequence of equation variables is passed through a variable embedding encoder to obtain a sequence of equation variable embedding coding vectors. It should be understood that the variable embedding encoder can learn the nonlinear relationship and complex pattern between equation variables, and embed different variables into a common space to better extract valuable feature information and improve the accuracy and robustness of subsequent hardware description generation and simulation. At the same time, the variable embedding encoder can provide interpretability of variable relationships in the embedding space. By analyzing the equation variable embedding coding vector, the similarities and differences between different variables can be understood, which is helpful for analyzing and interpreting the simulation results.

[0064] Furthermore, since there are equation-based semantic association features between the embedded coding features of different equation variables after embedded coding, in order to extract the semantic information and logical relationships contained in the different variables in the equation, and further improve the accuracy and interpretability of hardware description generation and simulation, in the technical solution of the present application, the sequence of the equation variable embedding coding vectors is passed through a semantic encoder based on a converter structure to obtain an equation semantic coding feature vector. It should be understood that the converter structure has a powerful long-range dependency modeling capability and can capture dependencies between different equation variables across longer distances. Through long-range dependency modeling, the overall structure and meaning of the equation can be better understood. Not only that, the attention mechanism in the converter structure can automatically learn the importance between equation variables and focus on the variables most relevant to the current task to improve the efficiency and accuracy of semantic coding.

[0065] In a specific embodiment of the present application, the sequence of equation variable embedded coding vectors is semantically encoded to obtain equation semantic coding features, including: passing the sequence of equation variable embedded coding vectors through a semantic encoder based on a converter structure to obtain an equation semantic coding feature vector as the equation semantic coding feature.

[0066] Furthermore, the sequence of equation variable embedding coding vectors is passed through a semantic encoder based on a converter structure to obtain an equation semantic coding feature vector as the equation semantic coding feature, including: passing the sequence of equation variable embedding coding vectors through the semantic encoder based on a converter structure to obtain multiple equation variable feature vectors; and, cascading the multiple equation variable feature vectors to obtain the equation semantic coding feature vector.

[0067] Then, the equation semantic encoding feature vector is passed through a hardware description generator based on a generative adversarial network to obtain the hardware description. That is, the hardware description generator based on the generative adversarial network can efficiently generate a hardware description that meets specific performance and resource constraints based on the long-distance semantic association features of the normalized difference equation, and return the hardware description to the FPGA. In this way, customized hardware can be efficiently generated on the FPGA based on fixed-point operations, while shortening development time and improving simulation quality.

[0068] In a specific embodiment of the present application, the hardware description is generated based on the equation semantic encoding features, and the hardware description is returned to the FPGA, including: passing the equation semantic encoding feature vector through a hardware description generator based on a generative adversarial network to obtain the hardware description; and returning the hardware description to the FPGA.

[0069] Furthermore, the equation semantic encoding feature vector is passed through a hardware description generator based on a generative adversarial network to obtain the hardware description, including: optimizing the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector; passing the optimized equation semantic encoding feature vector through the hardware description generator based on a generative adversarial network to obtain the hardware description.

[0070] In the above technical solution, the sequence of equation variable embedding coding vectors expresses the embedded semantic coding representation of the equation variables. In this way, after the sequence of equation variable embedding coding vectors passes through a semantic encoder based on a converter structure, context association can be further performed based on the embedded coding representation context between variables, thereby obtaining an equation semantic coding feature vector for expressing the global semantics of the normalized difference equation. However, considering the differences in the encoding semantic representations of each equation variable based on the variable granularity, although the distribution correlation between local semantic distributions is improved through context association, there are still explicit distribution differences between local semantic distributions, which leads to the discreteness of the local feature distribution of the equation semantic coding feature vector obtained by aggregating the context global semantic association representation corresponding to the sequence of equation variable embedding coding vectors, which leads to poor iterative consistency in the convergence of the equation semantic coding feature vector through the hardware description generator based on the adversarial generative network to the probability mapping of the text semantic space domain of the hardware description, thereby reducing the quality of the generated results.

[0071] Based on this, the present application optimizes the equation semantic coding feature vector to obtain an optimized equation semantic coding feature vector, including: for the first eigenvalue v of the equation semantic coding feature vector i and the second eigenvalue v j , calculate the absolute value of the difference divided by the sum of the absolute values ​​and then correct the relative probability value, wherein the correction makes the relative probability value greater than zero and less than one; calculate the first product of the first eigenvalue multiplied by the relative probability value, the second product of the second eigenvalue multiplied by the absolute value of the difference between the relative probability value and one, the first quotient of the first eigenvalue divided by the absolute value of the difference between the relative probability value and one, and the second quotient of the second eigenvalue divided by the relative probability value; after adding the first product and the second product, further subtract the difference between the first quotient and the second quotient to obtain the first eigenvalue v i and the second eigenvalue v j The corresponding eigenvalue m of the corresponding optimization matrix i,j ; and, multiplying the optimization matrix with the equation semantic encoding feature vector to obtain an optimized equation semantic encoding feature vector.

[0072] Specifically, it is expressed as:

[0073]

[0074] m i,j ∈M,v i ∈V,v j(j≠i) ∈V

[0075]

[0076] Where V represents the semantic encoding feature vector of the equation, v i and v j denote the first eigenvalue and the second eigenvalue of the semantically encoded eigenvector of the equation, respectively, i,j Represents the relative probability value, m i,j Represents the first eigenvalue v i and the second eigenvalue v j The corresponding eigenvalue of the optimization matrix, M, represents the first eigenvalue v i and the second eigenvalue v j The corresponding optimization matrix is, represents matrix multiplication, V′ represents the optimized equation semantic encoding feature vector;

[0077] Among them, the first eigenvalue v i and the second eigenvalue v j The corresponding relative probability value p i,j It is expressed as:

[0078]

[0079] Among them, v i and v j denote the first eigenvalue and the second eigenvalue of the semantically encoded feature vector of the equation, ε denotes a predetermined hyperparameter, and p i,j Represents the relative probability value.

[0080] Here, for the region-boundary integral relationship of the high-dimensional feature manifold of the equation semantic encoding feature vector, by defining the probability distribution of the feature set of the equation semantic encoding feature vector as a manifold constraint boundary, the high-dimensional manifold of the feature set of the equation semantic encoding feature vector, which is composed of eigenvalue pairs, is approximated to avoid the mapping ambiguity of the diversified feature representation of the equation semantic encoding feature vector to the local manifold representation in the high-dimensional feature generative regression convergence space, and improve the execution iteration consistency of each local feature distribution in the mapping task, so as to improve the convergence effect of the feature generative regression and improve the text quality of the obtained hardware description. In this way, the simulated system of different numerical scales can be converted to a unified numerical scale through normalization, and then the simulation calculation can be realized on the FPGA based on fixed-point operation. In this way, customized hardware can be efficiently generated, while shortening the development time and improving the simulation quality.

[0081] In summary, the method of using fixed-point operations to implement real-time simulation on FPGA based on the embodiment of the present application is explained. Based on fixed-point operations, the normalized differential equation is converted into a corresponding hardware description, which can improve the system's hardware resource utilization and calculation speed, realize high-speed real-time simulation, and reduce the cost of the system.

[0082] In one embodiment of the present application, Figure 4 FIG. 1 is a block diagram of a system for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application. Figure 4 As shown, a system 200 for implementing real-time simulation on an FPGA using fixed-point operations according to an embodiment of the present application includes: a per-unit processing module 210, which is used to per-unit process the differential equations of the simulated system to obtain per-unit differential equations; a discretization processing module 220, which is used to discretize the per-unit differential equations to obtain per-unit differential equations; a fixed-point operation module 230, which is used to convert the per-unit differential equations into corresponding hardware descriptions based on fixed-point operations; and an FPGA operation module 240, which is used to deploy the hardware description on the FPGA for operation after synthesis.

[0083] Here, those skilled in the art will appreciate that the specific functions and operations of the various units and modules in the system for implementing real-time simulation using fixed-point operations on FPGA have been described in the above reference. Figures 1 to 3 It has been described in detail in the description of the method of implementing real-time simulation on FPGA using fixed-point operation, and therefore, its repeated description will be omitted.

[0084] As described above, the system 200 for implementing real-time simulation on FPGA using fixed-point operations according to the embodiment of the present application can be implemented in various terminal devices, such as a server for implementing real-time simulation on FPGA using fixed-point operations. In one example, the system 200 for implementing real-time simulation on FPGA using fixed-point operations according to the embodiment of the present application can be integrated into the terminal device as a software module and / or a hardware module. For example, the system 200 for implementing real-time simulation on FPGA using fixed-point operations can be a software module in the operating system of the terminal device, or can be an application developed for the terminal device; of course, the system 200 for implementing real-time simulation on FPGA using fixed-point operations can also be one of the many hardware modules of the terminal device.

[0085] Alternatively, in another example, the system 200 for implementing real-time simulation on an FPGA using fixed-point operations and the terminal device may be separate devices, and the system 200 for implementing real-time simulation on an FPGA using fixed-point operations may be connected to the terminal device via a wired and / or wireless network and transmit interactive information in accordance with an agreed data format.

[0086] Reference below Figure 5, which shows a schematic diagram of the structure of an electronic device 600 suitable for implementing the embodiment of the present disclosure. The terminal device in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0087] like Figure 5 As shown, the electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0088] Typically, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 5 The electronic device 600 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0089] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 609, or installed from the storage device 608, or installed from the ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0090] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0091] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0092] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0093] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0094] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0095] The modules involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a module does not limit the module itself in some cases. For example, a test parameter acquisition module may also be described as a "module for acquiring device test parameters corresponding to a target device".

[0096] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0097] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0098] Figure 6 This is an application scenario diagram of a method for implementing real-time simulation on an FPGA using fixed-point operations provided in another embodiment of the present application. Figure 6 As shown, in this application scenario, first, the normalized difference equation (for example, Figure 6 C) is uploaded to the cloud server; then, the obtained normalized differential equation is input to a server (for example, Figure 6 In S) shown in , the server is capable of processing the normalized differential equation based on a real-time simulation algorithm implemented on the FPGA using fixed-point operations to generate the hardware description and return the hardware description to the FPGA.

[0099] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for implementing real-time simulation on FPGA using fixed-point arithmetic, characterized in that: include: Performing per-unit processing on the differential equation of the simulated system to obtain a per-unit differential equation; Discretizing the normalized differential equation to obtain a normalized difference equation; Converting the normalized difference equation into a corresponding hardware description based on fixed-point arithmetic; and The hardware description is synthesized and deployed to run on FPGA.

2. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 1, characterized in that: The differential equation of the simulated system is normalized to obtain a normalized differential equation, including: selecting basis values ​​for variables and constants in the differential equation; Dividing the variables and constants by the corresponding base values ​​to obtain corresponding per-unit values; and The variables and constants in the differential equation are replaced with corresponding per-unit values ​​to obtain the normalized differential equation.

3. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 2, characterized in that: The discretization process is any one of the Euler method, the trapezoidal method, the explicit and implicit Runge-Kutta method and the Symplectic algorithm.

4. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 3, characterized in that: The normalized difference equation is converted into a corresponding hardware description based on fixed-point operations, including: Uploading the normalized difference equation to a cloud server; On the cloud server, performing equation description segmentation based on variable granularity on the normalized difference equation to obtain a sequence of equation variables; Passing the sequence of equation variables through a variable embedding encoder to obtain a sequence of equation variable embedding encoding vectors; Performing semantic encoding on the sequence of the equation variable embedding coding vectors to obtain equation semantic coding features; Based on the semantic encoding features of the equation, the hardware description is generated, and the hardware description is returned to the FPGA.

5. The method for implementing real-time simulation on FPGA using fixed-point operations according to claim 4, characterized in that: The sequence of equation variable embedding coding vectors is semantically encoded to obtain equation semantic coding features, including: passing the sequence of equation variable embedding coding vectors through a semantic encoder based on a converter structure to obtain an equation semantic coding feature vector as the equation semantic coding feature.

6. The method for implementing real-time simulation on FPGA using fixed-point arithmetic according to claim 5, characterized in that: The sequence of the equation variable embedding coding vectors is passed through a semantic encoder based on a transformer structure to obtain an equation semantic coding feature vector as the equation semantic coding feature, including: Passing the sequence of equation variable embedding encoding vectors through the semantic encoder based on the transformer structure to obtain a plurality of equation variable feature vectors; and The multiple equation variable feature vectors are concatenated to obtain the equation semantic encoding feature vector.

7. The method for implementing real-time simulation on FPGA using fixed-point operations according to claim 6, characterized in that: Generating the hardware description based on the semantic encoding feature of the equation, and returning the hardware description to the FPGA, including: Passing the equation semantic encoding feature vector through a hardware description generator based on a generative adversarial network to obtain the hardware description; The hardware description is returned to the FPGA.

8. The method for implementing real-time simulation on FPGA using fixed-point operations according to claim 7, characterized in that: The equation semantic encoding feature vector is passed through a hardware description generator based on a generative adversarial network to obtain the hardware description, including: Optimizing the equation semantic coding feature vector to obtain an optimized equation semantic coding feature vector; The optimized equation semantic encoding feature vector is passed through the hardware description generator based on the generative adversarial network to obtain the hardware description.

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