AMS circuit automatic design method using large language model

Abstract

The invention relates to the field of electronic design automation (EDA), and provides an AMS circuit automatic design method using a large language model. The method aims at solving the problem that an existing AMS circuit design is insufficient in automation degree, and mainly comprises the steps that a schematic circuit diagram and text description are extracted from literatures, and a data set containing the schematic circuit diagram, a netlist and annotation information is constructed; performing connectivity detection on the schematic circuit diagram, and extracting a netlist; carrying out annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; obtaining a design strategy by using a large language model, and describing a circuit architecture; according to the design strategy and the local annotation, relevant circuits and test platforms are retrieved, a complete circuit topology is assembled, and simulation is carried out; size optimization is carried out based on constraints, and a Bayesian optimization algorithm is used for solving; and if the initial topological structure cannot meet the performance target, carrying out topological reconstruction. According to the invention, the automation level and efficiency of analog and mixed signal circuit design are improved.

Description

Technical Field

[0001] The invention relates to the field of automatic AMS circuit design and provides an automatic AMS circuit design method using a large language model. Background Art

[0002] Digital circuit synthesis technology has been widely used in the field of electronic design automation (EDA), enabling modern large-scale digital integrated circuits (ICs) to comply with Moore's Law. However, the degree of automation in analog and mixed-signal (AMS) circuit design lags significantly behind digital circuit design. Currently, AMS circuits are mainly designed in a full-custom manner, and the design process still relies heavily on human experts to determine circuit topology and component size. This time-consuming and labor-intensive design process significantly limits the scalability of AMS circuits.

[0003] Large language models (LLMs) have recently shown great potential in solving various electronic design automation (EDA) challenges, providing new possibilities for the automated design of analog and mixed-signal (AMS) circuits. Artisian uses LLMs to automatically design AMS circuits, but the method they proposed is only applicable to operational amplifier circuits and cannot be directly generalized to other types of circuits. The method has poor versatility. The poor versatility mainly refers to the limitations of the large language model (LLM) used by Artisian in the automated design of analog and mixed-signal (AMS) circuits. Specifically, the poor versatility of this method is reflected in the following aspects:

[0004] Specific circuit type restrictions: Artisian's method is mainly aimed at operational amplifier circuit design, which limits its scope of application. Since different AMS circuit types have different design requirements and performance indicators, this method cannot be directly applied to other types of circuits, such as comparators, filters, etc.

[0005] Limitations of behavioral design: This method can only generate behavioral circuits, that is, it describes the behavior of the circuit at a higher level, but cannot be directly converted into accurate circuits at the transistor level. In practical applications, behavioral circuits need to be further converted into transistor-level circuits. This conversion process may lead to an increase in the number of transistors, thereby reducing design efficiency.

[0006] Parameter design limitations: Artisian's method only provides circuit topology, but does not include the design of key parameters such as transistor size. In actual AMS circuit design, transistor size has an important impact on circuit performance, so the lack of this key step will limit the practical application of the design solution.

[0007] Lack of generalization: Since the method relies on a specific type of circuit and design requirements, its generalization ability is limited when faced with new or different design scenarios. This means that the method cannot be easily adapted and optimized for other types of AMS circuit designs.

[0008] In summary, the limitations of Artisian's method in terms of versatility, design efficiency and parameter design limit its application in the field of automatic design of analog and mixed-signal circuits. Summary of the invention

[0009] The purpose of the present invention is to solve the problem that the prior art only provides a behavioral-level operational amplifier circuit, and the behavioral-level circuit is modeled to a transistor-level circuit, which will cause the number of transistors to exceed the circuit directly designed at the transistor level, resulting in low design efficiency.

[0010] The technical solution adopted by the present invention to solve the above technical problems is:

[0011] An AMS circuit automatic design method using a large language model comprises the following steps:

[0012] Step 1: Extract the circuit schematic diagram and text description from the original document to obtain the circuit schematic diagram, netlist and annotation information for constructing the AMSnet-KG knowledge graph;

[0013] The steps in step 1 include:

[0014] Step 1.1: Collect raw data from textbooks and academic papers, including circuit schematics and text descriptions, to provide the basis for the dataset.

[0015] Step 1.2: Use a semi-supervised learning method to extract circuit schematics. Specifically, the schematics are labeled on a subset of page images, and a target detection model is trained to identify and extract all circuit schematics on the remaining pages.

[0016] Step 1.3, using the uniformity of the schematics printed in the literature for template matching, manually annotate one copy of each component type, and quickly identify other identical components through template matching;

[0017] Step 1.4, label each direction of each component category, including direction information for determining component connections;

[0018] Step 1.5: Use the template matching data to train the model and apply it to annotate the remaining circuit schematics for extraction;

[0019] Step 1.6: Manually evaluate the recall rate of component and symbol detection results to ensure that the recall rate meets the threshold requirement, and obtain the position labels and category labels of all components in the circuit schematic;

[0020] Step 1.7: Output a dataset containing circuit schematics, netlists, and annotation information for building the AMSnet-KG knowledge graph.

[0021] Step 2: Perform connectivity detection on the circuit schematic to obtain a netlist;

[0022] The steps in step 2 include:

[0023] Step 2.1, perform component identification processing on the circuit schematic diagram to obtain component annotations;

[0024] Step 2.2, perform network cable identification processing on the component annotation to obtain a netlist;

[0025] Step 2.2.1: Traverse each component label in the circuit schematic to identify the connection relationship between the components.

[0026] Step 2.2.2, classify the wires in the schematic diagram according to the preset wire identification rules. The wire identification rules are that all wires are represented by solid lines, and wires that intersect but have no intersection are not considered connected;

[0027] Step 2.2.3: Perform an extended search on the wire pixels around each component until other components or boundaries are encountered to form a component cluster.

[0028] Step 2.2.4: Analyze each component cluster to determine its connectivity:

[0029] Step 2.2.4.1. If the cluster contains only the starting component, mark it as no connectivity detected.

[0030] Step 2.2.4.2. If the cluster contains exactly two components, mark these two components as connected.

[0031] Step 2.2.4.3. If the cluster contains an odd number of components, and it is greater than two, mark the circuit diagram as abnormal and require manual inspection.

[0032] Step 2.2.4.4. If the cluster contains an even number of components, and it is greater than two, assume that the circuit diagram has no missing nodes and the intersecting wires are not connected.

[0033] Step 2.2.5: Apply 2D convolution to the searched wires to locate the intersection. The convolution kernel dimension is adjusted according to the line thickness and layout.

[0034] Step 2.2.6, regard the index of the maximum pixel density near the intersection as the intersection point, and add it to the component annotation;

[0035] Step 2.2.7, repeat the grouping process, connect each component in the grouping to the intersection, and eliminate the four-component cluster;

[0036] Step 2.2.8: If the number of components in a group exceeds four, reduce it by two each iteration until only two components remain in each group;

[0037] Step 2.2.9, rearrange the relative connections, delete the intersections, and complete the network cable identification process.

[0038] Step 2.2.10. For some components, correctly order the connections according to the SPICE netlist format requirements. For example, the connections of a four-terminal MOSFET must follow the order of drain, gate, source, and body / substrate.

[0039] Step 2.2.11. For the component, use the orientation markings on the bounding box to determine an angle range for each connection.

[0040] Step 2.2.12. For the symbol, use MLLM to determine the function of each pin;

[0041] Step 2.2.13. Manually verify the quality of the network cable marking process to ensure an accuracy rate of 96%, and manually correct erroneous results to ensure data quality;

[0042] Step 2.2.14. Output a netlist containing circuit components, symbols, and nets.

[0043] Step 3, annotate the circuit schematic and netlist to obtain annotation information;

[0044] The steps in step 3 include:

[0045] Step 3.1: Manually annotate the circuit schematic and netlist to obtain local annotations. The specific operations include:

[0046] Label each component in the circuit schematic, including identifying the network wires as input, bias, and output;

[0047] Labeling groups of components, such as identifying a group of components as a building block, including a current mirror or a differential pair;

[0048] Dimensioning constraints, marking certain sets of components to follow symmetry constraints such as length and width;

[0049] Label the nets that connect the circuit's pins to the testbench;

[0050] Step 3.2: Perform MLLM generation processing on the circuit schematic and netlist to obtain global annotations. The operations include:

[0051] The qualitative descriptions are summarized into key-value pairs using a multilingual large language model (MLLM), including: {gain: high} or {load: current mirror};

[0052] Generate JSON files to introduce more structure in annotation information;

[0053] Merge equivalent annotations to simplify the data retrieval process and reduce the amount of data to form a knowledge graph;

[0054] Step 3.5: Utilize the circuit diagram and context description information originally obtained from the literature, combine the circuit diagram image, and obtain the local annotations and global annotations to annotate each circuit, and output the circuit schematic, netlist, and annotation information containing complete circuit design information.

[0055] Step 4: construct a knowledge graph for the circuit schematic, netlist, and annotation information to obtain AMSnet-KG;

[0056] The steps in step 4 include:

[0057] Step 4.1, perform entity relationship definition processing on the circuit schematic, netlist and annotation information to obtain the knowledge graph structure;

[0058] Step 4.1.1. Entity definition

[0059] Define entities as strings or circuits;

[0060] String entities are used to represent circuit components, test platforms, etc., such as "NMOS", "PMOS", or circuit structure functions.

[0061] The circuit entity is used to represent the complete circuit topology, including information such as schematic diagram, netlist, local annotation and global annotation.

[0062] Step 1.4.2: Relationship Definition

[0063] Relationships are used to connect entities to form a graph structure;

[0064] The relationship type can be a string, such as "connects", "contains", "drives", etc.

[0065] The start and end points of a relationship are entities, such as "M1 is connected to M2" or "Comparator contains NMOS".

[0066] Step 1.4.4: Triplet construction

[0067] The basic building block in the graph is the "entity-relationship-entity" relationship query triple.

[0068] Triples are used to represent the relationship between entities, for example, “M1 is connected to M2” can be represented as a triple (“M1”, “connected”, “M2”).

[0069] Step 1.4.5: Merge equivalent annotations

[0070] Merge equivalent annotations into a knowledge graph for efficient retrieval.

[0071] For example, multiple circuits may use the same bias circuit. The bias circuit annotations of these circuits can be merged into one entity and a relationship can be established, such as "M1 contains the bias circuit."

[0072] Step 1.4.6: Knowledge graph retrieval * Use triples to search in the knowledge graph, for example: * Retrieve all circuits using differential pairs: MATCH(node: circuit{input:'Differential pair'}) RETURN node * Retrieve all circuits using current mirrors as loads: MATCH(node: circuit{load:'Current mirror'}) RETURN node * Use Cypher or other graph database query languages ​​for retrieval.

[0073] Step 4.2: Perform database storage processing on the knowledge graph structure to obtain AMSnet-KG:

[0074] Step 5. Select the topology through KG-RAG

[0075] Using performance specifications as input, the large language model (LLM) is used to obtain design strategies, describe circuit architecture, convert design strategies into relational query triples, use the triples to retrieve related circuits and test platforms in the knowledge graph, use local annotations to assemble the retrieved circuit components and test platforms into a complete circuit topology, and perform simulation.

[0076] Step 5.1: Convert performance specifications into relational query triples.

[0077] Step 5.2: Use matching query in the knowledge graph to retrieve relevant circuits and test platforms.

[0078] Step 5.3: According to the local annotation, the retrieved circuit components and test platform are assembled into a complete circuit topology.

[0079] Step 5.4: Use Cadence's Spectre circuit simulator to simulate the assembled circuit topology.

[0080] Step 6: Constraint-based size optimization

[0081] Formulate the size optimization problem as a black-box optimization problem and solve it using Bayesian optimization (BO). Use local annotations as constraints to reduce the parameter search space. Use expert insights, such as parameter sharing constraints, to further refine the search space. Use the Bayesian optimization algorithm to select the next sampling point and update the surrogate model. Repeat the steps until the performance goal or the iteration limit is reached.

[0082] Step 6.1, the size optimization problem is formulated as a black box optimization problem and solved using Bayesian optimization (BO). The goal is to minimize the difference between the performance index of the circuit design and the performance limit to optimize the circuit performance. The objective function is defined as the weighted square sum of the performance index, as shown below:

[0083]

[0084] where f i (x) represents the performance index of the ith simulation, and N represents the number of performance indexes;

[0085] is a performance limit, after which no additional performance points will be awarded.

[0086] and is the normalization factor obtained by the initial random sample set,

[0087] w i is the weight of the importance control item of each performance indicator.

[0088] Step 6.2: Use local annotations as constraints

[0089] The local annotation information retrieved by AMSnet-KG is used as constraints to reduce the parameter search space and improve the optimization efficiency. The transistor parameter set specified according to the local annotation should maintain equality or a certain ratio, and the number of parameters is reduced accordingly.

[0090] Step 6.2.1, define the local annotation as the prior knowledge of the parameter, such as the value range of the parameter;

[0091] Step 6.2.2: Update the prior distribution of parameters based on local annotations, thereby limiting the search space of parameters;

[0092] Step 6.3: Introducing expert knowledge

[0093] Using expert knowledge, such as parameter sharing constraints, further refines the search space and guides the optimization process. An exhaustive search of all transistor parameters is inefficient, so we use expert knowledge as constraints on the search space.

[0094] Step 6.3.1, define parameter sharing constraints as the relationship between parameters provided by experts, for example, some parameters must take the same value;

[0095] Step 6.3.2: Update the prior distribution of parameters according to the parameter sharing constraint, thereby further restricting the search space of parameters;

[0096] Step 6.4: Use Bayesian optimization algorithm to select the next sampling point

[0097] The Bayesian optimization algorithm uses a series of initial data to define a surrogate model (usually a Gaussian process) and selects the next sampling point by maximizing the acquisition function and updating the surrogate model with the new sampled data;

[0098] Step 6.5: Repeat step 6.4 until the predetermined performance target is achieved or the upper limit of the number of iterations is reached. The optimal circuit parameters are found through iterative simulation and model update.

[0099] Step 7: Topology Reconstruction

[0100] If the initial topology fails to meet the performance target after size optimization, a topology reconstruction is performed, using LLM to propose a new design strategy that is based on the previous performance target and design, and uses the comparative knowledge of LLM to select a topology that is more suitable for the target performance. Steps 5 and 6 are repeated until the performance target is achieved or all possible topologies are exhausted.

[0101] Because the present invention adopts the above technical means, it has the following beneficial effects:

[0102] The present invention provides an AMS circuit automatic design method using a large language model, which solves the problem of insufficient automation of existing AMS circuit design by the following technical means:

[0103] 1. Data extraction and knowledge graph construction: By extracting circuit schematics and text descriptions from literature, a data set containing circuit schematics, netlists, and annotation information is constructed, and then a knowledge graph is constructed to store circuit information. This method solves the problem of obtaining and storing data required for AMS circuit design in the existing technology, and provides rich information resources for subsequent automatic design.

[0104] 2. Circuit schematic and netlist processing: Connectivity detection and annotation processing are performed on the circuit schematic, and the netlist is extracted to improve the automation of circuit design. This step reduces manual intervention and improves design efficiency by automatically identifying circuit components and connection relationships.

[0105] 3. Design strategy acquisition and circuit assembly: Use large language models to acquire design strategies, describe circuit architecture, and assemble into complete circuit topology based on design strategies and local annotations. This method combines artificial intelligence technology to automatically generate circuit design strategies based on performance specifications, thereby improving the level of design intelligence.

[0106] 4. Size optimization and topology reconstruction: The size optimization problem is formulated as a black box optimization problem and solved using the Bayesian optimization algorithm to improve the optimization efficiency. At the same time, if the initial topology structure cannot meet the performance target, the topology reconstruction is performed to further optimize the design. This step improves the performance and practicality of the design by automatically optimizing the circuit parameters and topology structure.

[0107] 5. Application of expert knowledge and large-scale multilingual language models: Introducing expert knowledge, such as parameter sharing constraints, further optimizes the search space, and uses large-scale multilingual language models for annotation processing and design strategy description, which enhances the accuracy and flexibility of the design.

[0108] Compared with the prior art, the present invention has advantages in the following aspects:

[0109] High degree of automation: greatly reduces manual intervention and improves design efficiency.

[0110] Intelligent design strategies: Combined with large language models, it can automatically generate design strategies based on performance specifications.

[0111] Optimization efficiency: The Bayesian optimization algorithm is used for size optimization to improve the optimization efficiency.

[0112] Flexibility and applicability: The introduction of expert knowledge and multilingual large-scale language models enhances the flexibility and applicability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0113] Figure 1 It is a simple block diagram of the process of the present invention;

[0114] Figure 2 A simplified flowchart of the detailed steps of step 1;

[0115] Figure 3 A simple block diagram is provided for analyzing each component cluster to determine its connectivity. DETAILED DESCRIPTION

[0116] The following is a detailed description of the embodiments of the present invention. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, modifications or equivalent substitutions made to the present invention should all be included in the scope of the claims of the present invention.

[0117] In addition, in order to better illustrate the present invention, numerous specific details are given in the following specific embodiments. It will be understood by those skilled in the art that the present invention can also be implemented without these specific details.

[0118] The present invention provides an AMS circuit automatic design method using a large language model, comprising the following steps:

[0119] Step 1: Extract the circuit schematic diagram and text description from the original document to obtain the circuit schematic diagram, netlist and annotation information for constructing the AMSnet-KG knowledge graph;

[0120] The steps in step 1 include:

[0121] Step 1.1: Collect raw data from textbooks and academic papers, including circuit schematics and text descriptions, to provide the basis for the dataset.

[0122] Step 1.2: Use a semi-supervised learning method to extract circuit schematics. Specifically, the schematics are labeled on a subset of page images, and a target detection model is trained to identify and extract all circuit schematics on the remaining pages.

[0123] Step 1.3, using the uniformity of the schematics printed in the literature for template matching, manually annotate one copy of each component type, and quickly identify other identical components through template matching;

[0124] Step 1.4, label each direction of each component category, including direction information for determining component connections;

[0125] Step 1.5: Use the template matching data to train the model and apply it to annotate the remaining circuit schematics for extraction;

[0126] Step 1.6: Manually evaluate the recall rate of component and symbol detection results to ensure that the recall rate meets the threshold requirement, and obtain the position labels and category labels of all components in the circuit schematic;

[0127] Step 1.7: Output a dataset containing circuit schematics, netlists, and annotation information for building the AMSnet-KG knowledge graph.

[0128] In order to facilitate those skilled in the art to better understand the technical concept of the present invention, we first collect a large amount of raw data from textbooks and academic papers. These materials are rich in circuit schematics and text descriptions, which provide us with a sufficient basis for forming a data set of <circuit schematics, netlists, annotation information>. In order to reduce the cost of manually extracting circuit schematics, we adopt a semi-supervised learning method. We annotate the bounding boxes of schematics on a subset of page images and train an object detection model using labeled data. This model is then used to identify and extract all circuit schematics from the remaining pages. Since most literature prints their schematics in a very uniform way, individual components are usually printed in a uniform way, which allows us to perform template matching. We do not need to manually annotate the bounding boxes of components in schematics to form a training set as we do for literature pages, but only need to annotate one copy of each component type. For example, after annotating a PMOS transistor, the region of interest (RoI) within the bounding box can be template matched with other schematics to quickly identify all other PMOS transistors. This greatly reduces the workload required for manual annotation. It is important to note that the direction information will be used in subsequent steps to determine component connectivity. Therefore, we need to provide a label for each direction of each component class.

[0129] Step 2: Perform connectivity detection on the circuit schematic to obtain a netlist;

[0130] The steps in step 2 include:

[0131] Step 2.1, perform component identification processing on the circuit schematic diagram to obtain component annotations;

[0132] Step 2.2, perform network cable identification processing on the component annotation to obtain a netlist;

[0133] Step 2.2.1: Traverse each component label in the circuit schematic to identify the connection relationship between the components.

[0134] Step 2.2.2, classify the wires in the schematic diagram according to the preset wire identification rules. The wire identification rules are that all wires are represented by solid lines, and wires that intersect but have no intersection are not considered connected;

[0135] Step 2.2.3: Perform an extended search on the wire pixels around each component until other components or boundaries are encountered to form a component cluster.

[0136] Step 2.2.4: Analyze each component cluster to determine its connectivity:

[0137] Step 2.2.4.1. If the cluster contains only the starting component, mark it as no connectivity detected.

[0138] Step 2.2.4.2. If the cluster contains exactly two components, mark these two components as connected.

[0139] Step 2.2.4.3. If the cluster contains an odd number of components, and it is greater than two, mark the circuit diagram as abnormal and require manual inspection.

[0140] Step 2.2.4.4. If the cluster contains an even number of components, and it is greater than two, assume that the circuit diagram has no missing nodes and the intersecting wires are not connected.

[0141] Step 2.2.5: Apply 2D convolution to the searched wires to locate the intersection. The convolution kernel dimension is adjusted according to the line thickness and layout.

[0142] Step 2.2.6, regard the index of the maximum pixel density near the intersection as the intersection point, and add it to the component annotation;

[0143] Step 2.2.7, repeat the grouping process, connect each component in the grouping to the intersection, and eliminate the four-component cluster;

[0144] Step 2.2.8: If the number of components in a group exceeds four, reduce it by two each iteration until only two components remain in each group;

[0145] Step 2.2.9, rearrange the relative connections, delete the intersections, and complete the network cable identification process.

[0146] Step 2.2.10. For some components, correctly order the connections according to the SPICE netlist format requirements. For example, the connections of a four-terminal MOSFET must follow the order of drain, gate, source, and body / substrate.

[0147] Step 2.2.11. For the component, use the orientation markings on the bounding box to determine an angle range for each connection.

[0148] Step 2.2.12. For the symbol, use MLLM to determine the function of each pin;

[0149] Step 2.2.13. Manually verify the quality of the network cable marking process to ensure an accuracy rate of 96%, and manually correct erroneous results to ensure data quality;

[0150] Step 2.2.14. Output a netlist containing circuit components, symbols, and nets.

[0151] Step 3, annotate the circuit schematic and netlist to obtain annotation information;

[0152] The steps in step 3 include:

[0153] Step 3.1: Manually annotate the circuit schematic and netlist to obtain local annotations. The specific operations include:

[0154] Label each component in the circuit schematic, including identifying the network wires as input, bias, and output;

[0155] Labeling groups of components, such as identifying a group of components as a building block, including a current mirror or a differential pair;

[0156] Dimensioning constraints, marking certain sets of components to follow symmetry constraints such as length and width;

[0157] Label the nets that connect the circuit's pins to the testbench;

[0158] Step 3.2: Perform MLLM generation processing on the circuit schematic and netlist to obtain global annotations. The operations include:

[0159] The qualitative descriptions are summarized into key-value pairs using a multilingual large language model (MLLM), including: {gain: high} or {load: current mirror};

[0160] Generate JSON files to introduce more structure in annotation information;

[0161] Merge equivalent annotations to simplify the data retrieval process and reduce the amount of data to form a knowledge graph;

[0162] Step 3.5: Utilize the circuit diagram and context description information originally obtained from the literature, combine the circuit diagram image, and obtain the local annotations and global annotations to annotate each circuit, and output the circuit schematic, netlist, and annotation information containing complete circuit design information.

[0163] Step 4: construct a knowledge graph for the circuit schematic, netlist, and annotation information to obtain AMSnet-KG;

[0164] The steps in step 4 include:

[0165] Step 4.1, perform entity relationship definition processing on the circuit schematic, netlist and annotation information to obtain the knowledge graph structure;

[0166] Step 4.1.1. Entity definition

[0167] Define entities as strings or circuits;

[0168] String entities are used to represent circuit components, test benches, etc., such as "NMOS", "PMOS", "Comparator", etc.

[0169] The circuit entity is used to represent the complete circuit topology, including information such as schematic diagram, netlist, local annotation and global annotation.

[0170] Step 1.4.2: Relationship Definition

[0171] Relationships are used to connect entities to form a graph structure;

[0172] The relationship type can be a string, such as "connects", "contains", "drives", etc.

[0173] The start and end points of a relationship are entities, such as "M1 is connected to M2" or "Comparator contains NMOS".

[0174] Step 1.4.4: Triplet construction

[0175] The basic building block in the graph is the "entity-relationship-entity" relationship query triple.

[0176] Triples are used to represent the relationship between entities, for example, “M1 is connected to M2” can be represented as a triple (“M1”, “connected”, “M2”).

[0177] Step 1.4.5: Merge equivalent annotations

[0178] Merge equivalent annotations into a knowledge graph for efficient retrieval.

[0179] For example, multiple circuits may use the same bias circuit. The bias circuit annotations of these circuits can be merged into one entity and a relationship can be established, such as "M1 contains the bias circuit."

[0180] Step 1.4.6: Knowledge graph retrieval * Use triples to search in the knowledge graph, for example: * Retrieve all circuits using differential pairs: MATCH(node: circuit{input:'Differential pair'}) RETURN node * Retrieve all circuits using current mirrors as loads: MATCH(node: circuit{load:'Current mirror'}) RETURN node * Use Cypher or other graph database query languages ​​for retrieval.

[0181] Step 4.2: Perform database storage processing on the knowledge graph structure to obtain AMSnet-KG;

[0182] Step 5. Select the topology through KG-RAG

[0183] Using performance specifications as input, the large language model (LLM) is used to obtain design strategies, describe circuit architecture, convert design strategies into relational query triples, use the triples to retrieve related circuits and test platforms in the knowledge graph, use local annotations to assemble the retrieved circuit components and test platforms into a complete circuit topology, and perform simulation.

[0184] Step 5.1: Convert performance specifications into relational query triples.

[0185] Step 5.2: Use matching query in the knowledge graph to retrieve relevant circuits and test platforms.

[0186] Step 5.3: According to the local annotation, the retrieved circuit components and test platform are assembled into a complete circuit topology.

[0187] Step 5.4: Use Cadence's Spectre circuit simulator to simulate the assembled circuit topology.

[0188] Step 6: Constraint-based size optimization

[0189] Formulate the size optimization problem as a black-box optimization problem and solve it using Bayesian optimization (BO). Use local annotations as constraints to reduce the parameter search space. Use expert insights, such as parameter sharing constraints, to further refine the search space. Use the Bayesian optimization algorithm to select the next sampling point and update the surrogate model. Repeat the steps until the performance goal or the iteration limit is reached.

[0190] Step 6.1, the size optimization problem is formulated as a black box optimization problem and solved using Bayesian optimization (BO). The goal is to minimize the difference between the performance index of the circuit design and the performance limit to optimize the circuit performance. The objective function is defined as the weighted square sum of the performance index, as shown below:

[0191]

[0192] where f i (x) represents the performance index of the ith simulation, and N represents the number of performance indexes;

[0193] is a performance limit, after which no additional performance points will be awarded.

[0194] and is the normalization factor obtained by the initial random sample set,

[0195] w i is the weight of the importance control item of each performance indicator.

[0196] Step 6.2: Use local annotations as constraints

[0197] The local annotation information retrieved by AMSnet-KG is used as constraints to reduce the parameter search space and improve the optimization efficiency. The transistor parameter set specified according to the local annotation should maintain equality or a certain ratio, and the number of parameters is reduced accordingly.

[0198] Step 6.2.1, define the local annotation as the prior knowledge of the parameter, such as the value range of the parameter;

[0199] Step 6.2.2: Update the prior distribution of parameters based on local annotations, thereby limiting the search space of parameters;

[0200] Step 6.3: Introducing expert knowledge

[0201] Using expert knowledge, such as parameter sharing constraints, further refines the search space and guides the optimization process. An exhaustive search of all transistor parameters is inefficient, so we use expert knowledge as constraints on the search space.

[0202] Step 6.3.1, define parameter sharing constraints as the relationship between parameters provided by experts, for example, some parameters must take the same value;

[0203] Step 6.3.2: Update the prior distribution of parameters according to the parameter sharing constraint, thereby further restricting the search space of parameters;

[0204] Step 6.4: Use Bayesian optimization algorithm to select the next sampling point

[0205] The Bayesian optimization algorithm uses a series of initial data to define a surrogate model (usually a Gaussian process) and selects the next sampling point by maximizing the acquisition function and updating the surrogate model with the new sampled data;

[0206] Step 6.5: Repeat step 6.4 until the predetermined performance target is achieved or the upper limit of the number of iterations is reached. The optimal circuit parameters are found through iterative simulation and model update.

[0207] To facilitate better understanding by those skilled in the art, refer to the following example:

[0208] Step 6: Constraint-based size optimization

[0209] Step 6.1: Problem Formulation and Initialization The size optimization problem is formulated as a black box optimization problem and solved using the Bayesian Optimization (BO) method. The initial input data size N is initialized. init , the number of iterations N iter , and the parameter design space S with constraint enhancement param ;

[0210] Step 6.2: Generate initial samples from the design space S param Sampling N init Initial point x init, define local annotations as prior knowledge of parameters, and update the prior distribution of parameters based on the local annotations, thereby limiting the search space of parameters.

[0211] Step 6.3: Performance simulation using x init Perform simulation and obtain performance output y init .

[0212] Step 6.4: Fit the Gaussian process model using x init and init To fit the Gaussian process (GP) model.

[0213] Step 6.5: Define local annotations as prior knowledge of parameters, and update the prior distribution of parameters based on local annotations, thereby limiting the search space of parameters. Iterative optimization for t from 0 to N iter Perform the following steps:

[0214] Select the next sampling point: select the point of the next simulation through the acquisition function α(x), and use the maximization acquisition function to find the x that maximizes α(x) next .

[0215] Performance simulation: Using x next Perform simulation and obtain performance output y next .

[0216] Update the Gaussian process model: Use x next and next Update the Gaussian process (GP) model.

[0217] End the loop: When the predetermined number of iterations N is reached iter , the loop ends.

[0218] Return Optimal Parameters: Returns the optimal sizing parameters x*.

[0219] This algorithm describes a sizing process based on Bayesian optimization that finds the optimal circuit parameters through iterative simulation and model updating.

[0220] Step 7: Topology Reconstruction

[0221] If the initial topology fails to meet the performance target after size optimization, a topology reconstruction is performed, using LLM to propose a new design strategy that is based on the previous performance target and design, and uses the comparative knowledge of LLM to select a topology that is more suitable for the target performance. Steps 5 and 6 are repeated until the performance target is achieved or all possible topologies are exhausted.

Claims

1. An AMS circuit automatic design method using a large language model, characterized in that: The following steps are involved: Step 1: Extract the circuit schematic diagram and text description from the original document to obtain the circuit schematic diagram, netlist and annotation information for constructing the AMSnet-KG knowledge graph; Step 2: Perform connectivity detection on the circuit schematic to obtain a netlist; Step 3, annotate the circuit schematic and netlist to obtain annotation information; Step 4: Build a knowledge graph for the circuit schematic, netlist, and annotation information to obtain AMSnet-KG: Step 5. Select the topology through KG-RAG Using performance specifications as input, the large language model (LLM) is used to obtain design strategies, describe circuit architectures, convert design strategies into relational query triples, use triples to retrieve related circuits and test benches in the knowledge graph, use local annotations to assemble the retrieved circuit components and test benches into a complete circuit topology, and perform simulations; Step 6: Constraint-based size optimization Formulate the size optimization problem as a black-box optimization problem and solve it using Bayesian optimization. Use local annotations as constraints to reduce the parameter search space. Use expert insights, including parameter sharing constraints, to further optimize the search space. Use the Bayesian optimization algorithm to select the next sampling point and update the surrogate model. Repeat the steps until the performance target or the iteration limit is reached. Step 7: Topology Reconstruction If the initial topology cannot meet the performance target after size optimization, topology reconstruction is performed and a new design strategy is proposed using LLM. This strategy is based on the previous performance target and design. Using the comparative knowledge of LLM, a topology that is more suitable for the target performance is selected. Steps 5 and 6 are repeated until the performance target is achieved or all possible topologies are exhausted.

2. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in step 1 include: Step 1.1: Collect raw data from textbooks and academic papers, including circuit schematics and text descriptions, to provide the basis for the dataset. Step 1.2: Use a semi-supervised learning method to extract circuit schematics. Specifically, the schematics are labeled on a subset of page images, and a target detection model is trained to identify and extract all circuit schematics on the remaining pages. Step 1.3, using the uniformity of the schematics printed in the literature for template matching, manually annotate one copy of each component type, and quickly identify other identical components through template matching; Step 1.4, label each direction of each component category, including direction information for determining component connections; Step 1.5: Use the template matching data to train the model and apply it to annotate the remaining circuit schematics for extraction; Step 1.6: Manually evaluate the recall rate of component and symbol detection results to ensure that the recall rate meets the threshold requirement, and obtain the position labels and category labels of all components in the circuit schematic; Step 1.7: Output a dataset containing circuit schematics, netlists, and annotation information for building the AMSnet-KG knowledge graph.

3. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in step 2 include: Step 2.1, perform component identification processing on the circuit schematic diagram to obtain component annotations; Step 2.2: Perform network cable identification processing on the component labels to obtain a netlist.

4. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: Step 2.2 performs network cable identification processing on the component annotations to obtain the netlist, which specifically includes the following steps: Step 2.2.1, traverse each component annotation in the circuit schematic diagram to identify the connection relationship between the components; Step 2.2.2, classify the wires in the schematic diagram according to the preset wire identification rules. The wire identification rules are that all wires are represented by solid lines, and wires that intersect but have no intersection are not considered connected; Step 2.2.3, perform an extended search on the wire pixels around each component until other components or boundaries are encountered to form a component cluster; Step 2.2.4: Analyze each component cluster to determine its connectivity: Step 2.2.5, apply two-dimensional convolution to the searched wires to locate the intersection points, and adjust the convolution kernel dimension according to the line thickness and layout; Step 2.2.6, consider the index of the maximum pixel density near the intersection point as the intersection point, and add it to the component annotation; Step 2.2.7, repeat the grouping process, connect each component in the grouping to the intersection, and eliminate the four-component cluster; Step 2.2.8: If the number of components in a group exceeds four, reduce it by two each iteration until only two components remain in each group; Step 2.2.9, rearrange the relative connections, delete the intersections, and complete the network cable identification process; Step 2.2.10: For some components, correctly sort the connections according to the SPICE netlist format requirements; Step 2.2.

11. For the component, use the orientation markings on the bounding box to determine an angle range for each connection. Step 2.2.

12. For the symbol, use MLLM to determine the function of each pin; Step 2.2.

13. Manually verify the quality of the network cable marking process to ensure an accuracy rate of 96%, and manually correct erroneous results to ensure data quality; Step 2.2.

14. Output a netlist containing circuit components, symbols, and nets.

5. The AMS circuit automatic design method using a large language model according to claim 4, characterized in that: Step 2.2.4 analyzes each component cluster to determine its connectivity, as follows: Step 2.2.4.

1. If the cluster contains only the starting component, mark it as no connectivity detected; Step 2.2.4.

2. If the cluster contains exactly two components, mark the two components as connected; Step 2.2.4.3, if the cluster contains an odd number of components, and it is greater than two, mark the circuit diagram as abnormal and require manual inspection; Step 2.2.4.

4. If the cluster contains an even number of components, and it is greater than two, assume that the circuit diagram has no missing nodes and the intersecting wires are not connected.

6. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in step 3 include: Step 3.1: Manually annotate the circuit schematic and netlist to obtain local annotations. The specific operations include: Label each component in the circuit schematic, including identifying the network wires as input, bias, and output; Labeling groups of components, such as identifying a group of components as a building block, including a current mirror or a differential pair; Dimensioning constraints, marking certain sets of components to follow symmetry constraints such as length and width; Label the nets that connect the circuit's pins to the test bench; Step 3.2: Perform MLLM generation processing on the circuit schematic and netlist to obtain global annotations. The operations include: Use a multilingual large language model (MLLM) to aggregate qualitative descriptions into key-value pairs; Generate JSON files to introduce more structure in annotation information; Merge equivalent annotations to simplify the data retrieval process and reduce the amount of data to form a knowledge graph; Step 3.5: Utilize the circuit diagram and context description information originally obtained from the literature, combine the circuit diagram image, and obtain the local annotations and global annotations to annotate each circuit, and output the circuit schematic, netlist, and annotation information containing complete circuit design information.

7. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in step 4 include: Step 4.1, perform entity relationship definition processing on the circuit schematic, netlist and annotation information to obtain the knowledge graph structure; Step 4.2: Perform database storage processing on the knowledge graph structure to obtain AMSnet-KG.

8. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps of step 4.1 include: Step 4.1.1, Entity Definition Define entities as strings or circuits; String entities are used to represent circuit components, test benches, including "NMOS", "PMOS", or circuit structure functions; The circuit entity is used to represent the complete circuit topology, including schematic diagram, netlist, local annotation and global annotation information; Step 1.4.2: Relationship Definition Relationships are used to connect entities to form a graph structure; The relationship type can be a string, including "connect", "contains", and "drive"; The starting point and end point of a relationship are entities; Step 1.4.4: Triplet construction The basic unit in the graph is the "entity-relationship-entity" relationship query triple; Triples are used to represent relationships between entities; Step 1.4.5: Merge equivalent annotations Merge equivalent annotations into a knowledge graph for efficient retrieval.

9. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in step 5 include: Step 5.1, convert the performance specification into a relational query triple; Step 5.2: Use matching query in the knowledge graph to retrieve relevant circuits and test platforms; Step 5.3, assembling the retrieved circuit components and test platform into a complete circuit topology according to the local annotation; Step 5.4: Use Cadence's Spectre circuit simulator to simulate the assembled circuit topology.

10. The AMS circuit automatic design method using a large language model according to claim 1, characterized in that: The following steps are involved: The steps in step 6 include: Step 6.

1. Formulate the size optimization problem as a black box optimization problem and solve it using Bayesian optimization. The goal is to minimize the difference between the performance index of the circuit design and the performance limit to optimize the circuit performance. The objective function is defined as the weighted sum of the squares of the performance index, as shown below: where f i (x) represents the performance index of the ith simulation, and N represents the number of performance indexes; is a performance limit, after which no additional performance points will be awarded. and is the normalization factor obtained by the initial random sample set, w i is the weight of the importance control item of each performance indicator; Step 6.2: Use local annotations as constraints The local annotation information retrieved by AMSnet-KG is used as constraints to reduce the parameter search space and improve the optimization efficiency. The transistor parameter set specified by the local annotation should maintain equality or a certain ratio, and the number of parameters is reduced accordingly; Step 6.2.1, define the local annotation as the prior knowledge of the parameter, such as the value range of the parameter; Step 6.2.2: Update the prior distribution of parameters based on local annotations, thereby limiting the search space of parameters; Step 6.3: Introducing expert knowledge Use expert knowledge, such as parameter sharing constraints, to further optimize the search space; Step 6.3.1, define parameter sharing constraints as the relationship between parameters provided by experts, for example, some parameters must take the same value; Step 6.3.2: Update the prior distribution of parameters according to the parameter sharing constraint, thereby further restricting the search space of parameters; Step 6.4: Use Bayesian optimization algorithm to select the next sampling point The Bayesian optimization algorithm uses a series of initial data to define a surrogate model and selects the next sampling point by maximizing the acquisition function and updating the surrogate model with the new sampled data; Step 6.5: Repeat step 6.4 until the predetermined performance target is achieved or the upper limit of the number of iterations is reached, and the optimal circuit parameters are found through iterative simulation and model update.

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