Server mainboard lamination and design method

Abstract

The invention discloses a server mainboard lamination and a design method. The design method of the server mainboard lamination comprises the following steps: arranging a key power supply on a power supply layer; the copper thickness of the two power supply layers is set according to the current of a key power supply of the server mainboard, and a dielectric layer is arranged between the two power supply layers; according to the signal rate information of the server mainboard, classifying the signals of the server mainboard according to the transmission rate; selecting a base material of a dielectric layer between a signal layer of the layout signal and a corresponding ground layer according to the signal classification of the server mainboard; from the outer layer to the inner layer, the sequence of the conducting layers of the server mainboard lamination is designed according to the sequence of the outermost conducting layer and the corresponding ground layer, the signal layer and the corresponding ground layer and the power supply layer; and constructing a lamination model of server mainboard lamination. According to the technical scheme provided by the embodiment of the invention, the preparation cost and the preparation difficulty are reduced.

Description

Technical Field

[0001] The invention relates to the field of printed circuit boards, and in particular to a server mainboard stack and a design method. Background Art

[0002] As the core component of the server, the server motherboard stack not only carries key hardware such as processors, memory, storage and network interfaces, and expansion cards, but also ensures efficient collaboration between various components through its complex circuit design and layout. Since servers usually need to run 24 hours a day and are often under high load, and also need to consider seamless compatibility with multiple external devices and system interactions, the design of the server motherboard stack must fully consider stability, reliability, and compatibility.

[0003] In the design of server motherboards, stacking is a crucial link because factors such as the selection of substrate, the arrangement of electrical ground plane layers and signal layers, and the setting of core type and thickness will all affect the signal integrity of the server motherboard.

[0004] With the continuous advancement of CPU technology on server motherboards, the increase in processing speed and core number has significantly improved the signal transmission rate. While this improvement enhances server performance, it also brings new challenges to motherboard design. Higher data transmission rates, more channels, and faster memory technologies (such as DDR5) are widely used. In this context, in order to ensure the integrity of the signal, the use of high-performance substrates or increasing the number of layers has become an inevitable trend. Although these measures can effectively improve signal quality, they also lead to problems such as rising costs and extended project cycles.

[0005] In the design process of the existing printed circuit board (PCB) of the server motherboard, first of all, the choice of substrate is mainly related to the product grade and maximum signal transmission rate of the server motherboard. In order to ensure the quality of high-speed signal transmission, substrates with excellent performance are usually preferred, which will directly lead to an increase in the cost of the motherboard. It is worth noting that in the PCB design of most motherboards, not all signals are transmitted at the highest rate. For those signals with relatively low transmission rates and not very stringent requirements on signal quality, relatively low-cost or universal substrates can be selected; secondly, in order to match the characteristic impedance requirements, the inner core generally uses thinner copper foil. In the face of the high current transmission requirements of the server motherboard and the high-speed signal line wiring space requirements, the current load can only be effectively dispersed and balanced by increasing the number of PCB layers to ensure the stable operation of the circuit; and the increase in the number of layers will not only increase the difficulty of the process, but also lead to further increase in costs. In summary, the existing technology usually uses a large number of high-performance boards and increases the number of layers to meet the design requirements of the server motherboard stacking, which directly leads to increased costs and increased process difficulty. For example, the following Figure 1 As shown in the stacking, Figure 1 It is a structural diagram of a server motherboard stack provided by the prior art. Figure 1 The server motherboard stack includes 18 conductive layers, namely L1, L2, L3, and L18. The stack is as follows:

[0006] Top / GND1 / S1 / VCC1 / S2 / GND2 / S3 / GND3 / VCC2 / VCC3 / GND4 / S4 / GND 5 / S5 / GND6 / S6 / GND7 / Bottom.

[0007] Among them, L1 layer is the top layer (Top), L2 layer is the ground layer GND1; L3 layer is the signal layer S1; L4 layer is the ground layer VCC1; L5 layer is the signal layer S2; L6 layer is the ground layer GND2; L7 layer is the signal layer S3; L8 layer is the ground layer GND3; L9 layer is the power layer VCC2; L10 layer is the power layer VCC3; L11 layer is the ground layer GND4; L12 layer is the signal layer S4; L13 layer is the ground layer GND5; L14 layer is the signal layer S5; L15 layer is the ground layer GND6; L16 layer is the signal layer S6; L17 layer is the ground layer GND7, and L18 layer is the bottom layer (Bottom).

[0008] Figure 1 The core board (Core), also called the dielectric layer, uses an ultra-low loss substrate such as R5775G substrate, and the copper thickness of all conductive layers is equal, for example, 0.5OZ copper thickness is used, which increases the preparation cost and difficulty of the server motherboard stack. Summary of the invention

[0009] The present invention provides a server mainboard stack and a design method, which reduce the preparation cost and preparation difficulty of the server mainboard stack.

[0010] According to one aspect of the present invention, a method for designing a server motherboard stack is provided, comprising:

[0011] Identify key power supplies based on the power supply information of the server motherboard;

[0012] Laying out the key power supply on the power layer;

[0013] The copper thickness of the two power supply layers is set according to the current size of the key power supply of the server motherboard, wherein a dielectric layer is provided between the two power supply layers;

[0014] According to the signal rate information of the server mainboard, the signals of the server mainboard are classified according to the transmission rate;

[0015] According to the signal classification of the server motherboard, a substrate for the dielectric layer between the signal layer and the corresponding ground layer for laying out the signal is selected, wherein the higher the signal transmission rate, the lower the signal transmission loss of the dielectric layer between the signal layer and the corresponding ground layer for the signal; the signal layer and the signal category of the server motherboard correspond one to one; the signal transmission loss of the dielectric layer between the signal layer and the corresponding ground layer for the signal is less than the signal transmission loss of the dielectric layer set between the two power supply layers;

[0016] From the outer layer to the inner layer, the conductive layer sequence of the server motherboard stack is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer; wherein the copper thickness of the signal layer is less than the copper thickness of the ground layer corresponding to the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer; from the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the transmission rate of the signal;

[0017] A stacking model of the server mainboard stack is constructed according to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material and characteristic impedance calculation model of the dielectric layer, and the symmetrical distribution principle of the stacking layer about the power layer.

[0018] Optionally, according to the signal rate information of the server mainboard, classifying the signals of the server mainboard according to the transmission rates includes:

[0019] According to the signal rate information of the server mainboard, the signal of the server mainboard is divided into a high-speed signal and a low-speed signal according to the transmission rate, wherein the transmission rate of the high-speed signal is greater than the transmission rate of the low-speed signal;

[0020] According to the signal classification of the server motherboard, the substrates of the dielectric layer between the signal layer and the corresponding ground layer include:

[0021] Laying out high-speed signals on a signal layer on the surface of the first dielectric layer;

[0022] The low-speed signal is arranged in the signal layer on the surface of the second dielectric layer, and the transmission loss of the signal by the second dielectric layer is greater than the transmission signal loss of the signal by the first dielectric layer.

[0023] Optionally, according to the power supply information of the server mainboard, before identifying the key power supply, the following steps are further included:

[0024] The motherboard information of the server motherboard is obtained, wherein the motherboard information includes at least one of physical specifications, electrical characteristics, processor configuration, memory expansion capability, inter-processor communication information, expansion interface performance, and power supply information.

[0025] Optionally, the physical specifications include board thickness and production grade; the electrical characteristics include characteristic impedance requirements; the processor configuration includes CPU model and power; the memory expansion capability includes the memory slot type and memory module specifications and maximum speed supported by the server motherboard; the inter-processor communication information includes the bus technology used for communication between CPUs or between the CPU and the chipset and its maximum operating speed; the expansion interface performance includes the expansion interface type and the maximum operating speed; the power supply information includes the estimated power consumption of the motherboard when running at full load and the current requirements of the key power supply network.

[0026] Optionally, the transmission rate of the high-speed signal is greater than or equal to 10 Gbps;

[0027] The transmission rate of the low-speed signal is less than 10 Gbps.

[0028] Optionally, the transmission rate of the high-speed signal is greater than or equal to 20 Gbps.

[0029] Optionally, the first dielectric layer is a R5775G substrate;

[0030] The second dielectric layer is a TU872 substrate;

[0031] The dielectric layer between the two power supply layers is a TU752 substrate.

[0032] Optionally, according to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material of the dielectric layer and the characteristic impedance calculation model, constructing the stacking model of the server mainboard stacking further includes:

[0033] Selecting the copper thickness of the outermost conductive layer to be equal to the copper thickness of the signal layer;

[0034] Selecting the same base material for the dielectric layer between the outermost conductive layer and the corresponding ground layer and the dielectric layer between the signal layer close to the outermost conductive layer and the corresponding ground layer;

[0035] Optionally, the base material of the adhesive layer in contact with the power layer is selected to be the same as the base material of the dielectric layer between the two power layers;

[0036] Selecting a bonding layer between the outermost conductive layer and the signal layer close to the outermost conductive layer to have the same base material as a dielectric layer between the signal layer close to the outermost conductive layer and the corresponding ground layer;

[0037] The bonding layer between two adjacent signal layers is selected to have the same base material as that of the dielectric layer between the signal layer close to the power layer and the corresponding ground layer in the two adjacent signal layers.

[0038] According to another aspect of the present invention, there is provided a server motherboard stack, comprising:

[0039] The server mainboard laminate is prepared according to the design method of the server mainboard laminate, and the design method of the server mainboard laminate is any of the design methods of the server mainboard laminate described in the first aspect of the present invention.

[0040] The server motherboard stacking design method provided by the embodiment of the present invention, in the planning of the signal layer and the selection of the substrate, classifies the signals of the server motherboard according to the transmission rate according to the signal rate information of the server motherboard so as to carry out centralized wiring planning. The higher the signal transmission rate, the lower the signal transmission loss of the dielectric layer between the signal layer transmitting the signal and the corresponding stratum, thereby effectively reducing the material cost under the premise of ensuring the overall performance.

[0041] In the planning of power layers and the selection of substrates, we follow the core principles of ensuring signal integrity and power integrity. According to the power information of the server motherboard, we identify the key power supply, select the power layer in the feature layer, and then layout the key power supply in a specific layer. In addition, we set the copper thickness of the two power layers according to the current size of the key power supply of the server motherboard to support stable power distribution and thermal management. The copper thickness of the power layer needs to meet the high current requirements of the key power supply, and there is no need to excessively increase the number of layers of the server motherboard stack, thereby ensuring performance while controlling costs.

[0042] In the planning of the conductive layer stacking sequence, from the outer layer to the inner layer, the conductive layer sequence of the server motherboard stacking is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer. From the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the signal transmission rate is, ensuring a low-impedance return path for high-speed signals and minimizing interference. The stacking model of the server motherboard stacking is constructed according to the principle of symmetrical distribution of the stacking layer about the power layer, which can reduce the warping phenomenon that may occur during the manufacturing and use of the server motherboard.

[0043] In terms of copper thickness selection, the copper thickness of the signal layer is less than the copper thickness of the corresponding ground layer of the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer. In order to balance the needs of signal transmission, power stability, and electromagnetic compatibility, some substrates adopt the strategy of yin and yang copper (also known as a combination of copper foils of different thicknesses). The signal layer uses thinner copper foil to control the characteristic impedance of the signal line; the ground layer can use thicker copper foil to provide a larger return path for the power supply and signal, reduce the power supply impedance and ground noise, and thus improve signal integrity and electromagnetic compatibility (EMC). The power layer can choose thicker copper foil to meet the current carrying requirements, so that the copper thickness of the power layer needs to meet the high current requirements of the key power supply, and there is no need to excessively increase the number of layers of the server motherboard stack, thereby ensuring performance while controlling costs.

[0044] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a structural schematic diagram of a server motherboard stack provided by the prior art;

[0047] Figure 2 It is a flow chart of a method for designing a server motherboard stack provided by an embodiment of the present invention;

[0048] Figure 3 is a flow chart of another server motherboard stacking design method provided by an embodiment of the present invention;

[0049] Figure 4 It is a structural schematic diagram of a stacking model of a server motherboard stack provided by an embodiment of the present invention;

[0050] Figure 5 The present invention is a schematic diagram of a server motherboard stack. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] In order to reduce the preparation cost and difficulty of the server motherboard, the embodiment of the present invention provides the following technical solutions:

[0054] like Figure 2 As shown, Figure 2 1 is a flow chart of a method for designing a server motherboard stack provided by an embodiment of the present invention. The method for designing a server motherboard stack includes the following steps:

[0055] S110. Identify a key power supply according to power supply information of a server mainboard.

[0056] The layout of the power plane of the key power supply needs to meet the high current requirements of the key power supply.

[0057] S120. Place key power supplies on the power layer.

[0058] Specifically, the power layer is selected at the feature layer, and then the key power supply is laid out at the specific layer.

[0059] S130. The copper thickness of two power supply layers is set according to the current size of the key power supply of the server mainboard, and a dielectric layer is provided between the two power supply layers.

[0060] Specifically, the thickness of the power layer can be set thicker than other conductive layers, for example, greater than or equal to 70 microns, so that the copper thickness of the power layer can meet the high current requirements of the key power supply without excessively increasing the number of layers of the server motherboard stack, thereby ensuring performance while controlling costs.

[0061] S140: Classify the signals of the server mainboard according to the transmission rates based on the signal rate information of the server mainboard.

[0062] The signals of the server mainboard are classified according to the transmission rate, and the substrate of the dielectric layer between the signal layer and the corresponding ground layer of the layout signal can be selected according to the classification of the signals of the server mainboard.

[0063] S150. According to the signal classification of the server mainboard, select a substrate for the dielectric layer between the signal layer and the corresponding ground layer for laying out the signal, wherein the higher the signal transmission rate, the lower the signal transmission loss of the dielectric layer between the signal layer and the corresponding ground layer for the signal; the signal layer and the signal category of the server mainboard correspond one to one; the signal transmission loss of the dielectric layer between the signal layer and the corresponding ground layer for the signal is less than the signal transmission loss of the dielectric layer set between the two power supply layers.

[0064] Specifically, the server motherboard can transmit signals of different transmission rates. For signals with high transmission rates, high-performance high-speed boards with low signal transmission loss can be selected to ensure signal integrity. For signals with low transmission rates, areas with relatively low performance requirements can be selected, and lower-cost boards can be selected, thereby effectively reducing material costs while ensuring overall performance.

[0065] S160. From the outer layer to the inner layer, the conductive layer sequence of the server motherboard stack is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer; wherein the copper thickness of the signal layer is less than the copper thickness of the ground layer corresponding to the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer; from the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the signal transmission rate.

[0066] From the outer layer to the inner layer, the conductive layer sequence of the server motherboard stack is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer. From the outer layer to the inner layer, the closer the signal layer is to the power layer, the lower the signal transmission rate is, ensuring a low-impedance return path for high-speed signals and minimizing interference.

[0067] S170, constructing a stacking model of the server mainboard stack according to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material and characteristic impedance calculation model of the dielectric layer, and the symmetrical distribution principle of the stacking layer with respect to the power layer.

[0068] The stacking model of the server motherboard stacking is constructed according to the symmetrical distribution principle of the stacking about the power layer, which can reduce the warping phenomenon that may occur in the server motherboard stacking during the manufacturing and use process.

[0069] According to the characteristic impedance of the server motherboard, the copper thickness of the conductive layer, the base material of the dielectric layer and the characteristic impedance calculation model, a stacking model of the server motherboard stacking is constructed, that is, under the rule that the copper thickness of the signal layer is less than the copper thickness of the corresponding ground layer of the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer, from the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the signal transmission rate is; under the rule that the copper thickness of the two power layers is set according to the current size of the key power supply of the server motherboard, the higher the signal transmission rate, the lower the signal transmission loss of the dielectric layer between the signal layer transmitting the signal and the corresponding ground layer, the stacking model of the server motherboard stacking is simulated and constructed, in which different layers are connected by an adhesive layer.

[0070] The server motherboard stacking design method provided by the embodiment of the present invention, in the planning of the signal layer and the selection of the substrate, classifies the signals of the server motherboard according to the transmission rate according to the signal rate information of the server motherboard so as to carry out centralized wiring planning. The higher the signal transmission rate, the lower the signal transmission loss of the dielectric layer between the signal layer transmitting the signal and the corresponding stratum, thereby effectively reducing the material cost under the premise of ensuring the overall performance.

[0071] In the planning of power layers and the selection of substrates, we follow the core principles of ensuring signal integrity and power integrity. According to the power information of the server motherboard, we identify the key power supply, select the power layer in the feature layer, and then layout the key power supply in a specific layer. In addition, we set the copper thickness of the two power layers according to the current size of the key power supply of the server motherboard to support stable power distribution and thermal management. The copper thickness of the power layer needs to meet the high current requirements of the key power supply, and there is no need to excessively increase the number of layers of the server motherboard stack, thereby ensuring performance while controlling costs.

[0072] In the planning of the conductive layer stacking sequence, from the outer layer to the inner layer, the conductive layer sequence of the server motherboard stacking is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer. From the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the signal transmission rate is, ensuring a low-impedance return path for high-speed signals and minimizing interference. In addition, the stacking model of the server motherboard stacking is constructed according to the principle of symmetrical distribution of the stacking layer about the power layer, which can reduce the warping phenomenon that may occur in the server motherboard stacking during manufacturing and use.

[0073] In terms of copper thickness selection, the copper thickness of the signal layer is less than the copper thickness of the corresponding ground layer of the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer. In order to balance the needs of signal transmission, power stability, and electromagnetic compatibility, some substrates adopt the strategy of yin and yang copper (also known as a combination of copper foils of different thicknesses). The signal layer uses thinner copper foil to control the characteristic impedance of the signal line; the ground layer can use thicker copper foil to provide a larger return path for the power supply and signal, reduce the power supply impedance and ground noise, and thus improve signal integrity and electromagnetic compatibility (EMC). The power layer can choose thicker copper foil to meet the current carrying requirements, so that the copper thickness of the power layer needs to meet the high current requirements of the key power supply, and there is no need to excessively increase the number of layers of the server motherboard stack, thereby ensuring performance while controlling costs.

[0074] The embodiment of the present invention also provides a method for designing a server motherboard stack. Figure 3 As shown, Figure 3 1 is a flow chart of another method for designing a server motherboard stack provided by an embodiment of the present invention. The method for designing a server motherboard stack includes the following steps:

[0075] S210. Obtain motherboard information of the server motherboard, where the motherboard information includes at least one of physical specifications, electrical characteristics, processor configuration, memory expansion capability, inter-processor communication information, expansion interface performance, and power supply information.

[0076] Optionally, the physical specifications of the server motherboard include board thickness and production grade; electrical characteristics include characteristic impedance requirements; processor configuration includes CPU model and power; memory expansion capability includes memory slot types and memory module specifications and maximum speed supported by the server motherboard; inter-processor communication information includes bus technology used for communication between CPUs or between CPU and chipset and its maximum operating speed; expansion interface performance includes expansion interface type and maximum operating speed; power supply information includes estimated power consumption of the motherboard when running at full load and current requirements of key power supply networks.

[0077] Among them, the bus technologies used for communication between CPUs or between CPUs and chipsets include UPI and CXL. UPI is Intel's

[0078] Ultra Path Interconnect is a technology that replaces QPI. It has higher communication speed, higher efficiency and lower power consumption. QPI is Intel's QuickPath Interconnect. CXL (Compute ExpressLink) technology leads a new era of high-speed interconnection, achieving a surge in data throughput and a significant reduction in latency, perfectly matching the needs of modern computing and storage systems.

[0079] In the extended interface performance, the extended interface types include PCIE structure, USB interface, SATA interface, etc.

[0080] Exemplarily, the motherboard information of the server motherboard is as follows:

[0081] Physical specifications: Board thickness 2.5mm.

[0082] Characteristic impedance: 50 ohm, 85 ohm, 100 ohm, 90 ohm.

[0083] Processor configuration: The CPU model is S5000C, and its maximum power consumption is 200W.

[0084] Memory expansion capability: supports 4 DDR4 interfaces with a maximum rate of 3200MT / s.

[0085] Inter-processor communication: CPU0 and CPU1 are interconnected using C2C X8 communication, with a single lane rate of 32 Gbps.

[0086] Expansion interface performance: 4-way PCIE X1 expansion interface, 2-way PCIEX8 expansion interface, 2-way PCIE X16 expansion interface, with a maximum rate of 8Gbps; 2-way USB3.0 interface with a maximum rate of 5Gbps; the rates of HDMI interface, SATA interface, SPI interface, etc. are all less than 5Gbps.

[0087] Key power supply and current information: CPU0 power supply and CPU1 power supply: VDD / 240A; VDDQ / 60A; whole board power supply 3V3 / 20A.

[0088] S220. Identify a key power supply according to power supply information of a server mainboard.

[0089] Taking the motherboard information of the above server motherboard as an example, the key power supplies are CPU0 power supply and CPU1 power supply.

[0090] S230. Place the key power supply on the power layer.

[0091] like Figure 4 As shown, Figure 4 is a structural schematic diagram of a stacking model of a server motherboard stack provided by an embodiment of the present invention, Figure 4 In the server motherboard stacking model, the stacking model includes 14 conductive layers, namely the outermost conductive layer (TOP layer), L2 layer, L3 layer, up to L13 layer, and the outermost conductive layer (BOTTOM layer), and the stacking is:

[0092] Top / GND1 / S1 / GND2 / S2 / GND3 / VCC1 / VCC2 / GND4 / S3 / GND5 / S4 / GND6 / Bottom.

[0093] Among them, the L2 layer is the ground layer GND1; the L3 layer is the signal layer S1; the L4 layer is the ground layer GND2; the L5 layer is the signal layer S2; the L6 layer is the ground layer GND3; the L7 layer is the power layer VCC1; the L8 layer is the power layer VCC2; the L9 layer is the ground layer GND4; the L10 layer is the signal layer S3; the L11 layer is the ground layer GND5; the L12 layer is the signal layer S4; and the L13 layer is the ground layer GND6.

[0094] For example, Figure 4 As shown, the CPU0 power supply and the CPU1 power supply are arranged on the power supply layers L7 and L8, the L7 layer is the power supply layer VCC1, and the L8 layer is the power supply layer VCC2.

[0095] S240. The copper thickness of two power supply layers is set according to the current size of the key power supply of the server motherboard, and a dielectric layer is set between the two power supply layers.

[0096] like Figure 4 As shown, illustratively, the copper thickness of the power layers L7 and L8 is set to 70 microns.

[0097] S250. According to the signal rate information of the server mainboard, the signal of the server mainboard is divided into a high-speed signal and a low-speed signal according to the transmission rate, wherein the transmission rate of the high-speed signal is greater than the transmission rate of the low-speed signal.

[0098] Optionally, the transmission rate of the high-speed signal is greater than or equal to 10 Gbps, and the transmission rate of the low-speed signal is less than 10 Gbps. Preferably, the transmission rate of the high-speed signal is greater than or equal to 20 Gbps.

[0099] S260 , layout the high-speed signal on the signal layer on the surface of the first dielectric layer.

[0100] For example, Figure 4 As shown, the L3 layer and the L12 layer are symmetrically set as signal layers with respect to the power layer, and the memory DDR5 or DDR4 is set to transmit high-speed signals above 10 Gbps, and high-speed signals above 10 Gbps are preferentially laid out.

[0101] Optionally, the first dielectric layer between the L3 layer, the L12 layer and the corresponding stratum is an ultra-low loss substrate R5775G substrate.

[0102] S270, layout the low-speed signal in the signal layer on the surface of the second dielectric layer, the transmission loss of the second dielectric layer to the signal is greater than the transmission loss of the first dielectric layer to the signal, and the transmission loss of the dielectric layer arranged between the two power supply layers to the signal is greater than the transmission loss of the second dielectric layer to the signal.

[0103] For example, Figure 4As shown, the L5 layer and the L10 layer are symmetrically set as signal layers with respect to the power layer, and the memory DDR5 or DDR4 is set to transmit low-speed signals below 10bps.

[0104] Optionally, the second dielectric layer between the L5 layer, the L10 layer and the corresponding ground layer is a low-loss substrate TU872 substrate; and the dielectric layer between the two power layers is a standard-loss substrate TU752 substrate.

[0105] Among them, the signal transmission loss of the standard loss substrate TU752 substrate is greater than the signal transmission loss of the low loss substrate TU872 substrate, and the signal transmission loss of the low loss substrate TU872 substrate is greater than the signal transmission loss of the ultra-low loss substrate R5775G substrate.

[0106] S280. From the outer layer to the inner layer, the conductive layer sequence of the server motherboard stack is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer; wherein the copper thickness of the signal layer is less than the copper thickness of the ground layer corresponding to the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer; from the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the signal transmission rate.

[0107] For example, Figure 4 As shown, from the outer layer to the inner layer, the order of the conductive layers is as follows: the outermost conductive layer (TOP layer) and its corresponding ground layer GND1, the signal layer L3 layer of the high-speed signal and its corresponding ground layer GND2, the signal layer L5 layer of the low-speed signal and its corresponding ground layer GND3, the power layer L7 layer and the power layer L8 layer;

[0108] The outermost conductive layer (BOTTOM layer) and its corresponding ground layer GND6, the signal layer L12 of the high-speed signal and its corresponding ground layer GND5, the signal layer L10 of the low-speed signal and its corresponding ground layer GND4, the power layer L7 and the power layer L8.

[0109] Exemplarily, the copper thickness of the signal layer (18 microns) is smaller than the copper thickness of the ground layer corresponding to the signal layer (35 microns); the copper thickness of the power layer (70 microns) is larger than the copper thickness of the ground layer (35 microns); from the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the signal transmission rate.

[0110] S290. Construct a stacking model of the server mainboard stack according to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material and characteristic impedance calculation model of the dielectric layer, and the symmetrical distribution principle of the stacking layer about the power layer.

[0111] Optionally, in the process of constructing the stacking model of the server mainboard stacking layer according to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material of the dielectric layer and the characteristic impedance calculation model, and the symmetrical distribution principle of the stacking layer about the power layer, S290 further includes:

[0112] Choose the copper thickness of the outermost conductive layer to be equal to the copper thickness of the signal layer.

[0113] For example, Figure 4 As shown, the copper thickness of the outermost conductive layer (TOP layer and BOTTOM layer) and the signal layer is equal, and the copper thickness is 18 microns.

[0114] The dielectric layer between the outermost conductive layer and the corresponding ground layer and the dielectric layer between the signal layer close to the outermost conductive layer and the corresponding ground layer are selected to have the same base material.

[0115] Exemplarily, the substrates of the dielectric layer between the outermost conductive layer (TOP layer) and the corresponding stratum and the substrates of the dielectric layer between the signal layer close to the outermost conductive layer (TOP layer) and the corresponding stratum are the same, both of which are ultra-low loss substrate R5775G substrates. The substrates of the dielectric layer between the outermost conductive layer (BOTTOM layer) and the corresponding stratum and the substrates of the dielectric layer between the signal layer close to the outermost conductive layer (BOTTOM layer) and the corresponding stratum are the same, both of which are ultra-low loss substrate R5775G substrates.

[0116] And / or, the base material of the adhesive layer in contact with the power layer is selected to be the same as the base material of the dielectric layer between the two power layers.

[0117] For example, Figure 4 As shown, the base material of the bonding layer in contact with the power layer is the same as the base material of the dielectric layer between the two power layers, both of which are standard lossy base material TU752 base material.

[0118] The bonding layer between the outermost conductive layer and the signal layer close to the outermost conductive layer is selected to have the same base material as that of the dielectric layer between the signal layer close to the outermost conductive layer and the corresponding ground layer.

[0119] Exemplarily, the bonding layer between the outermost conductive layer (TOP layer) and the L3 signal layer has the same substrate as the dielectric layer between the L3 signal layer and the corresponding ground layer, which is an ultra-low loss substrate R5775G substrate.

[0120] The bonding layer between the outermost conductive layer (BOTTOM layer) and the L12 signal layer is made of the same base material as the dielectric layer between the L12 signal layer and the corresponding ground layer, both of which are ultra-low loss base material R5775G base material.

[0121] The bonding layer between two adjacent signal layers is selected to have the same base material as that of the dielectric layer between the signal layer close to the power layer and the corresponding ground layer.

[0122] Exemplarily, the bonding layer between the signal layer L3 and the signal layer L5 is the same as the substrate of the dielectric layer between the signal layer L5 near the power layer and the corresponding ground layer in the signal layer L3 and the signal layer L5, both of which are low-loss substrate TU872 substrate.

[0123] The server motherboard stacking design method provided by the embodiment of the present invention can be realized by a 14-layer board Figure 1 The function of the 18-layer board reduces the preparation cost and difficulty.

[0124] Table 1 Commonly used substrates and comparison

[0125]

[0126] Table 2 Figure 3 The structure and Figure 1 Structural comprehensive cost comparison table in

[0127]

[0128]

[0129] The dual-channel server motherboard stacking design method proposed in the embodiment of the present invention, by carefully selecting and combining substrates with different performances, greatly reduces the development cost of the server motherboard while ensuring the integrity of high-speed signals. At the same time, the process of local thick copper (the power layer is the layer with the largest copper thickness of the conductive layer) and yin-yang copper (the signal layer and the ground layer are a combination of copper foils of different thicknesses) ensures the integrity of the power supply while effectively reducing the need to add additional layers due to high current requirements, thereby further simplifying the motherboard structure and reducing the overall cost.

[0130] It should be noted that the dielectric layer and the bonding layer in the embodiment of the present invention are both prepregs, and substrates with different signal transmission losses are selected according to the signal transmission rate, such as the ultra-low loss substrate R5775G substrate, the low loss substrate TU872 and the standard loss substrate TU752. Among them, 1 oz copper thickness is equal to 35 microns copper thickness.

[0131] The embodiment of the present invention further provides a server motherboard laminate. The server motherboard laminate is prepared according to a design method for a server motherboard laminate, and the design method for the server motherboard laminate is any of the design methods for the server motherboard laminate described in the embodiment of the present invention.

[0132] like Figure 5 As shown, Figure 5 The present invention is a schematic diagram of a server motherboard stack. Figure 5 The server motherboard stackup shown is based on Figure 4The physical structure of the server motherboard stack-up model prepared is shown.

[0133] It should be noted that Figure 4 The thickness of each film layer in the stacking model of the server motherboard stacking shown is a theoretical value. Figure 5 The thickness of each film layer in the server motherboard stack shown is the empirical value in the actual production process, and the thickness of the film layer may be slightly different from the theoretical value.

[0134] The server motherboard stack has the beneficial effects of any of the server motherboard stack design methods described in the embodiments of the present invention, which will not be described in detail here.

[0135] It should be noted that:

[0136] 1) The thickness of the prepreg in the embodiment of the present invention is not fixed, and can be adjusted appropriately according to the thickness of the board. The adjustment principle is to maintain the upper and lower symmetry.

[0137] 2) The first dielectric layer includes but is not limited to R5775G substrate; the second dielectric layer includes but is not limited to TU872 substrate; the dielectric layer between the power layers includes but is not limited to TU752 substrate.

[0138] 3) During the design of the server motherboard stack, the number of conductive layers can be determined based on the signal transmission rate. Figure 4 An exemplary embodiment includes 14 conductive layers. When the number of signals exceeding 10G is large and the wiring space of the L3 layer and the L12 layer is insufficient, the number of conductive layers can be increased according to the symmetrical distribution principle of the stacking layer with respect to the power layer.

[0139] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0140] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for designing a server motherboard stack, characterized in that: include: Identify key power supplies based on the power supply information of the server motherboard; Laying out the key power supply on the power layer; The copper thickness of the two power supply layers is set according to the current size of the key power supply of the server motherboard, wherein a dielectric layer is provided between the two power supply layers; According to the signal rate information of the server mainboard, the signals of the server mainboard are classified according to the transmission rate; According to the signal classification of the server motherboard, a substrate for the dielectric layer between the signal layer and the corresponding ground layer for laying out the signal is selected, wherein the higher the signal transmission rate, the lower the signal transmission loss of the dielectric layer between the signal layer and the corresponding ground layer for the signal; the signal layer and the signal category of the server motherboard correspond one to one; the signal transmission loss of the dielectric layer between the signal layer and the corresponding ground layer for the signal is less than the signal transmission loss of the dielectric layer set between the two power supply layers; From the outer layer to the inner layer, the conductive layer sequence of the server motherboard stack is designed in the order of the outermost conductive layer and its corresponding ground layer, the signal layer and its corresponding ground layer, and the power layer; wherein the copper thickness of the signal layer is less than the copper thickness of the ground layer corresponding to the signal layer, and the copper thickness of the power layer is greater than the copper thickness of the ground layer; from the outer layer to the inner layer, the closer the signal layer layout is to the power layer, the lower the transmission rate of the signal; A stacking model of the server mainboard stack is constructed according to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material and characteristic impedance calculation model of the dielectric layer, and the symmetrical distribution principle of the stacking layer about the power layer.

2. The method for designing a server motherboard stack according to claim 1, characterized in that: According to the signal rate information of the server motherboard, the signals of the server motherboard are classified according to the transmission rate, including: According to the signal rate information of the server mainboard, the signal of the server mainboard is divided into a high-speed signal and a low-speed signal according to the transmission rate, wherein the transmission rate of the high-speed signal is greater than the transmission rate of the low-speed signal; According to the signal classification of the server motherboard, the substrates of the dielectric layer between the signal layer and the corresponding ground layer include: Laying out high-speed signals on a signal layer on the surface of the first dielectric layer; The low-speed signal is arranged in the signal layer on the surface of the second dielectric layer, and the transmission loss of the signal by the second dielectric layer is greater than the transmission signal loss of the signal by the first dielectric layer.

3. The method for designing a server motherboard stack according to claim 1, characterized in that: According to the power information of the server motherboard, before identifying the key power supply, it also includes: The motherboard information of the server motherboard is obtained, wherein the motherboard information includes at least one of physical specifications, electrical characteristics, processor configuration, memory expansion capability, inter-processor communication information, expansion interface performance, and power supply information.

4. The method for designing a server motherboard stack according to claim 3, characterized in that: The physical specifications include board thickness and production grade; the electrical characteristics include characteristic impedance requirements; the processor configuration includes CPU model and power; the memory expansion capability includes the memory slot type, memory module specifications and maximum speed supported by the server motherboard; the inter-processor communication information includes the bus technology used for communication between CPUs or between the CPU and the chipset and its maximum operating speed; the expansion interface performance includes the expansion interface type and the maximum operating speed; the power supply information includes the estimated power consumption of the motherboard when running at full load and the current requirements of the key power supply network.

5. The method for designing a server motherboard stack according to claim 2, wherein: The transmission rate of the high-speed signal is greater than or equal to 10 Gbps; The transmission rate of the low-speed signal is less than 10 Gbps.

6. The method for designing a server motherboard stack according to claim 5, characterized in that: The transmission rate of the high-speed signal is greater than or equal to 20 Gbps.

7. The method for designing a server motherboard stack according to claim 5, characterized in that: The first dielectric layer is R5775G substrate; The second dielectric layer is a TU872 substrate; The dielectric layer between the two power supply layers is a TU752 substrate.

8. The method for designing a server motherboard stack according to claim 1, characterized in that: According to the characteristic impedance of the server mainboard, the copper thickness of the conductive layer, the base material of the dielectric layer and the characteristic impedance calculation model, constructing the stacking model of the server mainboard stacking also includes: Selecting the copper thickness of the outermost conductive layer to be equal to the copper thickness of the signal layer; The dielectric layer between the outermost conductive layer and the corresponding ground layer and the dielectric layer between the signal layer close to the outermost conductive layer and the corresponding ground layer are selected to have the same base material.

9. The method for designing a server motherboard stack according to claim 1, characterized in that: Selecting a base material of the bonding layer in contact with the power layer to be the same as a base material of the dielectric layer between the two power layers; Selecting a bonding layer between the outermost conductive layer and the signal layer close to the outermost conductive layer to have the same base material as a dielectric layer between the signal layer close to the outermost conductive layer and the corresponding ground layer; The bonding layer between two adjacent signal layers is selected to have the same base material as that of the dielectric layer between the signal layer close to the power layer and the corresponding ground layer in the two adjacent signal layers.

10. A server motherboard stack, characterized in that: include: The server mainboard laminate is prepared according to the design method of the server mainboard laminate, and the design method of the server mainboard laminate is the design method of the server mainboard laminate according to any one of claims 1-9.

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