Defect analysis method and device for wafer bonding structure, and computer readable medium

Abstract

The invention provides a defect analysis method and device for a wafer bonding structure and a computer readable medium. The defect analysis method for the wafer bonding structure comprises the steps that the wafer bonding structure is provided; the wafer bonding structure comprises a first wafer and a second wafer which are stacked and arranged along a first direction; the first wafer comprises a side surface obtained by edge trimming; a bonding interface is arranged between the first wafer and the second wafer; acquiring an image of a defect area in the bonding interface; the defect area extends towards the radial direction of the bonding interface from a boundary line between the side surface and the bonding interface; the radial direction is perpendicular to the first direction; and dividing the image of the defect region into a plurality of sub-regions, and calculating the area of each sub-region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a defect analysis method and device for a wafer bonding structure, and a computer-readable medium. Background Art

[0002] With the development of large-scale integrated circuits, the characteristic size of circuits continues to shrink, and chips are developing in the three-dimensional direction into the post-Moore era to meet the needs of high integration, fast transmission speed, and low power consumption. One way to achieve three-dimensional integration of chips is to use wafer bonding technology to bond two wafers and then cut the wafer bonding structure into multiple chip bonding structures. After the wafer bonding process is completed, it is usually necessary to thin the back of at least one wafer to expose the circuit lead-out end in the wafer and further form a pad lead-out structure on the back of the wafer. However, after the back of the wafer is thinned by the grinding process, the edge of the wafer may become a weak point and may break or peel off in the subsequent process, which may cause contamination to the machine or other wafers. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a defect analysis method and device for a wafer bonding structure, and a computer-readable medium.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a defect analysis method for a wafer bonding structure, comprising:

[0006] A wafer bonding structure is provided; the wafer bonding structure comprises a first wafer and a second wafer stacked and arranged along a first direction; the first wafer comprises a side surface obtained by edge trimming; and a bonding interface is comprised between the first wafer and the second wafer;

[0007] Acquire an image of a defective region in the bonding interface; the defective region extends from a boundary line between the side surface and the bonding interface toward a radial direction of the bonding interface; the radial direction is perpendicular to the first direction;

[0008] The image of the defect region is divided into a plurality of sub-regions, and the area of ​​each of the sub-regions is calculated.

[0009] In an optional implementation, the acquiring an image of a defective region in the bonding interface includes:

[0010] The image of the defective area is acquired online by machine vision technology; the image of the defective area includes a first edge line corresponding to the boundary line between the defective area and the non-defective area in the bonding interface, and a second edge line corresponding to the boundary line between the side and the bonding interface.

[0011] In an optional implementation, dividing the image of the defect area into a plurality of sub-areas includes:

[0012] A plurality of dividing lines are defined; each of the dividing lines extends in a direction perpendicular to the second side line and includes a first endpoint located on the first side line and a second endpoint located on the second side line; the distance between each two adjacent second endpoints is equal; a sub-region is an area surrounded by two adjacent dividing lines, the first side line between the two first endpoints of the two adjacent dividing lines, and the second side line between the two second endpoints of the two adjacent dividing lines.

[0013] In an optional implementation, the number of the sub-areas is greater than or equal to 360.

[0014] In an optional implementation, the defect analysis method of the wafer bonding structure further includes:

[0015] The length of each of the dividing lines is measured.

[0016] In an optional implementation manner, calculating the area of ​​each of the sub-regions includes:

[0017] The area of ​​the sub-region is calculated according to the length of two adjacent dividing lines, the distance between the two first end points of the two adjacent dividing lines, and the distance between the two second end points of the two adjacent dividing lines.

[0018] In an optional embodiment, providing a wafer bonding structure includes:

[0019] bonding the first wafer to the second wafer;

[0020] Performing a thinning process on a surface of one side of the first wafer that is away from the second wafer on two opposite sides along the first direction;

[0021] The first wafer is edge trimmed to obtain the wafer bonding structure.

[0022] In an optional implementation, the defect analysis method of the wafer bonding structure further includes:

[0023] The area of ​​each of the sub-regions is compared with a preset threshold to obtain a defect analysis result of the wafer bonding structure.

[0024] In a second aspect, an embodiment of the present disclosure provides a defect analysis device for a wafer bonding structure, wherein the wafer bonding structure includes a first wafer and a second wafer stacked and arranged along a first direction; the first wafer includes a side surface obtained by edge trimming; the first wafer and the second wafer include a bonding interface; the defect analysis device includes:

[0025] an acquisition module, configured to: acquire an image of a defective region in the bonding interface; the defective region extends from a boundary line between the side surface and the bonding interface toward a radial direction of the bonding interface; the radial direction is perpendicular to the first direction;

[0026] The processing module is configured to: divide the image of the defect area into multiple sub-areas, and obtain the area of ​​each of the sub-areas.

[0027] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, the defect analysis method of the wafer bonding structure described in the above-mentioned embodiment is implemented.

[0028] In the technical solution provided in the present disclosure, the defect analysis method of the wafer bonding structure includes obtaining an image of a defect area in a bonding interface, dividing the image of the defect area into multiple sub-areas, calculating the area of ​​each sub-area and comparing the area of ​​the sub-area with a preset threshold value to obtain a defect analysis result of the wafer bonding structure. Through the defect analysis method, the extent of extension of cracks in the defect area in the bonding interface caused by edge trimming toward the radial direction of the bonding interface can be quantitatively analyzed online, thereby improving the accuracy and efficiency of defect analysis of the wafer bonding structure after edge trimming. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic flow chart of a defect analysis method for a wafer bonding structure provided by an embodiment of the present disclosure;

[0030] Figure 2 A schematic diagram of the formation process of the wafer bonding structure provided in the embodiment of the present disclosure Figure 1 ;

[0031] Figure 3 A schematic diagram of the formation process of the wafer bonding structure provided in the embodiment of the present disclosure Figure 2 ;

[0032] Figure 4 A schematic diagram of the formation process of the wafer bonding structure provided in the embodiment of the present disclosure Figure 3 ;

[0033] Figure 5A schematic diagram of an image of a defect area provided by an embodiment of the present disclosure;

[0034] Figure 6 A schematic diagram of the division of sub-areas provided in an embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of setting a standard line provided in an embodiment of the present disclosure;

[0036] Figure 8 An exemplary monitoring table provided for an embodiment of the present disclosure;

[0037] Fig. 9 An exemplary monitoring chart provided for an embodiment of the present disclosure;

[0038] Fig.10 A schematic diagram of a defect analysis device provided in an embodiment of the present disclosure;

[0039] Fig.11 Schematic diagram of a computer-readable medium provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0042] In the drawings, like reference numerals refer to like elements throughout.

[0043] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] With the development of large-scale integrated circuits, the characteristic size of circuits continues to shrink, and chips are developing in the three-dimensional direction into the post-Moore era to meet the needs of high integration, high transmission speed, low power consumption, etc. One way to achieve three-dimensional integration of chips is to use wafer bonding technology to bond two wafers and then cut the wafer bonding structure into multiple chip bonding structures. After the wafer bonding process is completed, it is usually necessary to thin the back of at least one wafer to expose the circuit lead-out end in the wafer and further form a pad lead-out structure on the back of the wafer. However, after the back of the wafer is thinned by the grinding process, the edge of the wafer may become a weak point and may break or peel off in the subsequent process, which may cause contamination to the machine or other wafers.

[0046] In some embodiments, the process of forming the wafer bonding structure may include edge trimming of the wafer after backside thinning to remove the edge portion of the wafer, thereby reducing the possibility of the edge portion of the wafer being broken or peeled off during subsequent processes. However, during the edge trimming process, the mechanical stress generated by the trimming tool on the wafer bonding structure may cause cracks to form on the bonding interface between the wafers.

[0047] In some embodiments, it is necessary to determine whether the extension of cracks in the bonding interface of the wafer bonding structure after edge trimming will have a significant impact on the product yield through offline slicing and photography and manual observation and judgment. On the one hand, this detection method will reduce production efficiency. On the other hand, manual observation and judgment are prone to misjudgment or missed judgment, and are not conducive to reducing production costs.

[0048] In view of the above problems, the present disclosure proposes the following implementations.

[0049] The present invention provides a defect analysis method for a wafer bonding structure. Figure 1 A schematic diagram of a defect analysis method for a wafer bonding structure provided by the present disclosure is shown in FIG. Figure 1 As shown, the defect analysis method of the wafer bonding structure includes the following steps:

[0050] Step S10: providing a wafer bonding structure; the wafer bonding structure comprises a first wafer and a second wafer stacked and arranged along a first direction; the first wafer comprises a side surface obtained by edge trimming; and the first wafer and the second wafer comprise a bonding interface;

[0051] Step S20: acquiring an image of a defect region in the bonding interface; the defect region extends from a boundary line between the side surface and the bonding interface toward a radial direction of the bonding interface; the radial direction is perpendicular to the first direction;

[0052] Step S30: Divide the image of the defect area into a plurality of sub-areas, and calculate the area of ​​each of the sub-areas.

[0053] In some embodiments, Figure 2 , Figure 3 and Figure 4 A schematic diagram of the structure of the formation process of the wafer bonding structure provided by the embodiment of the present disclosure, wherein: Figure 4 for Figure 3 Combined with reference Figure 2 , Figure 3 and Figure 4 , the specific process of performing step S10 may include: bonding the first wafer 101 to the second wafer 102; thinning the surface of one side of the first wafer 101 away from the second wafer 102 in the first direction; trimming the edge of the first wafer 101 to obtain the wafer bonding structure 100; the first wafer 101 includes a side surface 1011 obtained by edge trimming, and the first wafer 101 and the second wafer 102 include a bonding interface 103. Here, the first direction may be the Z direction.

[0054] In some specific examples, the first wafer 101 and the second wafer 102 may both include a circuit structure, and by bonding the first wafer 101 and the second wafer 102, an electrical connection between the circuit structure in the first wafer 101 and the circuit structure in the second wafer 102 may be achieved, thereby achieving three-dimensional integration of the circuit structure. Here, the circuit structure may include a storage array, a peripheral circuit, etc., and the present disclosure does not specifically limit this.

[0055] In the embodiment of the present disclosure, during the edge trimming process, a blade is required to cut the edge portion of the first wafer 101 along the first direction. During this process, the edge portion of the second wafer 102 may also be partially removed, and the mechanical stress generated by the blade on the wafer bonding structure 100 during the cutting process may cause a defective area to be generated in the bonding interface 103. The defective area extends from the boundary line between the side surface 1011 and the bonding interface 103 toward the radial direction of the bonding interface 103. Here, in combination with reference Figure 3 and Figure 4 , the bonding interface 103 can be approximately circular, and the radial direction of the bonding interface 103 is perpendicular to the first direction and points to the center of the bonding interface 103. If the extent of the defect area extending toward the radial direction of the bonding interface 103 is large, it may have a negative impact on the reliability of the connection between the first wafer 101 and the second wafer 102 and the circuit structure in the first wafer 101 and the second wafer 102. Therefore, a reliable defect analysis method is needed to analyze the extent of the defect area.

[0056] In some embodiments, the specific process of executing step S20 may include: acquiring an image of the defective area online through machine vision technology.

[0057] In a specific example, Figure 5 The image of the defect area is obtained online through machine vision technology, combined with the reference Figure 3 , Figure 4 and Figure 5 The image of the defective region includes a first edge line 201 corresponding to a boundary line between the defective region and the non-defective region in the bonding interface 103 , and a second edge line 202 corresponding to a boundary line between the side surface 1011 of the first wafer 101 and the bonding interface 103 .

[0058] In some specific examples, the process of acquiring an image of a defective area through machine vision technology may include: using a high-resolution image acquisition device to acquire an image of a wafer bonding structure, using a convolutional neural network to preprocess and extract features from the acquired image, and using a trained image recognition model to identify and locate the defective area. Among them, the preprocessing of the image may include operations such as noise reduction, standardization and normalization to enhance the contrast and clarity of the image, help remove irrelevant information in the image, and highlight the morphological features of the defective area; the feature extraction of the image may include feature extraction of the preprocessed image through a convolutional neural network, and the convolutional neural network gradually learns and extracts important features of the defective area from the image through a series of convolutional layers, pooling layers and fully connected layers, such as the boundary between the defective area and the non-defective area, and the boundary between the side of the first wafer and the bonding interface; the recognition of the defective area may include using a pre-trained image recognition model to identify the defective area, and the defect recognition model is a deep learning model. During the training process, the features of the defective area in different wafer bonding structures have been learned, so the defective area can be accurately identified; the positioning of the defective area may include further using a positioning algorithm to determine the position of the defective area after the defective area is identified, and using a geometric transformation and a registration algorithm to transform the image of the defective area into Figure 5 The images shown are for subsequent defect analysis.

[0059] In the disclosed embodiment, images of defective areas in the bonding interface can be acquired online by non-destructive means, so that the edge-trimmed wafer bonding structure can be monitored in real time, thereby improving the efficiency of defect analysis on the wafer bonding structure.

[0060] Continue to refer to Figure 5 The defective area may include multiple cracks extending in different directions, and the defective area is divided into multiple fragments of different sizes. The first edge line 201 corresponding to the boundary line between the defective area and the non-defective area is also irregular. If the degree of formation of the defective area is determined only by manual observation, it is difficult to formulate a unified analysis and judgment standard. Therefore, it is necessary to further conduct quantitative analysis of the defective area.

[0061] Reference Figure 6, the specific process of executing step S30 may include: defining a plurality of dividing lines 203 in the image of the defective area, each dividing line 203 extending in a direction perpendicular to the second edge line 202, and including a first endpoint A located on the first edge line 201 and a second endpoint B located on the second edge line 202, and the distance between each two adjacent second endpoints B is equal; a sub-area 204 is an area surrounded by two adjacent dividing lines 203, the first edge line 201 between the two first endpoints A of the two adjacent dividing lines 203, and the second edge line 202 between the two second endpoints B of the two adjacent dividing lines 203.

[0062] In some specific examples, the image of the defective area may be divided into a plurality of sub-areas 204 by defining a dividing line 203 , and the number of the sub-areas 204 is greater than or equal to 360.

[0063] In a specific example, the shape of the boundary line between the side 1011 of the first wafer 101 and the bonding interface 103 can be approximately circular, and the length of the second edge line 202 corresponding to the boundary line is the circumference of the circle. By defining the dividing line 203, the image of the defective area can be divided into 360 sub-areas 204, and the distance between the two second endpoints B of two adjacent dividing lines 203 is approximately equal to the arc length corresponding to the central angle of 1°.

[0064] In some embodiments, the defect analysis method of the wafer bonding structure further includes: measuring the length of each dividing line 203 .

[0065] In some embodiments, the specific process of executing step S30 may include: calculating the area S of the sub-region 204 based on the length of two adjacent dividing lines 203, the distance between the two first endpoints A of the two adjacent dividing lines 203, and the distance between the two second endpoints B of the two adjacent dividing lines 203.

[0066] In some specific examples, a straight line fitting may be performed on the line connecting the two first endpoints A of two adjacent dividing lines 203 , and the area S of each sub-region 204 may be obtained by integral calculation.

[0067] In some embodiments, the defect analysis method for a wafer bonding structure further includes: comparing the area S of each sub-region 204 with a preset threshold to obtain a defect analysis result of the wafer bonding structure.

[0068] In some specific examples, refer to Figure 7, a standard line CC' can be defined, and the area of ​​the area defined by the standard line CC' and the two adjacent dividing lines 203 and the second edge line 202 between the two end points B of the two adjacent dividing lines 203 is the preset threshold value S0. Here, for a wafer bonding structure, its preset threshold value S0 is fixed, and for different wafer bonding structures, the preset threshold value S0 may be different.

[0069] In a specific example, the setting position of the standard line CC' can correspond to the boundary line of the core area where the circuit structure is set in the wafer bonding structure. When the area S of the sub-area is greater than the preset threshold value S0, it can be considered that the crack in the defective area has extended to the core area of ​​the wafer bonding structure and may affect the yield of the circuit structure in the core area; when the area S of the sub-area is less than or equal to the preset threshold value S0, it can be considered that although cracks have occurred in the edge area of ​​the bonding interface after edge trimming, it will not have a significant impact on the circuit structure in the core area of ​​the wafer bonding structure.

[0070] In the embodiment of the present disclosure, the image of the defect area is divided into multiple sub-areas 204 by defining a dividing line 203, and the distances between each two adjacent second endpoints B are equal, that is, the range of the central angle covered by each sub-area 204 is equal, then the area S of each sub-area can reflect the severity of the extension of the cracks in the defect area in the radial direction of the bonding interface, that is, the defect analysis method provided by the present disclosure includes not only a qualitative analysis of the defect area, but also a quantitative analysis of the extension degree of the cracks in the defect area in the radial direction of the bonding interface. Compared with direct manual observation and judgment or only by obtaining an image of the entire defect area for qualitative analysis, it is conducive to formulating a unified analysis and judgment standard, thereby greatly improving the efficiency and accuracy of defect analysis of wafer bonding structures.

[0071] In some specific examples, the data collected online can also be linked to a defect management system, and related monitoring charts can be maintained in the defect management system to achieve automated monitoring of defect areas in the wafer bonding structure. Figure 8 and Fig. 9 This is an example of a monitoring chart maintained in a defect management system. It should be noted that the specific values ​​in the figure are only examples and are not intended to be specific limitations on the present disclosure.

[0072] In some specific examples, in the defect management system, based on the comparison result between the area S of the sub-region in the defective region and the preset threshold S0, the relevant alarm can be automatically triggered. For example, the alarm can be triggered when the area S of the sub-region is much larger than the preset threshold S0, or the alarm can be triggered when the number of sub-regions with an area S larger than the preset threshold S0 in the same wafer bonding structure exceeds the threshold. Through the automated monitoring of the defective region, the health of the edge trimming process can be fed back in time, and the alarm can be triggered in time when the health deteriorates, so as to avoid affecting the preparation of the next batch of wafer bonding structures.

[0073] In some specific examples, the defect analysis data of wafer bonding structures of different batches can also be maintained in the same monitoring chart, so as to intuitively reflect the differences in the degree of defect formation of wafer bonding structures of different batches, which is conducive to analyzing the reasons for the differences in yield of different batches of products.

[0074] In an embodiment of the present disclosure, a defect analysis method for a wafer bonding structure includes acquiring an image of a defect region in a bonding interface, dividing the image of the defect region into a plurality of sub-regions, calculating the area of ​​each sub-region and comparing the area of ​​the sub-region with a preset threshold value to obtain a defect analysis result of the wafer bonding structure. The defect analysis method can be used to quantitatively analyze and automatically monitor the defect region in the bonding interface caused by edge trimming online, thereby improving the efficiency and accuracy of defect analysis of the wafer bonding structure after edge trimming.

[0075] Based on a concept similar to the defect analysis method of the wafer bonding structure described above, the present disclosure also provides a defect analysis device for a wafer bonding structure. Figure 3 The wafer bonding structure 100 includes a first wafer 101 and a second wafer 102 stacked along a first direction; the first wafer 101 includes a side surface 1011 obtained by edge trimming; and a bonding interface 103 is included between the first wafer 101 and the second wafer 102.

[0076] In some embodiments, Fig.10 A schematic diagram of a defect analysis device for a wafer bonding structure provided by an embodiment of the present disclosure, such as Fig.10 As shown, the defect analysis device 300 includes: an acquisition module 301, configured to: acquire an image of a defect area in the bonding interface 103; the defect area extends from a boundary line between the side 1011 and the bonding interface 103 toward a radial direction of the bonding interface 103; the radial direction is perpendicular to the first direction; the processing module 302 is configured to: divide the image of the defect area into a plurality of sub-areas, and acquire the area of ​​each of the sub-areas.

[0077] In some embodiments, the acquisition module 301 is specifically configured to: acquire the image of the defective area online through machine vision technology. Figure 5 The image of the defective region includes a first edge line 201 corresponding to a boundary line between the defective region and a non-defective region in the bonding interface, and a second edge line 202 corresponding to a boundary line between the side surface and the bonding interface.

[0078] In some embodiments, reference Figure 6 The processing module 302 is specifically configured to: define multiple dividing lines 203; each of the dividing lines 203 extends in a direction perpendicular to the second edge line 202, and includes a first endpoint A located on the first edge line 201 and a second endpoint B located on the second edge line 202; the distance between each two adjacent second endpoints B is equal; a sub-area 204 is an area surrounded by two adjacent dividing lines 203, the first edge line 201 between the two first endpoints A of the two adjacent dividing lines 203, and the second edge line 202 between the two second endpoints B of the two adjacent dividing lines 203.

[0079] In some embodiments, the processing module 302 is also configured to: measure the length of each of the dividing lines 203; and calculate the area S of the sub-region 204 based on the lengths of two adjacent dividing lines 203, the distance between the two first endpoints A of the two adjacent dividing lines 203, and the distance between the two second endpoints B of the two adjacent dividing lines 203.

[0080] In some embodiments, the processing module 302 is further configured to: compare the area S of each of the sub-regions with a preset threshold S0 to obtain a defect analysis result of the wafer bonding structure.

[0081] Based on a concept similar to the above-mentioned defect analysis method for a wafer bonding structure, the present disclosure also provides a computer-readable medium. Fig.11 A schematic diagram of a computer readable medium provided in an embodiment of the present disclosure. A computer readable medium 401 stores a computer program, and when the computer program is executed by a processor 402, the defect analysis method of the wafer bonding structure in any of the above embodiments can be implemented.

[0082] In some specific embodiments, the computer readable medium 401 can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM) and other memories; it can also be various devices including one or any combination of the above memory devices.

[0083] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0085] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A defect analysis method for a wafer bonding structure, characterized in that: include: Provide wafer bonding structure; The wafer bonding structure comprises a first wafer and a second wafer stacked and arranged along a first direction; the first wafer comprises a side surface obtained by edge trimming; and a bonding interface is comprised between the first wafer and the second wafer; Acquire an image of a defective region in the bonding interface; the defective region extends from a boundary line between the side surface and the bonding interface toward a radial direction of the bonding interface; the radial direction is perpendicular to the first direction; The image of the defect region is divided into a plurality of sub-regions, and the area of ​​each of the sub-regions is calculated.

2. The defect analysis method of the wafer bonding structure according to claim 1, characterized in that: The acquiring an image of a defective area in the bonding interface comprises: The image of the defective area is acquired online by machine vision technology; the image of the defective area includes a first edge line corresponding to a boundary line between the defective area and a non-defective area in the bonding interface, and a second edge line corresponding to a boundary line between the side and the bonding interface.

3. The defect analysis method of wafer bonding structure according to claim 2, characterized in that: The step of dividing the image of the defective area into a plurality of sub-areas comprises: A plurality of dividing lines are defined; each of the dividing lines extends in a direction perpendicular to the second side line and includes a first endpoint located on the first side line and a second endpoint located on the second side line; the distance between each two adjacent second endpoints is equal; a sub-region is an area surrounded by two adjacent dividing lines, the first side line between the two first endpoints of the two adjacent dividing lines, and the second side line between the two second endpoints of the two adjacent dividing lines.

4. The defect analysis method of the wafer bonding structure according to claim 3, characterized in that: The number of the sub-areas is greater than or equal to 360.

5. The defect analysis method of wafer bonding structure according to claim 3, characterized in that: The defect analysis method of the wafer bonding structure further includes: The length of each of the dividing lines is measured.

6. The defect analysis method of the wafer bonding structure according to claim 5, characterized in that: The calculating the area of ​​each sub-region comprises: The area of ​​the sub-region is calculated according to the length of two adjacent dividing lines, the distance between the two first end points of the two adjacent dividing lines, and the distance between the two second end points of the two adjacent dividing lines.

7. The defect analysis method of wafer bonding structure according to claim 1, characterized in that: The wafer bonding structure provided comprises: bonding the first wafer to the second wafer; Performing a thinning process on a surface of one side of the first wafer that is away from the second wafer on two opposite sides along the first direction; The first wafer is edge trimmed to obtain the wafer bonding structure.

8. The defect analysis method of wafer bonding structure according to claim 1, characterized in that: The defect analysis method of the wafer bonding structure also includes: The area of ​​each of the sub-regions is compared with a preset threshold to obtain a defect analysis result of the wafer bonding structure.

9. A defect analysis device for a wafer bonding structure, characterized in that: The wafer bonding structure comprises a first wafer and a second wafer stacked and arranged along a first direction; the first wafer comprises a side surface obtained by edge trimming; and a bonding interface is comprised between the first wafer and the second wafer; The defect analysis device comprises: an acquisition module, configured to: acquire an image of a defective region in the bonding interface; the defective region extends from a boundary line between the side surface and the bonding interface toward a radial direction of the bonding interface; the radial direction is perpendicular to the first direction; The processing module is configured to: divide the image of the defect area into multiple sub-areas, and obtain the area of ​​each of the sub-areas.

10. A computer readable medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the defect analysis method of the wafer bonding structure according to any one of claims 1 to 8 is implemented.

Images